Commit graph

17 commits

Author SHA1 Message Date
Ryan McClelland 83c298cd32 drivers: spi: dw: define max-xfer-size
The max size was determined by looking at the ARCH of the cpu. This really
comes from the ip configuration when generated. Add `max-xfer-size`
property to the devicetree.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2024-01-20 13:11:42 +01:00
Ryan McClelland 330dba0861 drivers: spi: dw: fix naming convention of aux-reg
aux-reg should be defined with a hyphen in the bindings

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2024-01-20 13:11:42 +01:00
Daniel Leung 9f9b4a8afa uart: ns16550: use io-mapped DT property for IO port access
The old CONFIG_UART_NS16550_ACCESS_IOPORT has been used to
indicate whether to access the NS16550 UART via IO port
before device tree is used to describe hardware. Now we have
device tree, and we can specify whether a particular UART
needs to be accessed via IO port using property io-mapped.
Therefore, CONFIG_UART_NS16550_ACCESS_IOPORT is no longer
needed (and thus also CONFIG_UART_NS16550_SIMULT_ACCESS).
Remove these two kconfigs and modify code to use device tree
to figure out how to access the UART hardware.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-26 12:03:04 +02:00
Siyuan Cheng 4babd545cc drivers: pinctrl: add pinctrl driver for ARC emsdp
Add Synopsys ARC EMSDP board Pin controller for its Pmod
and Arduino shield interface.

Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-05-29 09:21:07 -04:00
Siyuan Cheng cbdd2f38da drivers: spi: add Data Fusion Subsystem SPI driver
Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI
driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll
SPI-Flash and DFSS SPI to connect external devices. Both drivers
share most source code, but DFSS uses ARC auxiliary registers.
Move FIFO depth setting to device tree.

Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-05-22 15:25:19 +02:00
Nikolay Agishev 0d8292ab6b ARC: Add HS4x support
Minimal HSDK4xD support

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2023-05-02 16:54:24 +02:00
Siyuan Cheng f9d155b7d5 dts: boards :emsdp: add SPI support
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.

Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-03-10 11:39:24 +01:00
Gerard Marull-Paretas b2a1eeb6ac soc: arc: define ICI in DT
ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded
in C files. This patch moves this information to Devicetree and updates
code to make use of it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 754c022fa2 soc: arc: snps_arc_iot: define sysconf in DT
sysconf base address was hardcoded in <soc.h>. Create a new compatible
and define it in Devicetree, where hardware needs to be described.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 5f40a9f40f soc: arc: synopsys: move secure timer0 definition to DT
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.

DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:

- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 44250fe3d3 soc: arch: synopsys: move timer0/1 IRQ information to DT
timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is
nowadays a better place to describe hardware. Note that I have followed
existing upstream Linux code to do these changes.

Ref.
- https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/
  hsdk.dts
- https://elixir.bootlin.com/linux/latest/source/Documentation/
  devicetree/bindings/timer/snps,arc-timer.txt

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Gerard Marull-Paretas 247d5acdf9 dts: arc: synopsys: move intc out of cpus node
interrupt controller is not a CPU, move it to the root node.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-03 07:46:14 -04:00
Kumar Gala b2f10ce0d0 dts: arc: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-20 09:23:45 -05:00
Kumar Gala 762eadc15d drivers: gpio: dw: rework init to use DT_INST_FOREACH_STATUS_OKAY
Use DT_INST_FOREACH_STATUS_OKAY to reduce duplicated code for each
instance.

We make interrupts optional since they aren't always available.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-14 10:31:42 +02:00
Gerard Marull-Paretas 4c8a8149de dts: add reg-shift property to all ns16550 devices
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).

This patch adds the property to all ns16550 nodes, with the following
values:

- 2 if SoC did not have any custom value defined by
  UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
  value (4=2, 2=1, 1=0).

These changes will allow simplifying the ns16550 driver.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 16:59:02 -05:00
Evgeniy Paltsev f81b3e03ac ARC: boards: HSDK: ged rid of pinmux usage
Pinmux is deprecated (see #39740) so let's get rid of
it's usage for HSDK board.

As we call pinmux only once at init phase we simply do
register setup in platform code instead of pinmux.

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2022-05-18 17:20:26 +02:00
Maureen Helm de514bb7d0 dts: arc: synopsys: Move SoC devicetree includes under a vendor dir
Cleans up SoC devicetree include file locations to follow the convention
of dts/<arch>/<vendor>/

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-05-09 17:54:48 -04:00