On USBHS, we cannot access the DWC2 register until VBUS is detected and
valid. Kernel event API is used to block if a valid VBUS signal is not
present when the user tries to force usbd_enable().
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The NUMDEVEPS field provides the number of endpoints in addition to the
control endpoint. It is used to iterate over GHWCFG1 register value to
get correct number of configured IN/OUT endpoints. To get it correctly,
we need to use it internally as number including control endpoint.
Interpretation of INEPS misses +1 because value 0 means 1 IN endpoint
and so on.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Rework and rename vendor quirks to better reflect where they intended to
be called. Number of quirks probably not final and will be trimmed
later.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move most of the controller initialization to a separate function called
during udc_enable(). This allows us to add support for the platform
where the device controller is only available when VBUS is present and
the PHY is powered.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Should increment `ch.chan_idx` instead of `channel_idx`,
otherwise we will be stucked in the loop forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
While running the following command:
aplay ... | arecord ...
multiple times, it was discovered that the SAI transmit
FIFO goes into underrun. This only happened in the
beginning, a few BCLK cycles after unmasking the transmit
data line. With the following flow:
1) Trigger start on RX
a) Do TX and RX software reset
b) Enable RX FIFO error interrupt
c) Enable RX DMA requests
d) Enable receive data line
e) Enable transmitter
f) Enable receiver
..... some time has passed .....
2) Trigger start on TX
a) Enable DMA requests
b) Enable transmit data line
and configuration in mind:
1) RX is SYNC with TX
2) TX is ASYNC
3) Each FSYNC edge is 32-bit wide
4) Each frame contains 2 32-bit words
this points to the following possibilites:
1) The transmitter is enabled so close to the
start of a new frame that even though the DMA requests
are asserted, the DMAC doesn't have enough time
to service them until the module goes into underrun
=> the timing is bad.
2) The transmitter is enabled somewhat close to
the start of a new frame such that the DMAC is not
fast enough to service the module until it goes into
underrun => DMAC is too slow AND the timing is bad.
Although the exact cause was not pinpointed, this patch
aims to fix the problem by writing a frame's worth of 0s
in the transmit FIFO. This way, even if we're dealing with
scenario 1) or 2), the DMAC has plenty of time to perform
the transfer (i.e: a frame), thus avoiding the underrun.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The vbat driver requires the adc node to be enabled:
```c
.adc = DEVICE_DT_GET(DT_INST_IO_CHANNELS_CTLR(inst))
```
Update its Kconfig to depend on `DT_HAS_ST_STM32_ADC_ENABLED`,
which is the `"st,stm32-adc"` compat that all ST ADC bindings
include, this will guarantee that at least one ADC node is
enabled, but not necessarily the ADC used by the vbat node.
To make sure that it at least compiles, we init the `adc`
pointer only if the specified ADC node is enabled, otherwise
it will points to `NULL`.
Finally, check if the `adc` points to `NULL` in
`stm32_vbat_init`. We are not relying on the existing
`device_is_ready` check because `DEVICE_DT_GET` will not
return `NULL` if the ADC is enabled. `adc == NULL` means
that the ADC node is not enabled in the devicetree.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
We have already code using toolchain provided __get_cpuid(), clean up
apic_tsc and make it consistent with the rest of the code.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Use a structured channel specifier rather than a single enum when
specifying channels to read in the new read/decoder API.
Replaces usages of a seperate channel and channel_index parameter
where previously used with a struct sensor_chan_spec.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Rework CMD12 failure logic for SDHC SPI driver. Previously, the error
code of CMD12 was not checked, so even if CMD12 failed to send the
initial command would be retried. Change this behavior to retry CMD12
until it succeeds. If CMD12 fails, its error code will be propagated to
the caller. Otherwise, the return code from the command being sent by
the caller will be propagated.
Fixes#72365
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Properly release SPI bus on transmit error within the SDHC SPI driver.
In these cases return code is not checked, as we wish to return the
error code from the failed transfer to the SD stack.
Fixes#72364
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RC32K and RCX low power clocks require runtime calibration to work
correctly.
Frequency of those clock can differ from chip to chip, one constant
value from Kconfig may not be best when low power clock (sourced
from RCX or RC32K) is used for system tick.
This code modifies global z_clock_hw_cycles_per_sec variable that
is used when TIMER_READS_ITS_FREQUENCY_AT_RUNTIME is enabled
in Kconfig.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This adds HCI driver which enables communication with CMAC core on
Renesas SmartBond DA1469x series. The CMAC core is running an Apache
NimBLE controller binary and uses shared memory for communcation via
mailboxes.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Add driver for TSic 206/306/316/506F/516/716 temperature sensor.
The driver uses PWM capture driver to read a single wire with
Manchester-like encoding.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Implement more robust handling for legacy SFDP tables, which may not
implement some of the JEDEC defined DWORDS for SFDP data. Instead of
failing to probe/initialize the flash when these DWORDS are not defined
in the basic flash parameter table, revert to sane defaults for SPI
flash.
Fixes#72051
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
`CONFIG_PM_DEVICE` being disabled does not mean that the `power-gpio`
does not need to be controlled.
Additionally, not having a `power-gpio` property does not mean that
power management is not supported, just that is has no work to do.
Signed-off-by: Jordan Yates <jordan@embeint.com>
In #72651, build fails due to conflict when enabling mbedTLS components.
Current Wi-Fi implementation for ESP32 can discard those selected cryptos.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The CDNS will report a M0 error if the data length is not what
it expects, but certain CCCs can have a variable length such as
GETMXDS and GETCAPS. This sets it up to ignore the M0 error if
it sees that ccc was GETMXDS or GETCAPS.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
GETSTATUS and GETMRL where not checking the right argc length. This
corrects it to check for the right count.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Misc fixes for the grtc timer driver:
* In non tickless mode:
* The tick time would drift a bit with each interrupt
* If something would cause a very significant delay
in handling the tick interrupt the number of announcements
would be incorrect
* Fortickless mode: The calculation of the next tick time
in sys_clock_set_timeout() was incorrectly done,
resulting in two spurious, too early, wakes of the kernel
before each correct wake. This caused tests/kernel/context/
to fail.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This puts the QSPI peripheral into memory-mapped mode when
CONFIG_STM32_MEMMAP is set. Writes and erase put it back into indirect
write mode.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This CONFIG_STM32_MEMMAP is for enabling the MemoryMapped mode
on external octo or quad spi memory.
In this case, the flash_stm32_read is done in mem map mode
the flash_stm32_erase is not available.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Check if the driver is suspended in gpio_keys_change_deferred(), this
avoids a potential situation where a race condition could try and read
from a pin that has just been disconnected.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When a sensor that depends on an ADC is enabled in devicetree, enable
the ADC subsystem. ADC is roughly equivalent to a bus for these sensors
(the mechanism through which data is transferred), which had the same
conversion applied in #48707.
The same benefits apply here, namely removing the need for the following
pattern in board `.kconfig` files:
```
configdefault ADC
default y if SENSOR
```
Signed-off-by: Jordan Yates <jordan@embeint.com>
Some stm32 devices with quadspi (like stm32l47x or stm32l48x)
does not support Dual-Flash Mode. Avoid building error even if
the &quadspi node has a <flash-id> property defined.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Set the default initial bitrates globally via Kconfig. The initial bitrates
can still be overridden using the "bus-speed" and "bus-speed-data"
devicetree properties.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
RCAR MMC driver previously had to report inaccurate maximum supported
frequency to SD subsystem so that the subsystem would select SDR104 mode
timing. Remove this logic, as it should no longer be needed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Michael Hope
