Commit graph

5555 commits

Author SHA1 Message Date
Andy Ross
b2e4283555 sys_clock: Make sys_clock_hw_cycles_per_tick() a proper API
This was another "global variable" API.  Give it function syntax too.
Also add a warning, because on nRF devices (at least) the cycle clock
runs in kHz and is too slow to give a precise answer here.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
Ioannis Glaropoulos
3fb6ea210a arch: arm: re-program MPU stack guard upon userspace enter
Before entering userspace, the MPU stack guard is
configured to guard the default (i.e. afterwards, the "user")
thread stack, as the privileged stack has not yet been set. Upon
entering userspace the MPU stack guard needs to be re-programmed
to the privileged stack, otherwise, there is a risk that the
first system call might be serviced without privileged stack
protection, if it occurs before any context-switch. This commit
fixes this issue, by calling configure_mpu_stack_guard(..) upon
userspace entering.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-15 12:19:09 -05:00
Yasushi SHOJI
6fc0d77432 arch: add big endian support
This patch adds Big Endian architecture support.  Even if a compiler
generating big endian object files is used, our linker script, or
include/linker/linker-tool-gcc.h to be precise, has default output
format as little endian.

This patch adds a hidden config CONFIG_BIG_ENDIAN, which should be set
by big endian architectures or a SoC's, and adds an condition to
switch OUTPUT_FORMAT in our linker.cmd.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2018-10-10 09:28:05 -04:00
Alberto Escolar Piedras
8eb51a309d POSIX arch: Add stub for sys_arch_reboot()
To allow apps to compile with CONFIG_REBOOT,
add a weak stub for sys_arch_reboot which does nothing
in the POSIX arch
POSIX boards may choose to provide a more sensible implementation
if relevant.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-10-09 16:15:45 -04:00
Anas Nashif
95d710ca41 arch: nxp_mpu: fix types in log macro
Fix format type in log message.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Anas Nashif
8e38670af3 arch: setup logging using new logger
Use the new logger framework for architecture code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Anas Nashif
eb29978a57 userspace: move KOBJECT/PRIVILEGED_STACK_TEXT_AREA to Kconfig
Instead of hardcoding in linker script, use a Kconfig and deal with
dependencies in Kconfig instead of directly in the linker file.

This patch moves both:
PRIVILEGED_STACK_TEXT_AREA
and
KOBJECT_TEXT_AREA

to arch/Kconfig.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 14:18:26 -04:00
Flavio Ceolin
78f27a81f5 kernel: Using the same paramenters names in a specific function
MISRA-C requires that all declarations of a specific function, or
object, use the same names and type qualifiers.

MISRA-C rule 8.3

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-28 07:58:19 +05:30
Mark Ruvald Pedersen
d67096da05 portability: Avoid void* arithmetics which is a GNU extension
Under GNU C, sizeof(void) = 1. This commit merely makes it explicit u8.

Pointer arithmetics over void types is:
 * A GNU C extension
 * Not supported by Clang
 * Illegal across all ISO C standards

See also: https://gcc.gnu.org/onlinedocs/gcc/Pointer-Arith.html

Signed-off-by: Mark Ruvald Pedersen <mped@oticon.com>
2018-09-28 07:57:28 +05:30
Alberto Escolar Piedras
013f279111 uart: Add driver for posix arch
Added a new UART driver for posix arch boards.
The driver can be configured to either attach to a new
pseudo-terminal, or to connect to the invoking shell
stdin-out.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-09-27 17:24:34 +02:00
Krzysztof Chruscinski
27459a13e4 arch: Add LOG_PANIC to fault handlers
Added LOG_PANIC to fault handlers to ensure that log is flush and
logger processes messages in a blocking way in fault handler.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2018-09-27 13:11:26 +05:30
Ioannis Glaropoulos
13a4d884f0 arch: arm: remove un-necessary inclusion of <string.h>
Remove the inclusion of <string.h>, if CONFIG_INIT_STACKS
is defined, because it is not required anywhere in thread.c.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-26 18:26:03 -05:00
Ioannis Glaropoulos
66192618a7 arch: arm: Minor style and typo fixes in inline comments
Several style and typo fixes in inline comments of arm kernel
files and thread.c.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:56:34 -07:00
Ioannis Glaropoulos
7d4339a920 arch: arm: add explanatory comment for SPLIM_NS set functions
This commit adds an inline explanatory comment in the API
for setting the non-secure stack-pointer limit registers, to
stress that the API is only applicable to Mainline ARMv8-M MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:55:41 -07:00
Ioannis Glaropoulos
98e38109c4 arch: arm: fix error reason intialization
This commit fixes a minor bug by setting the error reason
(to, default, _NANO_ERR_HW_EXCEPTION) for errors detected
during Secure/Non-Secure stack inspection. Applicable only
to Secure firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:55:41 -07:00
Ramakrishna Pallala
56117f9f91 arch: Kconfig: Add Kconfig options for Low Power States
Add Kconfig options for Low Power and Deep Sleep States which
need to be selected by the SoC's based on it's supported
Low Power States.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-20 10:20:23 -04:00
Piotr Zięcik
1c16cfcc30 arch: arm: Make ARM_MPU the sole option controlling MPU usage
This commit removes all MPU-related (ARM_CORE_MPU and NXP_MPU)
options exept ARM_MPU, which becomes master switch controlling
MPU support on ARM.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
d393186d51 arch: arm: Introduce CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options
This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options,
which indicate which flavour of MPU is supported by given SoC family.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Sebastian Bøe
1765276000 arch: arm: Use BL instead of B to jump to _PrepC
The __reset vector is using the 'b' instruction to jump to _PrepC. 'b'
can only jump 2KB on Cortex-M0 platforms so this causes build failures
when _PrepC happens to be too far away from __reset.

To resolve this we use 'bl' instead as it can jump two thousand times
further[0].

This can also be resolved by porting the reset vector to C or by
placing the _PrepC function in a dedicated section that the linker
places next to __reset.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0489e/Cihfddaf.html

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-09-19 09:13:50 -04:00
Alberto Escolar Piedras
ba5476a2a0 native_posix: Add control of traces color
For native_posix:
Added command line options to control if traces should have
or not colors.
+
Detect if we are connected to a tty or not, and if we are
set the defaults for that option appropriately

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-09-18 14:56:10 +02:00
Flavio Ceolin
4a211ec241 include: Add missing headers guard
Add missing headers guard

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Flavio Ceolin
67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Ioannis Glaropoulos
73e8454d17 arch: arm: remove power-of-two align and size requirement for ARMv8-m
The ARMv8-m Memory Protection Unit does not require MPU regions
to be power-of-two aligned and sized. This commit removes this
requirement when building for ARMv8-m MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-14 23:05:13 -04:00
Flavio Ceolin
da49f2e440 coccicnelle: Ignore return of memset
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.

The only directory excluded directory was ext/* since it contains
only imported code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Flavio Ceolin
5884c7f54b kernel: Explicitly ignoring _Swap return
Ignoring _Swap return where there is no treatment or nothing to do.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Flavio Ceolin
8a9ba10c2c kernel: swap: Fix __swap signature
__swap function was returning -EAGAIN in some case, though its return
value was declared as unsigned int.

This commit changes this function to return int since it can return a
negative value and its return was already been propagate as int.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Sebastian Bøe
d98e046a24 cmake: move ti_lm3s6965-specific code into the soc directory
As far as possible SoC-specific code should be contained to it's
directory and core systems should not be referencing specific
SoCs. This keeps the common code clean and makes it easier to maintain
out-of-tree SoCs.

To this end we move CONFIG_SOC_TI_LM3S6965_QEMU's soft-reset related
code out of arch/arm/core/cortex_m and into arch/arm/soc/ti_lm3s6965.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-14 10:22:20 -05:00
Anas Nashif
abcf2ad5a8 kconfig: move soc selection to ZEPHYR_BASE/soc/
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
563c161a80 posix: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
696aa869d5 nios2: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
279cc2e448 riscv32: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
f183444682 arc: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
70d819b405 arm: soc: move arm SoCs to top-dir
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
5744437d25 kconfig: adapt help messages for new location of SoC code
Point to the new location of the soc code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cff0005a87 x86: move soc/cpu to top-level under soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Paweł Zadrożniak
7c2197f2d8 boards: nrf: uart: Moved UART pin configuration to DTS (nRF boards)
UART pins (TX, RX, RTS, CTS) are now configured in DTS files.
RTS and CTS definitions are optional. If flow control is enabled
and RTS/CTS pins are not defined, then compiler will issue
an error message.

Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
2018-09-11 23:29:50 -05:00
Ulf Magnusson
d713033d5c Kconfig: Use new preprocessor syntax for env. variables
With the new Kconfig preprocessor (described in
https://github.com/torvalds/linux/blob/master/Documentation/kbuild/
kconfig-macro-language.txt), the syntax for expanding environment
variables is $(FOO) rather than $FOO.

$(FOO) is a general preprocessor variable expansion, which falls back to
environment variables if the variable isn't set (like in Make). It can
also be used in prompts, 'comment's, etc.

The old syntax will probably be supported forever in Kconfiglib for
backwards compatibility, but might as well make it consistent now that
people might start using the preprocessor more.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-09-11 19:17:25 -04:00
Ulf Magnusson
d0e8752a52 Kconfig: Rename $ENV_VAR_{ARCH,BOARD_DIR} to $ARCH/$BOARD_DIR
The prefixes might be a leftover from the old 'option env="..."' symbols
(which are no longer needed). Since environment variables can be
referenced directly now, there's no point in having a prefix.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-09-11 19:17:25 -04:00
David Brown
e0dda1b4b0 lib: posix: clock: Add gettimeofday() call
Provide an implementation of gettimeofday().  This uses clock_gettime()
with the CLOCK_REALTIME parameter, which is currently unimplemented, but
will allow clients to call this function once this functionality has
been implemented.

Signed-off-by: David Brown <david.brown@linaro.org>
2018-09-11 09:21:52 -04:00
Pawel Dunaj
c850ba8efa arch: arm: soc: nordic_nrf: nrf52: Add missing header
Add missing header required to use bool type.

Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
2018-09-11 08:43:53 -04:00
Maureen Helm
0439deeac6 arm: Clear primask and faultmask during startup
A bootloader may leave primask or faultmask set, so clear them during
startup when we enable interrupts and switch to the main thread.
Previously we only cleared primask for architecture variants which don't
support basepri, but now we do it for all architecture variants.

Fixes a failure on mimxrt1050_evk with the latency_measure test and
shell_module sample when using an nxp internal bootloader.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-11 08:36:57 -04:00
Filip Kubicz
990a0e8c71 dts: add SPI bindings for nRF family
This change adds DTS definition of SPI device for nRF chips.
It also removes SPI pin configuration from Kconfig and moves it to
chip DTS.

Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
2018-09-11 11:41:37 +02:00
Filip Kubicz
5c3992f34f dts: update I2C bindings for nRF chips
Change 'nRF5' family names to 'nRF' in I2C DTS.

Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
2018-09-11 11:41:37 +02:00
Daniel Leung
8708611fab adc: add native driver for Quark D2000
This adds a native ADC driver for Quark D2000.

Original: origin

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-05 18:38:57 -04:00
Sathish Kuttan
c5f04d7c24 arch: xtensa: remove extra #endif
Remove extra #endif that should have been removed when the
corresponding #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP was
removed in commit a2248782a2

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-09-04 14:27:33 -04:00
Anas Nashif
3298905bfe xtensa: removed obsolete headers
Went in by mistake in a bad rebase, fixes #9753.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-01 13:58:46 -04:00
Punit Vara
c995c4b42b dts: arc: Use dts tree for designware driver
Get required data from dts tree.

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-08-29 13:46:57 -04:00
Punit Vara
ef83943387 drivers: Use Designware driver for sensor subsystem
Remove adc_qmsi_ss to use designware driver for sensor subsystem

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-08-29 13:46:57 -04:00
Justin Watson
4e551aabb6 sam: adc: Updated SAM ADC driver.
Updated to work with new ADC API.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-08-29 13:46:57 -04:00
Andrzej Głąbek
0a97b5bf35 dts: nrf: Add ADC nodes and bindings for nRF SoCs
This commit adds ADC nodes to DTS files for nRF SoCs and introduces
corresponding  bindings for these nodes.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-08-29 13:46:57 -04:00
Yannis Damigos
d2e713f9ef arch: stm32l4: Enable gpio interrupts correctly
Enable gpio interrupts correctly and don't
disable the already enabled interrupts.

Fixes #9630

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-08-29 08:53:09 -04:00
Yannis Damigos
32a6fa1c58 arch: st_stm32: Remove I2C and SPI instances from common defconfig
Remove I2C and SPI instances when enabling I2C_STM32 and
SPI_STM32 drivers.

It allows to enable the drivers if ports I2C_4, SPI_4,
SPI_5, SPI_6 are selected.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-08-29 07:04:32 -05:00
Kiril Zyapkov
64b130683c arch: arm: stm32l4: add missing I2C_3 to dts.fixup
One can enable I2C_3 in kconfig and set status = "ok" in dts, but
the driver expects to find the config as fixed up with this
addition.

Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
2018-08-28 13:18:44 -05:00
David B. Kinder
1c29bff055 doc: fix kconfig misspellings
Fix misspellings in kconfig files missed during regular reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-08-28 13:58:46 -04:00
Adithya Baglody
511edf0175 Revert "sam_e70: enable instruction and data caches on sam_e70"
This reverts commit c0907762f3.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-28 13:46:47 -04:00
Anas Nashif
c0907762f3 sam_e70: enable instruction and data caches on sam_e70
The Cortex-M7 CPU included in the SAM e70 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization.

Fixes #8138

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-27 10:09:19 -04:00
Sebastian Bøe
69d8c1c08c syscalls: Correct the type of _k_syscall_table
_k_syscall_table is an array of function pointers and is declared as
such in C sources, this makes it an STT_OBJECT[0] in the symbol
table. But when the same symbol is declared in assembly, it is
declared to be a function, which would make the symbol an STT_FUNC.

When linking with LTO this type inconsistency results in the warning:

real-ld: Warning: type of symbol `_k_syscall_table' changed from 2 to
1 in /tmp/cc84ofK0.ltrans8.ltrans.o

To fix this warning we declare the table with GDATA instead of GTEXT,
which will change the type from 'function' to 'object'.

[0]
https://docs.oracle.com/cd/E19455-01/816-0559/chapter6-79797/index.html

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-08-26 08:54:27 -07:00
Aurelien Jarno
069d409b29 arch: arm: stm32: enable instruction and data caches on STM32F7
The Cortex-M7 CPU included in the STM32F7 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization. Note that the D-cache should only be enabled if it
is disabled, to workaround CMSIS issue #331.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-08-25 07:15:33 -07:00
Wayne Ren
0be1875e42 boards: cleanup and update the default config of arc boards
apply to snps arc boards

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-24 09:31:24 -07:00
Piotr Mienkowski
f69199777f soc: efr32fg1p: correct clock initialization sequence
This patch changes clock initialization sequence to initialize external
cristal oscillators only if it was not done before. Initialization of
external cristal oscillators may be performed by the bootloader.

Tested on BRD4250B evaluation board.

Fixes #9471

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2018-08-22 11:06:58 -05:00
Ramakrishna Pallala
1301cc636b arch: arm: nordic_nrf: Add an API to check for valid PM state
Add an API _sys_soc_is_valid_power_state to check if a PM state
is valid or not.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-08-22 08:07:14 -07:00
Wayne Ren
506f21b631 arch: arc: small optimization in mpu driver
to avoid _get_num_regions to access the aux
reg each time in the for loop

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
eab5ff725d arch: arc: put the init context into privileged stack
as the thread is created in privileged mode, the init
context should also be in privileged stack.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
fa9fb831ed arch: arc: re-orgnize the code in _new_thread
re-orginize the code in _new_thread to make it
easier to understand and maintain

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
a1504c3c0d arch: arc: set the right init status for user space
The fake exception return is used to jump to user mode.
So the init status of user thread is in exception mode.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
d68c016793 arch: arc: enable stack check when arc is in secure mode
when arc is in secure mode, SSC bit of sec_stat,
not SC bit of status32,is used to enable stack check.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
f3d2893344 arch: arc: stack check will be disabled in exception
stack check bit of status32/sec_stat will be cleared
automically in exception entry.

so remove the redundent codes

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Diego Sueiro
d1219f4e29 arch/mcimx7_m4: Add i.MX7 Solo Kconfig SoC partnumber define
Adds the proper Kconfig entries for the i.MX7S partnumber presented
on WaRP7 board.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-21 18:54:41 -05:00
Diego Sueiro
671cb652a1 arch/mcimx7_m4: Add pad, clock and gate config for GPIO7 and UART6
Adds the necessery configuration for using the GPIO7 and UART6 on
i.MX7 platforms.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-21 18:54:41 -05:00
Anas Nashif
483910ab4b systemview: add support natively using tracing hooks
Add needed hooks as a subsystem that can be enabled in any application.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
a2248782a2 kernel: event_logger: remove kernel_event_logger
Move to more generic tracing hooks that can be implemented in different
ways and do not interfere with the kernel.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
ac47070d10 tests: qmsi: remove soc watch sample
Remove this feature specific to QMSI and available through samples only
to allow for migration to tracing hooks.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
b6304e66f6 tracing: support generic tracing hooks
Define generic interface and hooks for tracing to replace
kernel_event_logger and existing tracing facilities with something more
common.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Adithya Baglody
1d27b404a6 tests: benchmarks: timing_info: Enable benchmarks for riscv32.
This patch provides support needed to get timing related
information from riscv32 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
79f65d4db7 tests: benchmarks: timing_info: Enable benchmarks for nios2.
This patch provides support needed to get timing related
information from nios2 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
bb918d85f8 tests: benchmarks: timing_info: Enable benchmarks for xtensa.
This patch provides support needed to get timing related
information from xtensa based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
022588e88d tests: benchmarks: timing_info: Enable benchmarks for ARC.
This patch provides support needed to get timing related
information from ARC based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
db0c5ca08b arch: arc: Added benchmark related hooks.
The benchmark application timing_info needs certain hooks to be
present in the kernel to get the accurate measurements. This
patch adds these hook at all the required locations.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
a8b0b0d5e8 benchmarks: timing_info: Add hooks in the kernel for userspace.
Added sampling hooks in the kernel needed for userspace benchmarks.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Ioannis Glaropoulos
6ee0ad2944 arch: arm: add ASSERT in _get_region_attr_by_type
This commit adds an __ASSERT line in _get_region_attr_by_type,
to signal an error if the supplied MPU region type is not valid.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
b956690520 arch: arm: mpu: explicitly add UL in numerical shift operations
This commit adds a UL suffix after numerical digits to ensure
the correctness of certain shift operations.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
2a1fe6e285 arch: arm: implement ARMv8-M MPU driver
This commit implements and integrates the ARMv8-M MPU driver
into the memory protection system for ARM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
2f0e722167 arch: arm: mpu: move ARMv7m-specific functions in internal header
This commit refactors arm_mpu.c by moving all internal function
implementation that is specific to ARMv7-M architecture to a
separate internal header file. This allows to easily extend
arm_mpu.c to support ARMv8-M by including all ARMv8-M-specific
implementation in a similar internal header.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
5a69648061 arch: arm: refactor _get_region_attr_by_conf(.) function
This commit refactors the _get_region_attr_by_conf(.) function,
so it does the following:
 - it is renamed to _get_ram_region_attr_by_conf(), to reflect
   that it is only used to configure RAM MPU regions.
 - it gets an arm_mpu_region_attr_t object structure pointer
   to fill-in with the derived region attributes.
 - it takes an additional argument (the region base address),
   which allows the function to have a common signature with the
   ARMv8-M version of it (where the attribute derivation needs
   the base address).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
829781d56e arch: arm: refactor _get_region_attr_by_type() function
This commit refactors the _get_region_attr_by_type(.) function,
so it does the following:
 - it takes an arm_mpu_region_attr_t object pointer and use it
   to fill-in the derived region attributes.
 - it performs only the distinguishing between the different MPU
    region types, hiding the actual MPU-specific implementation
	in internal functions.
 - it takes an additional argument (the region base address),
   which allows the function to have a common signature with the
   ARMv8-M version of it (where the attribute derivation needs
   the base address).
 - it returs 0 or succes and a negative non-zero integer
   to indicate an error.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
ff919d5fdb arch: arm: adapt region_init(.) to use arm_mpu_region_attr structure
This commit adapts the _region_init(.) function so it can use
the rasr field of the arm_mpu_region_attr structure, when it
configures the RASR register.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Sathish Kuttan
824bcaca52 xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000
Added routines for setting up resource ownership for
    DMA, I2S
Added routine to setup power gating and clock configuration

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-08-19 11:06:09 -07:00
Ulf Magnusson
21e63ed2ae arch: arm: kconfig: Remove redundant FLOAT dependencies
The choice that contains FP_HARDAPI and FP_SOFTAPI already depends on
FLOAT, so the choice symbols don't have to.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-18 07:54:20 -07:00
Daniel Leung
fc182430c0 kernel: userspace: reserve stack space to store local data
This enables reserving little space on the top of stack to store
data local to thread when CONFIG_USERSPACE. The first customer
of this is errno.

Note that ARC, due to how it lays out the user stack and
privilege stack, sets the pointer itself rather than
relying on the common way.

Fixes: #9067

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-08-17 09:40:52 -07:00
Mieszko Mierunski
4f6aac1a67 dts: nrf5: Changed GPIO and GPIOTE define names
Changed names using nrf5 to nrf for consistency with other drivers.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
15813d343c boards: nrf: Changed GPIO default driver to NRFX shim
I removed GPIO configuration from board files and enabled them
as default in driver Kconfig file. All boards had GPIO ports
enabled that is why I decided to enable it by default.

Power management example was changed to use new driver.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
6d8220d27f drivers: gpio: Add shim for nrfx GPIO and GPIOTE drivers
Added shim implementation gpio_nrfx.c which uses nrfx drivers
for GPIO and GPIOTE

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
e99e363cc0 dts: nrf: Added DTS support for nRF51
DTS for nRF51 was missing, I updated soc and board files to
support DTS properly.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Flavio Ceolin
8aec087268 kernel: Fix bitwise operators with unsigned operators
Bitwise operators should be used only with unsigned integer operands
because the result os bitwise operations on signed integers are
implementation-defined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-08-16 19:47:41 -07:00
Flavio Ceolin
0866d18d03 irq: Fix irq_lock api usage
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.

In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-08-16 19:47:41 -07:00
Olivier Martin
945ef745e0 dts/rtc: Introduce binding for STM32 RTC
This commit adds rtc fixup and dts blocks for RTC hardware
on STM32L4.

Signed-off-by: Olivier Martin <olivier.martin@proglove.de>
2018-08-16 13:38:43 -07:00
Kiril Zyapkov
0d47ae4fca drivers: rtc: add support for STM32 RTC
Add support for the STM32 Real-Time-Clock leveraging the LL APIs

Signed-off-by: Johannes Hutter <johannes@proglove.de>
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
2018-08-16 13:38:43 -07:00
Nathaniel Graff
218d7a0aa9 riscv: Rename the FE310 SoC to Sifive Freedom
FE310 is the name of one SoC out of a range of products in the SiFive
Freedom line. The FE310 SoC port in Zephyr is compatible with all of
these products, so rename the SoC to SiFive Freedom

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-16 06:23:01 -07:00
Istvan Bisz
ea9d4a79c9 drivers: usb: add support for USB OTG FS on STM32F2
Add support for usbotg_fs, by adding the DT fixup, pinmux macros,
and the DT entries in stm32f2.dtsi.

Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
2018-08-16 06:19:19 -07:00
Sebastian Bøe
1186f5bb29 cmake: Deprecate the 2 symbols _SYSCALL_{LIMIT,BAD}
There exist two symbols that became equivalent when PR #9383 was
merged; _SYSCALL_LIMIT and K_SYSCALL_LIMIT. This patch deprecates the
redundant _SYSCALL_LIMIT symbol.

_SYSCALL_LIMIT was initally introduced because before PR #9383 was
merged K_SYSCALL_LIMIT was an enum, which couldn't be included into
assembly files. PR #9383 converted it into a define, which can be
included into assembly files, making _SYSCALL_LIMIT redundant.

Likewise for _SYSCALL_BAD.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-08-15 11:46:51 -07:00
Nathaniel Graff
970cfdb88b arch: riscv32: Move MEPC increment in irq_wrapper
Move the MEPC increment logic in __irq_wrapper such that the saved MEPC
is only incremented on a syscall (ecall instruction).

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 08:07:41 -05:00
Ulf Magnusson
8cf8db3a73 Kconfig: Use a short, consistent style for prompts
Consistently use

    config FOO
            bool/int/hex/string "Prompt text"

instead of

    config FOO
            bool/int/hex/string
            prompt "Prompt text"

(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).

The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.

Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/
how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-15 04:10:10 -07:00
Ioannis Glaropoulos
bb0b66e15a arch: arm: clean-up "default n" entries in Kconfig option definitions
This commit removes the depreciated "default n" entries from
boolean K-config options in arch/arm.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-15 04:09:16 -07:00
Ulf Magnusson
17f1b0adec Kconfig: Switch to improved globbing statements
A design flaw of 'gsource' is that there's no way to require at least
one file to match the glob pattern. This could lead to silent errors.

Switch to a new design, where a plain 'source' is globbing and requires
at least one file to match. A separate 'osource' (optional source)
statement is available for cases where it's okay for a pattern (or plain
filename) to not match any files.

'orsource' combines 'osource' and 'rsource' (relative source).

This commit search-replaces 'gsource' with 'source', but backwards
compatibility with 'gsource' is still maintained by making it an alias
for 'osource' (and by making 'grsource' an alias for 'orsource').

The three Kconfig files arch/{nios2,posix,xtensa}/Kconfig source
arch/{nios2,posix,xtensa}/soc/*/Kconfig, which doesn't match any files.
Use 'osource' for those. The soc/*/Kconfig files seem to be for
additional SoC-specific symbols, only none exist yet on those ARCHes.

Also use 'osource' for the source of $ENV_VAR_BOARD_DIR/Kconfig in
boards/Kconfig, which doesn't exist for all boards.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-15 04:07:44 -07:00
David Lamparter
c4703661e6 arch: arm: soc: add STM32L433
The L433 chip is a superset of the L432, just grabbing a few additional
interfaces (LCD, I2C2, USART3, SPI2, SDMMC).  All the support/HAL files
are already there, so enabling these is just a matter of build system
setup.

Tested on an application specific board (builds correctly and I2C2
works.)  I unfortunately don't have a nucleo/discovery board to create a
reference board for.

Signed-off-by: David Lamparter <equinox@diac24.net>
2018-08-13 18:59:17 -07:00
Ioannis Glaropoulos
f2bdee356b arch: arm: export entry veneers
When building a Secure firmware image, instruct the linker to
generate a symbol table with the entry veneers, to allow a Non
Secure firmware image to access Secure Entry functions via the
entry veneers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
db3f6aab02 arch: arm: add option to define an NSC region
This commit adds K-config options that allow the user to
signify an ARM Secure Firmware that contains Secure Entry
functions and to define the starting address of the linker
section that will contain the Secure Entry functions. It
also instructs the linker to append the NSC section if
instructed so by the user.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
3b79b283f9 arch: arm: API & implementation of SAU region configuration
This commit contribute an internal ARM API that enables the
user to confgure an ARM Security Attribution Unit region. It
also defines ARM_SAU as a K-config option to indicate that
an MCU implements the ARM SAU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
6e93eea3a3 arch: arm: api to permit/block NS system reset requests
This commit contributes a simple API to allow the TrustZone
user to block or permit Non-Secure System Reset requests.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
d9cfbc280f arch: arm: macro API for defining non-secure entry functions
This commit introduces an internal ARM macro API to allow the
TrustZone user to define Non-Secure entry functions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
a05081804a arch: arm: API macros for CMSE non-secure function pointers
This commit defines and implements and internal ARM macro API
that allows the TrustZone user to declare, define, and evaluate
pointers of non-secure function type.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
f8b5046b13 arch: arm: include GCC -mcmse compile option for secure firmware
Make GCC compile with the -mcmse compile option, if we are
building a Secure firmware. The option will make Security
Extensions for secure executables available, and will set
the corresponding compile-time indicator flag, accordingly:
(i.e. __ARM_FEATURE_CMSE=3).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
ba02c6d91e arch: arm: api for reading MCU SAU regions
Define and implement a function to read the number of
SAU regions configued for the MCU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
5bb3d01580 arch: arm: API to configure Secure exception boost
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to select whether Secure exceptions will
have priority boosting over Non-Secure exceptions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
179b8d15f1 arch: arm: API to configure fault target state
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to configure the target state of fault
exceptions that are not banked between security states.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
28acaeadc9 arch: arm: add macro definition for vector key write permit value
This commit adds a macro definition for the Vector Key value of
AIRCR register that permits the accompanying writes. The macro
is then used instead of the hard-coded numerical value.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
97d5f60afb arch: arm: configure NS stack pointer limit registers
This commit adds and implements an ARM internal API function
to configure the Non-Secure instance of MSPLIM or PSPLIM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
de78430072 arch: arm: internal API to enable/disable SAU
This commit defines and implements the internal ARM TrustZone
API to enable or disable the Security Attribution Unit.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
034499af1a arch: arm: configure non-secure registers from secure firmware
Define and implement an API to configure the Non-Secure instances
of core registers in ARM Cortex-M23 and Cortex-M33.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Paul Sokolovsky
028aae1ec9 net: config: Rename Kconfig options to correspond to library name
This finishes refactor of splitting off net_config library name from
net_app library, started in c60df1311, c89a06dbc. This commit makes
sure that Kconfig options are prefixed with CONFIG_NET_CONFIG_
instead of CONFIG_NET_APP_, and propagates these changes thru the
app configs in the tree.

Also, minor dependency, etc. tweaks are made.

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2018-08-13 18:42:31 -07:00
Nathaniel Graff
45d5d5db48 boards: riscv: Convert HiFive1 to DTS
Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and
riscv,plic0.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 18:35:38 -05:00
Ioannis Glaropoulos
b996955e34 arch: arm: optimize _size_to_mpu_rasr_size function
This commit optimizes _size_to_mpu_rasr_size(.) in the ARMv7-M
MPU driver, so it makes use of a single _builtin_clz() function
call, instead of two.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 13:00:30 -07:00
Ulf Magnusson
ec3eff57e0 Kconfig: Use the first default with a satisfied condition
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.

There are at least three problems with the patch:

  1. It's inconsistent with how Kconfig works in other projects, which
     might confuse newcomers.

  2. Due to oversights, earlier 'range' properties are still preferred,
     as well as earlier 'default' properties on choices.

     In addition to being inconsistent, this makes it impossible to
     override 'range' properties and choice 'default' properties if the
     base definition of the symbol/choice already has 'range'/'default'
     properties.

     I've seen errors caused by the inconsistency, and I suspect there
     are more.

  3. A fork of Kconfiglib that adds the patch needs to be maintained.

Get rid of the patch and go back to standard Kconfig behavior, as
follows:

  1. Include the Kconfig.defconfig files first instead of last in
     Kconfig.zephyr.

  2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
     last in arch/Kconfig.

  3. Include arch/<arch>/soc/*/Kconfig first instead of last in
     arch/<arch>/Kconfig.

  4. Swap a few other 'source's to preserve behavior for some scattered
     symbols with multiple definitions.

     Swap 'source's in some no-op cases too, where it might match the
     intent.

  5. Reverse the defaults on symbol definitions that have more than one
     default.

     Skip defaults that are mutually exclusive, e.g. where each default
     has an 'if <some board>' condition. They are already safe.

  6. Remove the prefer-later-defaults patch from Kconfiglib.

Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions

As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).

This commit includes some default-related cleanups as well:

  - Simplify some symbol definitions, e.g. where a default has 'if FOO'
    when the symbol already has 'depends on FOO'.

  - Remove some redundant 'default ""' for string symbols. This is the
    implicit default.

Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).

Piggyback some fixes for style nits too, e.g. unindented help texts.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-10 12:38:28 -07:00
Diego Sueiro
9283ee7acc arch: i.MX add RDC peripheral permission setting for applications cores
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).

This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.

The settings are defined at devicetree level and applied in the soc.c.

A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-09 10:17:32 -05:00
Wayne Ren
37cc2ccc0f arch: arc: fix a bug in mpu driver
for mpu stack guard, after arc_core_mpu_configure,
it should return

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-06 09:40:56 -05:00
Michael Scott
65af15bcc2 boards: arm: nrf52840_pca10056: add settings for WNC-M14A2A modem
These settings enable use of the WNC-M14A2A LTE-M modem as the default
network interface for the nRF52840-DK board (nrf52840_pca10056).

They include the following settings when MODEM_WNCM14A2A is selected:
- UARTE1 pin setup
- DTS / DTS fixup additions for WNC-M14A2A
- Kconfig settings for modem driver

Signed-off-by: Michael Scott <mike@foundries.io>
2018-08-06 10:43:46 +03:00
qianfan Zhao
eab3f3f27f arm: _FaultShow: fix typo MMFSR -> UFSR
The right param should be SCB_UFSR not SCB_MMFSR

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-08-03 08:41:22 -05:00
Kumar Gala
4b22ba7e4b syscall: Move arch specific syscall code into its own header
Split out the arch specific syscall code to reduce include pollution
from other arch related headers.  For example on ARM its possible to get
errno.h included via SoC specific headers.  Which created an interesting
compile issue because of the order of syscall & errno/errno syscall
inclusion.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-08-02 22:06:49 -05:00
Alberto Escolar Piedras
11aa0b8006 posix arch: Do not disable warnings
Initially missing function prototypes warnings and undefined macro
warnings  were disabled to quickly prototype the posix arch and
native_posix board.
But there is no excuse anymore to have this warnings disabled.
=> enable them.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
4388cde90f arch posix: Allow including XOPEN extensions
The native_posix random driver uses random() and srandom()
whicha are old XOPEN POSIX extension (part of POSIX 2001).

To avoid compiler warnings due to the host libC headers
not including this prototypes otherwise, let's define
this 2 macros.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
00b07615fa native_posix: Add missing headers and function prototypes
A few function prototypes were missing in the native_posix
board and its drivers.
Let's add them.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
c0ea40cd74 posix arch: Add missing header
Add missing header in posix arch file

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Ulf Magnusson
d1684a83a4 Kconfig: Clean up some symbol definitions
- Remove redundant 'n' defaults. 'n' is the default value for bool
  symbols.

  This makes the auto-generated documentation clearer as well: You get
  "implicitly defaults to n" instead of
  "- n if <propagated dependencies>".

- Shorten

      <type>
      prompt "foo"

  to

      <type> "foo"

  This works for all types, not just bool.

- Various formatting nits.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-01 12:47:17 -04:00
Anas Nashif
9426a3cbf9 arch: x86: set output format/arch per arch
Instead of doing this per platform, set the output format and arch on
architecture level.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-31 20:30:33 -04:00
Andrew Boie
b1dec2992e arc: add z_arch_user_string_nlen
Safely measure the length of a potentially dubious string.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Andrew Boie
3cef6deb16 arm: add z_arch_user_string_nlen
Uses fixup infrastructure to safely abort if we get an MPU
fault when examining a string passed in from user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Andrew Boie
9d3cdb3568 x86: add z_arch_user_string_nlen
Uses fixup infrastructure to safely abort if we get a page
fault while measuring a string passed in from user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Alberto Escolar Piedras
550225b668 native: Generalize native tasks
Some drivers or tests need to execute some code before Zephyr is
booted, dynamically register command line arguments, etc.

For this purpose, we generalize the NATIVE_EXIT_TASK to also
provide hooks to run a function at a given point during the startup
of native_posix.

Also, test/boards/native_posix/exit_tasks is generalized to cover
this new functionality.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-30 22:13:46 -04:00
Daniel Leung
b3e68703b5 arch/x86: apollo_lake: add PCI related bits for UARTs/I2Cs
This adds PCI related configuration for UARTs and I2C controllers
to the Apollo Lake SoC configuration to support PCI devices.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Daniel Leung
88f4b68165 arch/x86: apollo_lake: add MMU regions for I2C controllers
The Apollo Lake SoC has 8 I2C controllers. The MMU regions are
added to allow access.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Daniel Leung
67b48ab2a8 drivers/i2c: i2c_dw: extends driver to support 8 controllers
This adds the necessary driver structs to support a total of 8
I2C controllers. This also allows each I2C controller to have
its own PCI vendor/device IDs.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Yannis Damigos
fe321f02fa arch: st_stm32: Fix IRQs number of various SoCs
It corrects the IRQs number of various SoCs.
IRQs number is in conformity with the IRQn_Type
enumeration in SoC header files of STM32Cube
HAL.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-26 08:24:04 -05:00
Andrew Boie
97c06a7ab3 arm: fix assembler offset errors on Cortex-M0
In some kernel configurations, the offset can be greater
than the maximum of 124 for ldr/str immediate offsets.

Fixes: #9113

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-25 20:04:29 -04:00
Shawn Mosley
573f32b6d2 userspace: compartmentalized app memory organization
Summary: revised attempt at addressing issue 6290.  The
following provides an alternative to using
CONFIG_APPLICATION_MEMORY by compartmentalizing data into
Memory Domains.  Dependent on MPU limitations, supports
compartmentalized Memory Domains for 1...N logical
applications.  This is considered an initial attempt at
designing flexible compartmentalized Memory Domains for
multiple logical applications and, with the provided python
script and edited CMakeLists.txt, provides support for power
of 2 aligned MPU architectures.

Overview: The current patch uses qualifiers to group data into
subsections.  The qualifier usage allows for dynamic subsection
creation and affords the developer a large amount of flexibility
in the grouping, naming, and size of the resulting partitions and
domains that are built on these subsections. By additional macro
calls, functions are created that help calculate the size,
address, and permissions for the subsections and enable the
developer to control application data in specified partitions and
memory domains.

Background: Initial attempts focused on creating a single
section in the linker script that then contained internally
grouped variables/data to allow MPU/MMU alignment and protection.
This did not provide additional functionality beyond
CONFIG_APPLICATION_MEMORY as we were unable to reliably group
data or determine their grouping via exported linker symbols.
Thus, the resulting decision was made to dynamically create
subsections using the current qualifier method. An attempt to
group the data by object file was tested, but found that this
broke applications such as ztest where two object files are
created: ztest and main.  This also creates an issue of grouping
the two object files together in the same memory domain while
also allowing for compartmenting other data among threads.

Because it is not possible to know a) the name of the partition
and thus the symbol in the linker, b) the size of all the data
in the subsection, nor c) the overall number of partitions
created by the developer, it was not feasible to align the
subsections at compile time without using dynamically generated
linker script for MPU architectures requiring power of 2
alignment.

In order to provide support for MPU architectures that require a
power of 2 alignment, a python script is run at build prior to
when linker_priv_stacks.cmd is generated.  This script scans the
built object files for all possible partitions and the names given
to them. It then generates a linker file (app_smem.ld) that is
included in the main linker.ld file.  This app_smem.ld allows the
compiler and linker to then create each subsection and align to
the next power of 2.

Usage:
 - Requires: app_memory/app_memdomain.h .
 - _app_dmem(id) marks a variable to be placed into a data
section for memory partition id.
 - _app_bmem(id) marks a variable to be placed into a bss
section for memory partition id.
 - These are seen in the linker.map as "data_smem_id" and
"data_smem_idb".
 - To create a k_mem_partition, call the macro
app_mem_partition(part0) where "part0" is the name then used to
refer to that partition. This macro only creates a function and
necessary data structures for the later "initialization".
 - To create a memory domain for the partition, the macro
app_mem_domain(dom0) is called where "dom0" is the name then
used for the memory domain.
 - To initialize the partition (effectively adding the partition
to a linked list), init_part_part0() is called. This is followed
by init_app_memory(), which walks all partitions in the linked
list and calculates the sizes for each partition.
 - Once the partition is initialized, the domain can be
initialized with init_domain_dom0(part0) which initializes the
domain with partition part0.
 - After the domain has been initialized, the current thread
can be added using add_thread_dom0(k_current_get()).
 - The code used in ztests ans kernel/init has been added under
a conditional #ifdef to isolate the code from other tests.
The userspace test CMakeLists.txt file has commands to insert
the CONFIG_APP_SHARED_MEM definition into the required build
targets.
  Example:
        /* create partition at top of file outside functions */
        app_mem_partition(part0);
        /* create domain */
        app_mem_domain(dom0);
        _app_dmem(dom0) int var1;
        _app_bmem(dom0) static volatile int var2;

        int main()
        {
                init_part_part0();
                init_app_memory();
                init_domain_dom0(part0);
                add_thread_dom0(k_current_get());
                ...
        }

 - If multiple partitions are being created, a variadic
preprocessor macro can be used as provided in
app_macro_support.h:

        FOR_EACH(app_mem_partition, part0, part1, part2);

or, for multiple domains, similarly:

        FOR_EACH(app_mem_domain, dom0, dom1);

Similarly, the init_part_* can also be used in the macro:

        FOR_EACH(init_part, part0, part1, part2);

Testing:
 - This has been successfully tested on qemu_x86 and the
ARM frdm_k64f board.  It compiles and builds power of 2
aligned subsections for the linker script on the 96b_carbon
boards.  These power of 2 alignments have been checked by
hand and are viewable in the zephyr.map file that is
produced during build. However, due to a shortage of
available MPU regions on the 96b_carbon board, we are unable
to test this.
 - When run on the 96b_carbon board, the test suite will
enter execution, but each individaul test will fail due to
an MPU FAULT.  This is expected as the required number of
MPU regions exceeds the number allowed due to the static
allocation. As the MPU driver does not detect this issue,
the fault occurs because the data being accessed has been
placed outside the active MPU region.
 - This now compiles successfully for the ARC boards
em_starterkit_em7d and em_starterkit_em7d_v22. However,
as we lack ARC hardware to run this build on, we are unable
to test this build.

Current known issues:
1) While the script and edited CMakeLists.txt creates the
ability to align to the next power of 2, this does not
address the shortage of available MPU regions on certain
devices (e.g. 96b_carbon).  In testing the APB and PPB
regions were commented out.
2) checkpatch.pl lists several issues regarding the
following:
a) Complex macros. The FOR_EACH macros as defined in
app_macro_support.h are listed as complex macros needing
parentheses.  Adding parentheses breaks their
functionality, and we have otherwise been unable to
resolve the reported error.
b) __aligned() preferred. The _app_dmem_pad() and
_app_bmem_pad() macros give warnings that __aligned()
is preferred. Prior iterations had this implementation,
which resulted in errors due to "complex macros".
c) Trailing semicolon. The macro init_part(name) has
a trailing semicolon as the semicolon is needed for the
inlined macro call that is generated when this macro
expands.

Update: updated to alternative CONFIG_APPLCATION_MEMORY.
Added config option CONFIG_APP_SHARED_MEM to enable a new section
app_smem to contain the shared memory component.  This commit
seperates the Kconfig definition from the definition used for the
conditional code.  The change is in response to changes in the
way the build system treats definitions.  The python script used
to generate a linker script for app_smem was also midified to
simplify the alignment directives.  A default linker script
app_smem.ld was added to remove the conditional includes dependency
on CONFIG_APP_SHARED_MEM.  By addining the default linker script
the prebuild stages link properly prior to the python script running

Signed-off-by: Joshua Domagalski <jedomag@tycho.nsa.gov>
Signed-off-by: Shawn Mosley <smmosle@tycho.nsa.gov>
2018-07-25 12:02:01 -07:00
Aurelien Jarno
97bc5abedf drivers: i2c: stm32: add support for STM32F7
The STM32F7 uses the V2 version of the STM32 I2C controller. Add the
corresponding Kconfig, DTS, DTS fixup and pinmux entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-25 07:19:12 -04:00
Yannis Damigos
302494d35a arch: stm32f4/f7: Add OTG HS defines to dts fixup file
Add OTG HS defines to dts fixup file for STM32 F4 and
F7 series

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-24 22:27:17 -04:00
Zide Chen
98775f34c3 kconfig: decouple realmode boot from CONFIG_JAIHOUSE
Add CONFIG_REALMODE item so that it's possible to configure other
x86 boards to boot from real mode.

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-07-24 15:37:09 -07:00
Ioannis Glaropoulos
90b64489e5 arch: arm: allow processor to ignore/recover from faults
This commit adds the implementation that allows the ARM CPU
to recover from (otherwise fatal) MPU faults. A new error
reason, _NANO_ERR_RECOVERABLE, is introduced. The error
reason is used to suppress fault dump information, if the
error is actually recoverable.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
f713fa5d52 arch: arm: re-organize arm fault handling
This commit does several things:
- It unifies the way the fault inspection is implemented,
  irrespective of the selected fault dumping level.
- It removes the dumping of the Thread ID and faulting
  instruction address, as these are now displayed by
  _NanoFatalErrorHandler.
- It introduces a new debug print directive, to be used
  for the highest dumping level (2).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
afef645279 arch: arm: Call NanoFatalErrorHandler and split out Secure stack dump
This commit implements two changes.
- It splits out the dumping of the Secure stack information to a
  separate function. Dumping will only occur if the highest dump
  level has been selected.
- Forces _Fault() to invoke _NanoFatalErrorHandler, instead of
  _SysFatalErrorHandler. In addition, early return statemets are
  implemented in _Fault(), so the fatal error handler is only
  invoked once.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
f4645561f9 arch: arm: improve documentation of _Fault(.)
This commit improves the documentation of function _Fault(.),
in order to better describe the actual implementation and the
use of the function arguments.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Andrew Boie
17282578a9 arc: fix update of ERET on exc return
This code path for returning from an exception wasn't
updating ERET with ESF->pc, resulting in any updates to
the PC by the fault handler being ignored.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-20 14:13:09 -04:00
Ramakrishna Pallala
fe48f743f3 arch: arc: Fix Deep Sleep hang issue on Quark SE(ARC)
Fixed the RTC interrupt masking issue on Deep Sleep entry by
explicitly unmasking it on Deep Sleep exit sequence.

Re-oredered the SoC power states such that SYS_POWER_STATE_CPU_LPS is
the lowest possible Low Power State(LPS) and SYS_POWER_STATE_CPU_LPS_2
is the highest possible Low Power State(LPS). This is need to maintain
the LPS state consistency across different architectures.

Also re-mapped the Low Power States and Deep Sleep States as per
Quark SE C1000 data sheet document under Power Management section.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-19 17:12:58 -04:00
Ramakrishna Pallala
2e615181f0 arch: x86: Reorder the SoC power states for Quark SE
Re-oredered the SoC power states such that SYS_POWER_STATE_CPU_LPS is
the lowest possible Low Power State(LPS) and SYS_POWER_STATE_CPU_LPS_2
is the highest possible Low Power State(LPS). This is need to maintain
the LPS state consistency across different architectures.

Also removed the redundant SYS_POWER_STATE_DEEP_SLEEP_2 state.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-19 17:12:58 -04:00
Niranjhana N
414c39fc94 posix: add pthread_key and pthread_once APIs
Added 4 new pthread_key APIs for thread-specific data
key creation, deletion, setting and getting the values.

Added a key list to the posix_struct for threads.

Added pthread_once API.

Signed-off-by: Niranjhana N <niranjhana.n@intel.com>
2018-07-19 08:46:33 -04:00
Alberto Escolar Piedras
15d847add8 native: Add NATIVE_EXIT_TASK hooks
Some of the native application components or drivers need to
do a proper cleanup before the executable exits.
So we provide a macro similar to SYS_INIT but which will be
called just before exiting.
This can be used for freeing up resources, closing descriptors,
or doing any neccessary signaling to any other host process.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-18 15:43:12 -04:00
Andrei Emeltchenko
8a86931e8a board: quark_se_c1000: Add default setting for cc2520 radio
Add default settings for cc2520 radio.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2018-07-18 08:23:00 -04:00
Diego Sueiro
d99f6ada84 arch: Add support for i.MX PWM
Adds definitions, devicetree entries and clock controller
configurations for PWM peripheral.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-17 16:08:22 -05:00
Diego Sueiro
c2454309de arch: Add i.MX7 PWM get clock frequency function
This patch adds the get_pwm_clock_freq function to be used by the
i.MX PWM driver.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-17 16:08:22 -05:00
Daniel Leung
26e83aab35 arch/x86/soc: add SoC configuration for Apollo Lake
This adds the SoC configuration for Apollo Lake. This is based
on the Atom configuration.

Origin: Original

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 16:27:52 -04:00
Ioannis Glaropoulos
6e41f9e181 arch: arm: enable/disable MPU using API functions
This commit forces arm_mpu_init() to use the provided API
functions to enable and disable the MPU. Besides the clean-up
the commit enforces the MPU driver to use data and instruction
synchronization barriers every time the MPU is enabled. This
is aligned with the programming recommendations by ARM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-16 20:56:25 -04:00
Anas Nashif
942ab7ed35 esp32: include register headers in soc.h
This fixes a build issue on esp32 that was introduced recently with the
merge of an old PR.

Include the register headers in soc.h rather than soc.c and make them
available to other code via soc.h

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-16 19:00:32 -04:00
Ramakrishna Pallala
a20cc9e78b arch: arm: nrf52: Enable interrupts on wake up from sleep
Enable the interrupts on wake up from low power states

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-15 22:48:34 -04:00
Vitor Massaru Iha
f8718758e5 include: drivers: gpio: Turn functions generic - esp32
On 'drivers/i2c_esp32.c' there are functions useful for other
drivers. Functions and struct went moved to:

 * arch/xtensa/soc/esp32/peripheral.h
 * arch/xtensa/soc/esp32/soc.h
 * include/drivers/gpio/gpio_esp32.h

Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>
2018-07-15 16:13:36 -04:00
Jakub Rzeszutko
f0de6e06f8 drivers: serial: nrf: Serial driver modification to use DT
1. dts.fixup files updated with peripheral address and IRQ NUMBER.
2. Peripheral address is taken from DT.
3. IRQ number is taken from DT.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-07-13 11:08:03 +02:00
Ulf Magnusson
3cb9018e23 arch: x86: Kconfig: Fix CACHE_LINE_SIZE default for CPU_ATOM
With Zephyr's prefer-later-defaults behavior, the default value of
CACHE_LINE_SIZE was always 0, because 'default 0' acts like
'default 0 if y'.

Change the code to what was probably the intention (default to 0 unless
CPU_ATOM).

It looks like CACHE_LINE_SIZE is never used in the code when
CACHE_LINE_SIZE_DETECT is on, so maybe things could be simplified
further.

Piggy-back some prompt style consistency cleanups.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-07-12 23:08:43 -04:00
Ioannis Glaropoulos
8bfddb52e5 arch: arm: mpu: fix _get_region_ap(.) function
This commit fixes a bug in _get_region_ap(.) by adding
parentheses to enforce the correct operator precedence.

Fixes #8864.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-12 13:00:37 -05:00
Aurelien Jarno
9107e3dac8 drivers: usb: add support for USB OTG FS on STM32F7
The STM32F7 uses the same USB OTG FS controller than the STM32F4 series.
It is therefore trivial to add support for it, by adding the DT fixup
and pinmux macros, and the DT entries in stm32f7.dtsi. Keep it disabled,
it should be enabled at the board level.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-11 16:28:10 -05:00
Aurelien Jarno
8d1664c2f7 arch: arm: mpu: enable WBWA caching on per thread user RAM
Update _get_region_attr_by_type used to set up the user regions
on a per thread basis to match the REGION_USER_RAM_ATTR macro. Caching
attributes were set "Outer and inner write-through. No write allocate.",
this patch changes it to "Outer and inner write-back. Write and read
allocate.".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-11 10:55:31 -04:00
Wayne Ren
d27aadf941 arch: arc: add nsim support in soc
add nsim soc support, two configs are contained

* em with arc MPUv2
* em with arc SecureShield and MPUv3

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-07-10 19:05:13 -04:00
Kumar Gala
d76e39f8d3 arch: atmel_sam0: Fix Kconfig warnings
We were missing a few SOC_PART_NUMBER.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 15:28:32 -05:00
Sean Nyekjaer
781a2f0275 arch: add support SAMD20 used in the SAMD20 Xplained Pro Board
This add basic support the SAMD20 inkl. SPI and UART

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
2018-07-10 12:56:44 -05:00
Sean Nyekjaer
31aaf07719 arch: atmel_sam0: move clk config options to common Kconfig
The SAMD0 Family have almost the same clock options.
The samd20 and samd21 only clocks is not implemented yet.

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 12:56:44 -05:00
Christian Taedcke
6d5206e7b0 arm: exx32: Add additional include to efm32wg soc.h
This keeps the efm32wg soc.h in sync with the efr32fg1p soc.h.
This include is currently not necessary, but will be for further
peripheral drivers.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-07-10 12:53:50 -05:00
Christian Taedcke
496b799474 arm: exx32: Add Silabs EFR32FG1P soc files
The Silicon Labs EFR32FG1 Flex Gecko MCU includes:
	* Cortex-M4F core at 40MHz
	* up to 256KB of flash and 32KB of RAM
	* integrated Sub-GHz and/or 2.4GHz radio
	* multiple low power peripherals

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-07-10 12:53:50 -05:00
Maureen Helm
530a71310e arm: nxp: mpu: Consolidate k64 mpu regions
Reduces the number of mpu regions statically reserved at boot time by
one, giving a total of five. We originally sought to reduce the total to
three: 1 background region with lowest precendence for supervisor r/w, 1
flash region, and 1 sram region. However, the nxp mpu hardware does not
give precedence to any region over another, and thus we cannot revoke
access from the background region with a higher priority region. This
means we cannot support hardware stack protection with a single
background region.

Instead, create two background regions that cover the entire address
space, except for sram.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-07-10 12:46:04 -04:00
Kumar Gala
b3d34d2e4c arch: arm: nrf52: Support UARTE defines in dts.fixup
If we select UART0 as UARTE we will get different defines from the
generation script.  Support both UART and UARTE for UART0.  Also fixup
UART1 defines since this will always be UARTE.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 08:54:30 -05:00
Diego Sueiro
970c4f9cf3 arch: Add imx7d_m4 i2c definitions
Adds all necessary i2c definitions and configurations for imx7d_m4 soc.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-06 15:55:57 -05:00
Yong Jin
8776835bd6 arch: arm: stm32: add basic support for STM32F769 SoC
The STM32F769 has more interrupts and features than the STM32F746,
but the basic support is similar with STM32F746

Signed-off-by: Yong Jin <jinyong.iot@foxmail.com>
2018-07-06 09:56:25 -05:00
Istvan Bisz
5aaf827a3e arch: arm: stm32f2: remove core zephyr header inclusions from soc.h
The stm32f2 version of soc.h misses the changes done in commit
aee97be ("arch: arm: soc: remove core zephyr header inclusions
from soc.h").

Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
2018-07-06 09:47:18 -05:00
Yannis Damigos
4e26f9c3a6 arch: stm32f0/f1/f3/l0: remove core zephyr header inclusions
Apply the changes done in commit aee97be to F0, F1, F3, L0 series.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-06 09:46:09 -05:00
Maureen Helm
41dd6622ce arm: Print NXP MPU error information in BusFault dump
The NXP MPU triggers a bus fault when a memory access error occurs. Add
support in the bus fault handler to dump error details from the NXP MPU,
including the port number, mode (supervisor or user), address, bus
master number, and regions.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-07-05 13:42:40 -05:00
Kumar Gala
889b290a98 arch: arm: beetle: Pull in CMSDK header for CMSIS support on Beetle
Pulled CMSDK_BEETLE.h from mbed-os as a starting point to enable CMSIS
support on Beetle.  Trimed the file down that what we need on Zephyr
(dropped Device Specific Peripheral Section and system_CMSDK_BEETLE.h).

This lets us drop soc_mpu.h which duplicates MPU info that is defined in
CMSIS headers.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-05 13:40:27 -05:00
qianfan Zhao
7e2f6ebc7b stm32f2: add stm32f207xe soc
Used and tested(blinky, hello_world) on out of tree custom board.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
bdeece01b8 driver: uart_stm32: add support for stm32f2 series
clear RXNE flag in fifo_read, remove TEACK and REACK
check when uart_stm32_init because stm32f2 doesn't
has those flags.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
dffac9ab74 driver: interrupt_controller: Add support for stm32f2
Add kconfig and c code for stm32f2 interrupt controller driver

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6fb7b04461 drivers: stm32-gpio: Provide GPIO driver for stm32f2
Add necessary GPIO defines for the stm32f2 series soc

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6091a7fd50 drivers: clock_control: Add support for stm32f2
Add clock control support for the stm32f2

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
85d2633af2 stm32f2: add stm32f207xg soc
Add stm32f207xg soc to make nucleo-f207zg work.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6511c4122d arm: stm32f2: Add support for stm32f2 series
Add necessary kconfig and DTS files for stm32f2 series

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
Findlay Feng
a36bd915af arch: ARM: Change the march used by cortex-m0 and cortex-m0plus
Use -march=armv6s-m to ensure the svc directive exists

Signed-off-by: Findlay Feng <i@fengch.me>
2018-07-04 16:46:40 -04:00
Ioannis Glaropoulos
df41ed885a arch: arm: mpu: replace literals with CMSIS bitsets
This commit refactors internal functions in arm_mpu.c to use
bitsets and functions taken directly from ARM CMSIS instead of
hardcoded arithmetic literals. In several internal functions
some part of the implementation is abstracted further in inline
functions or convenience macros, to facilitate extending the
arm_mpu.c for ARMv8-M. In addition, the commit adds minor
improvements in internal function documentation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
d1944109a9 arch: arm: abstract MPU attribute generation in inline function
This commit abstracts the attribution generation for an MPU
region, determined based on a supplied configuration and the
given size, from the actual implementation, which is placed
in a separate inline function. This allows to have multiple
implementations of attribution generation for different ARM
MPU drivers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
2b79fceb84 arch: arm: refactor _region_init(..) function
This commit refactors the _region_init(..) internal MPU driver
function so it gets the region index and a struct arm_mpu_region
as aruments. The latter holds the MPU region configuration that
is to be applied to the region determined by the index argument.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
e202e04499 arch: arm: nrf: conditionally compile mpu_regions.c
This commit enforces conditional compilation of mpu_regions.c
in nrf52/CMakeLists.txt depending on whether ARM_MPU_NRF52X
K-option is defined.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:21:58 -04:00
Aurelien Jarno
5aa09c6baa drivers: entropy: stm32: add support for STM32F7
All the STM32F7 SoCs have a TRNG. Adding support for it is just a matter
of tweaking the #ifdef and including the right file from HAL.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-03 22:48:08 -04:00
Ioannis Glaropoulos
1ed37e77ce arch: arm: beetle: duplicate ARM MPU registers' definition
Duplicate the ARM MPU-related registers' definitions
specifically for Beetle SOC which is not compliant with
ARM CMSIS and does not include the ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 18:43:10 -04:00
Ioannis Glaropoulos
559249ee01 arch: arm: Remove redundant HAL definition for ARM MPU
This commit removes the redundant HAL definition for the ARM
Cortex-M MPU registers, and modifies the ARM MPU driver
implementation to directly use the provided HAL from CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 18:43:10 -04:00
Sebastian Bøe
347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Ioannis Glaropoulos
d20dac8254 arch: arm: minor refactor in arm_core_mpu_configure_user_context
This commit refactors arm_core_mpu_configure_user_context() so
it can use directly arm_core_mpu_configure().

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 17:11:14 -04:00
Ioannis Glaropoulos
33d3f14b15 arch: arm: add compile-time guards for arm_mpu code
This commit places all the implementation in arm_mpu.c within
build-time guards, ensuring that it is compiled-in only if the
kernel features requiring MPU are present (i.e. USERSPACE,
APPLICATION_MEMORY, or MPU_STACK_GUARDS). An exception to that
is the code required for MPU initialization, which is left out,
as MPU initialization occurs always if MPU is present.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 17:11:14 -04:00
Leandro Pereira
91220ba640 boards: native_posix: Add option to build with Address Sanitizer
Address Sanitizer helps finding issues related to memory: buffer
overflows, usage of uninitialized memory, etc.  This is available in
both Clang and GCC for a while, and, since the POSIX port is only
meant for testing, this will help find issues.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-03 17:06:25 -04:00
Aurelien Jarno
6ee562b754 arch: arm: stm32: add basic support for STM32F723 SoC
The STM32F723 has more interrupts than the STM32F746 due to the
additional SDMMC controller. Besides that the changes are very
similar to the ones of the STM32F746.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-03 13:53:36 -05:00
Ioannis Glaropoulos
059952c8e1 arch: arm: update compile options for DSP
This commit updates the compile options in cmake to distinguish
between ARMv8-M Mainline MCUs with or withouth the optional DSP
extension. A new Kconfig option: ARMV8_M_DSP, is introduced, to
signify the use of an ARMv8-M MCU with DSP support.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 12:17:13 -05:00
Piotr Zięcik
97adff57f1 arch: arm: nrf: Enable SEGGER RTT on all Nordic SoCs
All chips from nRF51 and nRF52 series support Segger RTT,
so we can enable it if given series is used.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-07-03 17:51:50 +02:00
Ioannis Glaropoulos
e325510d59 arch: arm: nrf: minor header files' clean up in soc/nrfx
This commit cleans up source files in soc/nrf51 soc/nrf52
folders by removing unnecessary header inclusions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-02 16:50:10 +02:00
Ioannis Glaropoulos
0677812910 arch: arm: nrf: remove kernel_includes.h from nRF5x soc.h inclusions
This commit removes the inclusion of kernel_includes.h from
the nRF51 and nRF52 soc.h headers. This prevents from an
inclusion cycle formation on soc.h. In the wake of
kernel_includes.h removal, necessary header files have been
added in several source files to be able to compile Zephyr for
nRF5x SOCs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-02 16:50:10 +02:00
Anas Nashif
bebda565b5 clang: fix for x86 iamcu
Clang, build IAMCU with -miamcu.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-01 22:58:09 +02:00
Anas Nashif
72edc4e15f clang/llvm: add initial configuration file for clang
Add an LLVM backend and a clang toolchain variant to support building
with llvm coming with popular Linux distributions.

This has been tested with X86 boards:
- quark_d2000_crb
- quark_se_c1000_devboard/Arduino 101

Use:

export ZEPHYR_TOOLCHAIN_VARIANT=clang

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-01 22:58:09 +02:00
Ioannis Glaropoulos
7c9a1f0f76 arch: arm: soc: add explanatory comment for kernel headers' inclusion
This commit adds an explanatory comment in all soc.h headers,
where kernel_includes.h header has been included, to stress out
that this header must be included after SOC-specific headers are
brought in. The reason is the fact that kernel_includes.h needs
the ARM CMSIS definitions, which are brought in by the
SOC-specific header inclusions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-29 17:53:15 -05:00
Aurelien Jarno
fa83a4d131 arch: arm: stm32f7: remove core zephyr header inclusions from soc.h
The stm32f7 version of soc.h misses the changes done in commit
aee97be710 ("arch: arm: soc: remove core zephyr header inclusions
from soc.h") as it was not merged at that time. Fix that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-29 11:52:51 -05:00
Alberto Escolar Piedras
2889f5f02c native: Do not ignore format-truncation warnings
Reverting 5124711d87
as issue #5732 is no more.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-06-28 19:58:55 +02:00
Kumar Gala
e860775873 Revert "arch: arm: stm32: correct include issue"
This reverts commit 30529da0e4.

We should include SoC headers from HALs before we include
kernel_includes.h.  On ARM this is needed because we tend to get CMSIS
related defines setup by the HAL headers.

Fixes: #8593

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-06-28 10:54:38 -05:00
Yurii Hamann
1fdc790ca2 serial: stm32: STM32F7 UART support
The patch adds serial driver support for STM32F7 family
microcontrollers, includes pinmux definitions and DTS fixup file.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
a229500d23 drivers: gpio: stm32: STM32F7 GPIO support
This patch adds GPIO support for STM32F7 family microcontrollers.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
cfb25c74a0 drivers: flash: stm32: STM32F7 flash memory suport
Added flash memory support for STM32F7 family microcontrollers

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
4df673f3fc drivers: clock_control: STM32F7 family clock control
This patch adds clock control support for STM32F7 family
microcontrollers.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
7d8d280db3 arch: arm: stm32: Basic STM32F7 family support
The patch includes support for STM32F746xG subfamily.
Related to issue #6981.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
qianfan Zhao
e7205be03d arch: stm32: Enable HAS_SEGGER_RTT on all stm32 SoCs
Enable HAS_SEGGER_RTT to allow user to select use of SEGGER RTT
and SystemView solution.

SEGGER provide a firmware that can convent ST-Link to J-Link,
And RTT is supports all stm32 SoCs, so lets enable RTT default

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-06-27 15:48:38 -05:00
Andrew Boie
8bcffefb33 arch: arm: clean up MPU code for ARM and NXP
* We are now *much* better at not reserving unnecessary
system MPU regions based on configuration. The #defines
for intent are now an enumerated type. As a bonus, the
implementation of _get_region_index_by_type() is much
simpler. Previously we were wasting regions for stack guard
and application memory if they were not configured.

* NXP MPU doesn't reserve the last region if HW stack
protection isn't enabled.

* Certain parts of the MPU code are now properly ifdef'd
based on configuration.

* THREAD_STACK_REGION and THREAD_STACK_USER_REGION was a
confusing construction and has now been replaced with
just THREAD_STACK_REGION, which represents the MPU region
for a user mode thread stack. Supervisor mode stacks
do not require an MPU region.

* The bounds of CONFIG_APPLICATION_MEMORY never changes
and we just do it once during initialization instead of
every context switch.

* Assertions have been added to catch out-of-bounds cases.

Fixes: #7384

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-06-27 12:56:38 -07:00
Christophe Priouzeau
30529da0e4 arch: arm: stm32: correct include issue
This commit correct the issue introduce by aee97be which
changed the order of header inclusion that lead
to warning generation at compilation, that truend into errors
in CI.
This commit reinstantiate the initial header inclusion order.

Fixes #8563
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
2018-06-27 12:35:27 -05:00
Ulf Magnusson
f1f1fb41bd arch: arm: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Also simplify the definition of CC3220SF_DEBUG. 'default's can be other
symbols too, not just literal values. The condition for the symbol to be
visible (user-configurable) can be put directly on the prompt as well.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
f428d8dacf arch: arc: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Also fix the 'default' on XIP. Due to Zephyr's prefer-later-defaults
behavior, it was always set to 'y' (when the dependencies were
satisfied).

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
8cb6fb7223 arch: xtensa: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
b0156b2c48 arch: nios: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
81d61601a8 arch: riscv32: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
87ecbe7f48 arch: x86: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
aed5e360ee arch/Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Sebastian Bøe
a1e806bf44 gen_isr_tables: Delete the dead code accompanying .intList.num_isrs
intList has been populated with the number of isrs, aka interrupts,
but nothing has not been using this information so we drop it and
everything used to construct it.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-25 12:54:49 -07:00
Carles Cufi
0f6bd5c891 arch: arm: nrf: Add support for the nRF52810
The nRF52810 is a low-cost variant of the nRF52832, with a reduced set
of peripherals and memory. This commit adds basic support for it in the
arch SoC and dts folders.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
2018-06-25 19:34:33 +02:00
Maureen Helm
54d1a608ff imxrt1050: Disable low-power modes
The imxrt1050 is configured to use SYSTICK for the kernel timer, but
SYSTICK cannot wake up the soc from low-power modes. Disable low-power
modes on this soc until we have support for an alternative timer.

This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An
earlier version of the board (EVK, not EVKB), had A0 silicon which
by default did not enter low-power mode on a wfi.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-23 11:00:20 +02:00
Johann Fischer
c36e800e8e usb: remove all CONFIG_*_EP_ADDR options
Remove all CONFIG_*_EP_ADDR options but keep the default
values for it, as they are necessary to find ep_addr in
usb_ep_cfg_data associated with bEndpointAddress in
interface descriptor.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-06-22 12:30:55 -04:00
Ioannis Glaropoulos
aee97be710 arch: arm: soc: remove core zephyr header inclusions from soc.h
This commit removes the direct inclusions of device.h or gpio.h
from soc.h header files in ARM SOCs, to avoid soc.h include
kernel.h.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-21 22:28:00 +02:00
Bartosz Sokolski
92778e4438 arch: soc: nrf52: add UART1 to dts fixup
Current fixup supports only UART0 while there is also UART1

Signed-off-by: Bartosz Sokolski <bartosz.sokolski@nordicsemi.no>
2018-06-21 13:49:13 +02:00
Sebastian Bøe
aed0b6c4bd isr_tables: Simplify how the sw_irq_handler function is used
This is a migration from using code generation to using the C language
which we in the general case we should aways strive towards.

It is equivalent to the simplification that was done with
_irq_spurious here:
https://github.com/zephyrproject-rtos/zephyr/pull/7574

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-20 15:39:29 -04:00
Joakim Andersson
5204fd7061 arch: arm: Set Zero Latency IRQ to priority level zero:
Set Zero Latency IRQ to priority level zero and SVCs to priority level
one when Zero Latency IRQ is enabled.
This makes Zero Zatency truly zero latency when the kernel has been
configured with userspace enabled, or when IRQ offloading is used.

Exceptions can still delay Zero Latency IRQ, but this is considered
ok since exceptions indicate a serious error, and the system needs to
recover.

Fixes: #7869

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2018-06-20 18:05:02 +02:00
Karol Gugala
1765d75ff4 riscv32: riscv-privilege: Microsemi Mi-V support
This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-20 11:57:07 -04:00
Karol Gugala
23a5b5d171 riscv32: riscv-privilege: integrate common code
This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-20 11:57:07 -04:00
Mieszko Mierunski
dc1c2742b6 boards: nrf: Moved SDA and SCL pin configuration to DTS for nRF boards
SDA and SCL pins can now be configured through DTS.
Pins on development kits have been assigned according to arduino
headers.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-06-20 13:38:18 +02:00
Stanislav Poboril
631eedd334 arch: Add imx6sx m4 soc support
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one
Cortex A9 core and one Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A9 core (running Linux) via RPMsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A9 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A9 can perform these steps at bootloader level after the Linux
system has booted.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-06-19 17:08:51 -05:00
Sebastian Bøe
8f321b48ac isr_tables: Simplify how the spurious irq function address is found
Instead of finding the address of the spurious irq function in the
intList section we now rely on the linker to find the address in the
_irq_spurious symbol.

This is a migration from using code generation to using the C language
which we in the general case we should aways strive towards.

In this specific case it makes the generated code 'irq_tables.c'
easier to read as we replace magic numbers with the &_irq_spurious
token.

Also, the path through the build system that _irq_spurious makes is
much shorter, so it is much easier for a user to understand how it is
used.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-19 13:46:35 -07:00
Ioannis Glaropoulos
bf15988510 arch: arm: beetle: duplicate CMSIS MPU-related macros
Duplicate the CMSIS MPU-related macro definitions specifically
for Beetle SOC which is is not compliant with ARM CMSIS and
does not include the ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
1547abb57d arch: arm: use CMSIS defines for MPU_RASR register bit setting
This commit removes the macro definitions for MPU_RASR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
8d52c17166 arch: arm: use CMSIS defines for MPU_RBAR register bit setting
This commit removes the macro definitions for MPU_RBAR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
0a41e23ac0 arch: arm: use CMSIS macro defines for MPU_CTRL register bit setting
This commit removes the macro definitions for MPU_CTRL register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Jakub Rzeszutko
eb84eff27f arch: arm: nrf: modification of config parameter: SOC_SERIES_NRF52X
Configuration parameter SOC_SERIES_NRF52X is common for all NRF5X SoCs.
Due to that it cannot select: CPU_HAS_FPU because not all Nordic
microcontrollers supports that. Selection of this parameter was moved
to configuration of each SoC in Kconfig.soc file.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-19 20:02:51 +02:00
Jakub Rzeszutko
1fa9d84332 arch: arm: nrf: add hardware description for nrf Kconfig files
Created NRF5x peripheral list that can be used to describe each
NRF5x SoC. Basing on this description Kconfig file can display
and allow to configure only these drivers that are available
for particular SoC.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-19 20:02:51 +02:00
Andrzej Głąbek
687355c9af arch: arm: nrf: Use SystemInit() from MDK in SoC initialization
Replace code that handles erratas and performs other SoC-specific
initialization, that was actually copied from SystemInit() provided
in MDK for particular SoCs, with a call to SystemInit().

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-06-19 14:25:39 +02:00
Alex Tereschenko
3c1a78ea0d cmake: replace PROJECT_SOURCE_DIR with ZEPHYR_BASE
Both variables were used (with the same value) interchangeably
throughout CMake files and per the discussion in GH issue,
ZEPHYR_BASE is preferred.

Also add a comment with explanation of one vs. the other.

Tested by building hello_world for several boards ensuring no errors.

Fixes #7173.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-18 15:25:55 -04:00
Aurelien Jarno
7688f49065 drivers: usb_dc_stm32: change all endpoints to bidirectional
The various STM32 reference manuals sometimes define the USB endpoints
as IN or OUT only and sometimes as bidirectional, even in the same
manual. This is likely because the OTG implementation has one set of
registers for the IN endpoints and one other set for OUT endpoints.
However at the end a given endpoint address can both transmit and
receive data.

This causes some confusion how to declare the endpoints in the device
tree, and depending on the SoC, they are either the same number of IN
and OUT endpoints declared, or they are declared as bidirectional. At
the end it doesn't really matter given how the driver uses those values:

    #define NUM_IN_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
                       CONFIG_USB_NUM_IN_ENDPOINTS)

    #define NUM_OUT_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
                        CONFIG_USB_NUM_OUT_ENDPOINTS)

    #define NUM_BIDIR_EP NUM_OUT_EP

This patch therefore cleanup the driver, the DTS, and the DTS fixups to
only define the number of bidirectional endpoints.

In addition to the cleanup, that fixes a regression introduced by commit
52eacf16a2 ("driver: usb: add check for endpoint capabilities"), which
introduced a wrong check for SoC only defining the number of
bidirectional endpoints.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-18 15:24:15 -04:00
Alexander Wachter
c601f3be67 can: Add can support for STM32L432
This commit enables CAN on the STM32L432.
Tested on nucleo l432ck with external transceiver and loopback mode.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-06-18 15:23:29 -04:00
Alex Tereschenko
0824ec6409 dt: nrf52840: remove 0x from USBD address
The prepended 0x causes DTC warnings and shouldn't be there.

Tested by compiling hello_world for nrf52840_pca10056 before and after.

Fixes #8334.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-16 18:00:56 +02:00
Ioannis Glaropoulos
7a864bb79b arch: arm: define and implement ARM IRQ target state API
This commit contributes the definition and the implementation
of an API for ARM MCUs to configure and get the configuration
of the security state targeted by a given external IRQ line.
The API is only available in Secure ARM Firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 15:53:11 +02:00
Ioannis Glaropoulos
fe3cd4c8ff arch: arm: convenience wrappers for C variable Non-Secure permissions
Declare and implement convenience wrappers to evaluate Non-Secure
read and write permissions of C variables using the cmse address
range intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
879366120e arch: arm: implement cmse address range check (secure)
This commit contributes the implementation of the CMSE
address range permission checks based on the ARMv8-M
address range check intrinsics exlusicely for Secure state.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
d426adccaa arch: arm: refactor function to align with the adopted api
Refactor arm_cmse_mpu_region_get(.) function, so its signature,
documentation, and implementation align with the rest of functions
for obtaining MPU, SAU and IDAU region numbers via the TT instruction.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
f630559e81 arch: arm: Define and implement API for test target (Secure)
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Tests Target (TT, TTA)
instruction support (for Secure requests).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
0a2dcaaf8f arch: arm: introduce dependencies for CPU_CORTEX_M_HAS_SPLIM option
This commit introduces additional dependencies and selection
scheme for CPU_CORTEX_M_HAS_SPLIM, for Zephyr Non-Secure builds
on ARMv8-M MCUs with Security Extensions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
13dc376240 arch: arm: introduce ARMV8_M_SE option
This commit introduces the ARMV8_M_SE K-config option
to signify the use of an ARMv8-M MCU with support for
Security Extensions. It also introduces dependences of
ARM_(NON)SECURE_FIRMWARE on ARMV8_M_SE.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
dd640f143e arch: arm: introduce ARM_NONSECURE_FIRMWARE option
This commit introduces the K-config option
ARM_NONSECURE_FIRMWARE, to indicate a Zephyr firmware image
that is intended to execute in Non-Secure state.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
158ea44ed3 arch: arm: improve help text for ARM_SECURE_FIRMWARE
This commit improves the help text description for K-config
option: ARM_SECURE_FIRMWARE.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Yasushi SHOJI
2e0af08e55 build: remove unused CMakeLists.txt
lib/libc/minimal/source/CMakeLists.txt and
lib/libc/minimal/source/stdout/CMakeLists.txt was introduced in
12f8f7616 but it is not used by the build system.  CMakeLists.txt in
the parent dir lib/libc/minimal/CMakeLists.txt adds C files to the
target with the lines like:

    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/atoi.c
    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/strtol.c

To make other empty CMakeLists.txt explicit, this commit adds a
comment line to them.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2018-06-14 15:02:02 -04:00
Aurelien Jarno
bb55155d5b arch: arm: core: cortex_m: add a barrier before the dummy FP instruction
On Cortex-M7 CPU (at least on STM32F723), the dummy move FPU instruction
is executed before the FPU lazy state preservation is disabled. Add an
instruction synchronization barrier before it to avoid that.

At the same time, remove the data synchronization barrier after the
dummy move as it does not have any effect on RAM or registers.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-14 19:09:34 +02:00
Marc Reilly
6c60abb03b drivers: gpio: add dts support for nrf52 gpio
This adds basic support for declaring gpio nodes in dts for nrf52.
The dts.fixup provides mapping for the generated defines to the config
defines currently used by the nrf gpio driver.

Existing boards that use nrf52 are updated.

Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
2018-06-14 15:56:39 +02:00
Tomasz Gorochowik
e86c53b48f arch: arm: atmel_sam: Map the whole RAM in MPU
The extra region is wrapped in an "ifdef" as two MPU regions are used
only if the total memory size is not a power of two.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2018-06-13 16:12:05 -07:00
Tomasz Gorochowik
31aa9b9ad1 arch: arm: atmel_sam: Use a single RAM region when possible
There is no need for two RAM regions when the total amount of memory is
a power of two. With this change it will be possible to map the whole
memory and save one MPU region for such cases.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2018-06-13 16:12:05 -07:00
Gautier Seidel
77643677a1 esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b
Recent ESP-IDF provides OS-agnostic wifi binary, needed by #3723

Closes #8240

Signed-off-by: Gautier Seidel <gautier.seidel@tado.com>
2018-06-13 18:53:43 -04:00
Ulf Magnusson
7f5203d370 kconfig: Remove UART_QMSI_{0,1}_NAME Kconfig reference
This symbol was removed by commit 17c6456678 ("drivers/uart: Use dts
to set uart priorities for QMSI driver"). The setting should come from
DTS now.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-13 13:35:56 -04:00
Ulf Magnusson
f177fb88a0 arch: arc: Fix reference to removed NSIM Kconfig symbol
The NSIM symbol was removed in commit 9bc69a46fa ("boards: Update arc
em_starterkit support from 2.2 to 2.3").

Guess that UART_NSIM should be used here now, similar to what was done
in commit 45221a9706 ("serial: nsim: Fix impossible-to-enable
CONFIG_UART_NSIM").

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-13 13:35:56 -04:00
Vinayak Kariappa Chettimada
070c1ae041 soc: nRF52x: Add Kconfig options to enable DC/DC converter
Added a hidden Kconfig option in arch/arm/soc/nordic_nrf
which is selected by selecting DC/DC circuitry being present
in the board.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2018-06-13 18:56:54 +02:00
Savinay Dharmappa
b7c4c0302c dts: riscv32: riscv32-qemu: Add device tree support
add device tree support for riscv32-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-06-13 08:47:52 -04:00
Erwan Gouriou
2800729614 arch/stm32: remove irq definition files
Since they are not used anymore because can be replaced
by CMSIS definition or generated from device tree,
remove IRQ definition file soc_irq.h

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-06-13 11:43:56 +02:00
Ioannis Glaropoulos
8c53f2422c arch: arm: set VECTOR_ADDRESS to _vector_start
This commit sets VECTOR_ADDRESS in prep_c.c directly to the
value of _vector_start for XIP images for MCUs which have the
VTOR register.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-12 17:28:46 +02:00
Jakub Rzeszutko
3f99eefe5a drivers: uart: Rename nrf5 namings to nrfx
UART driver renamed to keep the same convention as SPI and TWI drivers.
All substrings: "UART_NRF5" in defines renamed to  "UART_NRFX_UART".

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-12 13:21:18 +02:00
Jakub Rzeszutko
e7252fbbfe drivers: uart: Refactor nrf uart shim
Replace all register defines and calls with Nordic nrfx HAL.
Simplification of uart shim - assumed only one uart instance.
Added parity bit to configuration options.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-12 13:21:18 +02:00
Johann Fischer
2055b84f79 boards: frdm_kl25z: add USB support
Add USB support to FRDM_KL25Z board.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-06-12 04:09:50 -04:00
Florian Vaussard
653d75cfba pwm: stm32: Add PWM fixup for STM32* and remove Kconfig options
Add fixup info for PWM nodes on STM32F0/F1/F3/F4/L4 and remove the
conflicting Kconfig symbols to fully switch STM32 PWM to device tree.

Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
2018-06-12 03:54:26 -04:00
Andy Ross
41070c3b35 arch/arm: Fix locking in __pendsv
The PendSV handler sits below the priority of other OS interrupts, but
it was inspecting kernel state before masking those interrupts out!

Move the locking to the top.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-06-11 20:15:48 -04:00
Ioannis Glaropoulos
61439b01c2 arch: arm: remove redundant flag
This commit removes the arm_mpu_enabled status flag in the ARM
MPU driver. This flag is not needed, because the value of the
MPU_CTRL register stays the same while the MPU is enabled, and
is cleared to 0 when the MPU is disabled. Therefore, we do not
need to prevent from having the enable or the disable operation
to be called multiple times.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
dbede45dbe arch: arm: improve inline comment in _arm_mpu_config/enable
In _arm_mpu_config provide a more detailed description of the
effect of MPU PRIVDEFENA flag when enabling the ARM MPU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
7b56b448f6 arch: arm: accelerate _get_num_regions() for Cortex-M0+, M3, and M4
ARM Cortex-M0+, M3, and M4 MCUs have a fixed number of 8 MPU
regions, if MPU support is implemented. Therefore, we can
implement _get_num_regions() to return a constant, if CPU
is one of the above Cortex variants. _get_num_regions() is
invoked often in the code, so this solution increases processing
efficiency. A sanity check is implemented in arm_mpu_init(), to
ASSERT if the number of regions provided by hardware does not
match the expected (default) value.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
ab81d2c7ab arch: arm: block ARM_MPU K-option in Cortex-M0
This commits adds a dependency for ARM_MPU on !CPU_CORTEX_M0,
so an accidental selection or ARM_MPU in ARM Cortex-M0 MCUs
will signal a K-config warning.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Rajavardhan Gundi
4ec773f276 DTS: intel_s1000: Clean up I2C and UART stuff from soc.h
Clean up some remnant stuff related to I2C and UART from soc.h
and put it in dts.fixup

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Rajavardhan Gundi
e5b0e9ac07 DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Wayne Ren
d5bc9d7bee arch: arc: adjust privileged stack size of arc to 384 bytes
Considering the case of call of printk, interrupt and
other cases, adjust the privileged stack size of arc to
384 bytes to avoid the the overflow of privileged stack.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-11 09:05:15 -05:00
Wayne Ren
97d0436486 arch: arc: use top of isr stack as exception stack and bug fixes
* re-use top of isr stack as exception stack
* bug fixes in irq offload's implementation
* improve kernel oops implementation

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-11 09:05:15 -05:00
Anas Nashif
1c4fe3edc0 arch/arc: Set the right priority for ADC/AON on quark_se
ARC has only 2 priorities, 0 or 1. So let's set the right priority for
ADC and AON.

Fixes #8302

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-06-11 08:52:24 -05:00
Wayne Ren
c63298ea65 arch: arc: improve the reset code
This commit improves the reset of arc:
* make the processor in the correct status
* clear interrupt related regs

this may improve or fix #6515

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
fb3d2d3785 arch: arc: remove unused codes
base.user_options is already set in k_thread_
user_mode_enter

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
5dd552e66b arch: arc: STACK_CHECK_FAIL of STACK_CHECK not hang the system
Whether it should hang the system it not decided finally.
But remove it here to let some tests pass.

Fixes #8032

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
5b6f860539 arch: arc: use a separate stack for exception handling
* use a separate stack for exception handling, this
will gurantee the exception handling always work, not
affected by some speical cases, e.g., stack check exception
or mem. protection exception at the exception entry.

* this commit can fix the second case of #8092

* note: the thread switch is still possible in exception
handling, e.g, caused by thread_abort. But the switched out
thread cannot be recovered, as the thread context is not
setup.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Andrew Boie
2dd91eca0e kernel: move thread monitor init to common code
The original implementation of CONFIG_THREAD_MONITOR would
try to leverage a thread's initial stack layout to provide
the entry function with arguments for any given thread.

This is problematic:

- Some arches do not have a initial stack layout suitable for
this
- Some arches never enabled this at all (riscv32, nios2)
- Some arches did not enable this properly
- Dropping to user mode would erase or provide incorrect
information.

Just spend a few extra bytes to store this stuff directly
in the k_thread struct and get rid of all the arch-specific
code for this.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-06-06 14:26:45 -04:00
Erwan Gouriou
7f7718a09a arch: stm32: remove .hex binary build by default
BUILD_OUTPUT_HEX was enabled by default for stm32 SoCs.
This should not be the default setting and besides it has no
effect because of 'default n' in misc/Kconfig that seems to
prevail.
Removing the 'default y' for  stm32 to avoid confusion.

Fixes #8193

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-06-06 09:37:05 -04:00
Andy Ross
718597fe32 arch/arm: Fix THREAD_MONITOR entry struct
On ARM, the __thread_entry struct pointer used when
CONFIG_THREAD_MONITOR is enabled was pointing to the initial exception
stack frame.  That's not right: even though this contains all the same
info, it's not layout-compatible with the API struct.  And once the
thread starts running, the ESF gets unwound and the memory recliamed
for the stack frame of the entry function!

Stuff the __thread_entry struct into its own memory at the bottom of
the stack like the other architectures do.  Fixes #7541

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-06-05 13:25:27 -04:00
Tomasz Bursztyka
c5cb8e943c arch/arc: Set the right priority for WDT on quark_se
ARC has only 2 priorities, 0 or 1. So let's set the right priority for
WDT.

It looks like some commit has changed that, somewhere. And wrong
priorities were lurking around.

Fixes #8096

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-06-05 09:08:46 -04:00
Maureen Helm
b423ee5f2a nxp_imx: Move i.MX RT PLL selects to Kconfig.soc
PLL configuration options for i.MX RT SoCs were added in commit
3fd25c64c7, but the selects were
incorrectly added to the SoC defconfig rather than Kconfig.soc. This
resulted in the PLL options not being configured and the part not
booting properly.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-04 22:57:38 -04:00
Wayne Ren
b09b6b6ee8 arch: arc: add comments for _load_stack_check_regs
add comments for _load_stack_check_regs to avoid
wrong usage

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-04 13:31:43 -04:00
Wayne Ren
b829bc78c1 arch: arc: refactor the arc stack check support
* the original stack check codes have no consideration
  for userspace case. This will wrong cause possible stack
  check exception.
* this commit refactors the arc stack check support to
  support the usperspace.

* this commit fixes #7885. All the failed tests in #7885
  are run again to verify this commit. The test results are ok

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-04 13:31:43 -04:00
Ryan QIAN
5c6a3991b5 mimxrt1050: check if D-cache is enabled before enabling it.
An issue has been confirmed in CMSIS core header file in
SCB_EnableDCache when stack is in cacheable memory.

Issue report: https://github.com/ARM-software/CMSIS_5/issues/331

To workaround this issue by checking if Dcache's been enabled before
trying to enable it.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
5757b4482e mimxrt1050: fix dcdc value change process
- to check status bit to make sure DCDC output is stable

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
3fd25c64c7 boards: mimxrt1050_evk: add condition to initialize different PLL
- add conditions to initialize different PLL

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
b2522d44cb mimxrt1050: remove app specific code from soc file
- Remove clock gating code to be compatible with A1 silicon
- Remove PLL deinitialization code out of soc file

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Tomasz Bursztyka
0d56036f04 arch/x86: Rename a legacy network Kconfig option
ETHERNET option was from first network stack (a fork of uIP). This
option is now called NET_L2_ETHERNET.

Fixes #7798

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-06-04 08:24:28 -04:00
Alexander Wachter
b97dd472fb drivers: can: Move bit timing and clock to device tree
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-06-01 12:59:42 -05:00
Piotr Zięcik
997a49ade9 arm: userspace: Do not overwrite r7 during syscall.
The r7 register is used as a frame pointer on ARM Thumb. As result, it
cannot be modified by the assembly code in functions using stack frame.

This commit replaces r7 by r8, which is a general purpose register.
Also it fixes #7704.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-06-01 13:07:47 -04:00
Sathish Kuttan
9f4702b3b4 arch: soc: intel_s1000: set M/N divider ownership
Add bit definitions and set M/N divider ownership in
i2s_initialize.
Changes to comply with coding guidelines
Changes to address review comments

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Sathish Kuttan
ed33f43e48 arch: xtensa: intel_s1000: Reference clock API
Added a function to obtain the reference clock frequency value based on
SoC's bootstraps.
Added M/N divider base address in SoC header file

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Ioannis Glaropoulos
e76ef30aca arch: arm: mpu: minor comment style fixes
This commit fixes some minor function documentation issues
and comments' style in the NXP_MPU driver.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
7f643677be arch: arm: add additional sanity checks before MPU config change
This commit inserts sanity checks every time we are performing
a (re)-configuration of one or multiple MPU regions, ensuring
that we do not attempt to configure an invalid region number.

Particulary for arm_mpu_config(), called during pre-kernel
initialization phase, we add a system ASSERT if we attempt
to initialize more regions that what is supported by hardware.
We do this to ensure the misconfiguration is detected early and
the system boot is aborted.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
25c211d252 arch: arm: implement internal function to disable MPU region
This commit adds an internal function to disable an MPU region.
The function includes an assert that the requested MPU region
number is a valid one. arm_mpu.c is refactor to use this
function in all cases where an MPU region needs to be disabled.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
0967f11f6d arch: arm: enhance internal function documentation
This commit enhaces the documentation of internal functions
in arm_mpu.c by explicitly stating that the caller needs to
ensure the validity of the supplied MPU region index. The
warning is required as these functions modify the ARM MPU_RNR
register, without checking themselves the validity of the
provided region number.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
7b77a25f14 arch: arm: coding and comment style fixes
This commit fixes some minor issues with coding style
and comment syntax in arm_mpu.c

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Joakim Andersson
45b75dd7ff arch: arm: Fix zero interrupt latency priority level
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.

Update comments to reflect the priority levels reserved by the kernel.

Fixes: #8073

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2018-05-31 14:58:43 -04:00
Ioannis Glaropoulos
6399cb6b27 arch: arm: force MpuFaultHandler to inspect multiple error conditions
Upon MemManage Exception, multiple status bits of MMFSR may be
set. This commit modifies the MPU Fault Handler, so that it can
inspect and display information from all error conditions,
instead of just the first error condition that is true.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Ioannis Glaropoulos
56c9760834 arch: arm: use stored value for MMFAR
Make MPU stack guard checks use the previously stored value
of the MemManage Fault Address Register, to ensure that the
address-under-check is valid.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Andy Ross
1fe6c36730 esp32: Add some "logging" voodoo to SMP initialization
At least one of my WROOM boards has trouble getting the APPCPU
started, that was magically getting better when I started adding
printk's to debug.  It turns out that UART output (and NOT simply idle
cycles of delay) was the magic dust to fix things.  As this SMP
implementation is reverse engineered voodoo to begin with, this hack
should be acceptable in the medium term.

See in-file comments on smp_log() for details.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-31 14:02:03 -04:00
Gil Pitney
ec7d483b5b arch: arm: soc: cc2650: Remove dead code.
Remove the dead code that was guarded by previously removed
Kconfig symbols for the sensortag board.

With b028a51542,
this fixes #7873

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-30 22:20:37 -04:00
Wayne Ren
3c8ed211c2 arch: arc: fix the wrong setting of STACK_CHECK for user thread
For user thread, the stack check parameters will cover both
user stack part and privilege stack part. Because in arc, they
are in the same array.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-30 20:23:35 -04:00
Johann Fischer
5fae373107 dts: nxp: fix typo in usbd bindings
Fix typo in usbd bindings.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-30 11:23:39 -05:00
Erwan Gouriou
f315afd0a7 arch: stm32: Fix inclusion of SPI headers
In some STM32 series, SPI LL headers where included under
CONFIG_CLOCK_CONTROL_STM32_CUBE flag definition.
Fix this and use CONFIG_SPI_STM32 instead.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-29 07:44:00 -07:00
Adithya Baglody
c2d632d69d arch: arm/arc: Remove usage of zephyr_library_ifdef.
Phasing out the usage of this cmake macro from the arch folder.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Adithya Baglody
a9ea155425 arch: arm: add_subdirectory shouldn't depend on a hidden kconfig.
Previously the directory core/cortex/mpu/ was getting included
on a hidden kconfig. Now this has been replaced with the Kconfig
CONFIG_ARM_CORE_MPU.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Adithya Baglody
699aacad50 arch: arm: add_subdirectory shouldn't depend on a hidden kconfig.
Previously the directory core/mpu/ was getting included on a hidden
kconfig. Now this has been replaced with the Kconfig
CONFIG_ARC_CORE_MPU.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Carles Cufi
93a464321d arch: arm: nordic: nrf52: Enable instruction cache
Enable the instruction cache by default in order to achieve a speedup of
up to 20% in code execution.
Cache can be disabled by setting the new NRF_ENABLE_ICACHE Kconfig
option.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-28 17:59:38 +02:00
Aurelien Jarno
cbac8fcadb arch: arm: select CPU_HAS_FPU on STM32L4 family
All the STM32L4 SoCs have a Cortex-M4F CPU, and thus have a FPU. Update
stm32l4/Kconfig.series to select CPU_HAS_FPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-28 09:32:23 -05:00
Kumar Gala
71ce9b524a arch: arc: snps_emsk: Removed dead code
soc.h had defines for CONFIG_ARCV2_TIMER1_INT_{LVL,PRI}.  These defines
are both not used and no Kconfig symbols so lets remove them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-28 10:46:24 +02:00
Ulf Magnusson
cc4473831f soc: soc_family: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
d946ed7328 soc: defconfig.series: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
3ac3216d89 soc: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Leandro Pereira
edd18c8f5a arch: x86: Better document that CR0.WP will also be set when CR0.PG is
Setting bit CR0.WP (bit 16) will inhibit supervisor threads from
writing to RO pages.  It's a necessary flag to be set, and the constant
name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was
being set.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-26 19:09:33 -04:00
Aurelien Jarno
a9fe133d07 arch: arm: fix a typos in Kconfig file
Architectue => Architecture

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-26 19:07:55 -04:00
Ioannis Glaropoulos
0825d0cd19 arch: arm: fix undefined variable bug
This commit fixes a compilation bug for an undefined variable
(mmfar), which is only conditionally defined. Instead of mmfar
we use the ARM register value directly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-26 15:50:56 -04:00
Anthony Kreft
94a22daf36 arch: arm: STM32L053X8 support
Add support for the STM32L053X8 on the NUCLEO-L053R8 board.

Signed-off-by: Anthony Kreft <anthony.kreft@gmail.com>
2018-05-25 13:06:18 -05:00
Gil Pitney
9d2f370ddb boards: cc3220sf_launchxl: Make cc3220sf XIP by default
Previously, there was no easy command-line solution for loading
a Zephyr program to (internal) flash.
So, the default development method was to load via gdb/openocd
to SRAM and debug from there, thus making the cc3220sf platform
non-XIP (CONFIG_XIP=n) by default.

With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu),
the image can now be flashed and debugged via gdb/openocd,
so the default will be changed to XIP (CONFIG_XIP=y).

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-25 11:59:00 -05:00
Jun Li
8cc002e657 soc: stm32f1: add port uart4
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.

Signed-off-by: Jun Li <jun.r.li@intel.com>
2018-05-25 11:58:20 -05:00
Ilya Tagunov
1e6d827a53 drivers: serial: stm32: add LPUART support for L0/L4 series
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Ilya Tagunov
fd26514a4d drivers: serial: stm32: rework macros and fixups
STM32Lx LPUART peripherals do not fit well into existing U(S)ART
port numbering scheme, so there will be two separate namespaces
in Kconfig: one for U(S)ARTs and one for LPUARTs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Andy Ross
3a0cb2d35d kernel: Remove legacy preemption checking
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.

As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant.  And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-25 09:40:55 -07:00
Ioannis Glaropoulos
49f0dabfcc arch: arm: refactor default _FaultDump to provide fatal error code
Refactor the _FaultDump of the default debug-level (2) to
provide the error code that indicates the fatal error reason.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d54dc42af9 arch: arm: refactor FAULT_DUMP to retrieve the fatal error reason
Refactor FAULT_DUMP macro to obtain and store the fatal error
reason. Make non-default version of FAULT_DUMP (i.e. with
CONFIG_FAULT_DUMP level 1) to retrieve the default reason
for fatal errors (_NANO_ERR_HW_EXCEPTION).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d2c8a20560 arch: arm: document non-returning fatal handlers
Document that execution does not return from
_NanoFatalErrorHandler and _SysFatalErrorHandler.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Wayne Ren
876a9af9d5 arch: arc: fix the bug in register clear for USER_SPACE
* blink, fp should not be always cleared
* clean up code format
* use a better way to save and restore ER_SEC_STAT

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-25 15:56:15 +02:00
Wayne Ren
77eb883ab0 arch: arc: fix the bug in exception return for secure mode
* current codes use a faked interrupt return to do a thread switch
  in exception return.
* so the different between exception return and interrupt return
  should be carefully considered.
* when secure is enabled, the sec_stat should also be pushed in
  exception entry.
* when secure is enabled, SEC_STAT.IRM must be configured corrrectly
  for interrupt return.
* For the case of faked interrupt return in exception return, the
  correct value of SEC_STAT.IRM comes from ER_SEC_STAT.ERM.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-25 15:56:15 +02:00
Andrew Boie
6f6acb4667 arm_mpu: reduce boot MPU regions for various soc
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Fixes #6896

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 19:19:07 -04:00
Andrew Boie
d9a227c19c arm: st_stm32: reduce boot MPU regions
The PPB and Peripheral regions have been removed,
the Shareable options are only important with unlocked
dual cores. Just use the background mapping.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Related to #6896 and #7877

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 15:31:00 -07:00
Leandro Pereira
ecadd465a2 arch: x86: Allow disabling speculative store bypass
In order to mitigate against Spectre V4, add an option that will, at
boot time, verify if the CPU supports the SPEC_CTRL MSR; if so, it'll
attempt to disable the feature.

More information can be found in chapter 4 (Speculative Store Bypass
Mitigation) of the "Speculative Execution Side Channel Mitigations"
document, version 2, published by Intel: https://goo.gl/nocTcj

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-24 13:07:12 -04:00
Leandro Pereira
fb0fba91a5 arch: x86: Rename CPU_NO_SPECTRE to CPU_NO_SPECTRE_V2
There's a new known variant, so make it clear what this one is for.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-24 13:07:12 -04:00
Ioannis Glaropoulos
46a3e8bdf0 arch: arm: fix fault status register bitfield masks
This commit fixes the bitfield masks for the Cortex-M
fault status registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-24 11:31:54 -05:00
Tomasz Bursztyka
2bfcb8496d arch/arc: UART QMSI's baudrate is not present in Kconfig anymore
It's generated through dts.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-24 11:58:17 -04:00
Aurelien Jarno
509e6964cc arch: stm32l432: add support for USB controller
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Aurelien Jarno
dc01b99068 arch: stm32l4: only enable USB OTG on SoCs supporting it
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:

- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller

Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Kumar Gala
8321b6b64f arch: arm: nxp: Fixup HAS_MCUX_RTC
When the RTC support get added we had a select on HAS_RTC, however this
Kconfig symbol didn't exist.  Clean this up to match the pattern of
HAS_MCUX_RTC.  The driver now depends on that and the SoC selects it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-24 08:21:24 -05:00
Ulf Magnusson
5b20350a72 gdb_server: Remove leftover testing and x86 parts
gdb_server was removed in commit 0f669132a0 ("kernel: remove
gdb_server"), but still has a testcase that sets CONFIG_GDB_SERVER=y,
and some code in arch/x86/debug.

Remove the leftover parts. This also gets gets rid of undefined
references to the CONFIG_GDB_SERVER symbol.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-24 08:10:21 -04:00
Erwan Gouriou
9559277094 arch: stm32: Remove unsupported MPU options
Some code was developped around MPU support in ealy stage
of feature introduction. This code was gated under MPU_ENABLE
flag which does not exist and hence code has never been
enabled nor tested.
Since there has been futher MPU development since then, it seems
safer to simply remove that code and associated Kconfig symbols
to avoid that someone starts using it while it was not part of
MPU development track.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-24 08:04:00 -04:00
Kumar Gala
33628f1c47 arch: arc: userspace: Fix typo in comment
CONFIG_INIT_STACK should be CONFIG_INIT_STACKS

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
Kumar Gala
6ef2f76b2f arch: arm: thread.c: Fix typo in comment
Changed CONFIG_BUIILTIN_STACK_GUARD to CONFIG_BUILTIN_STACK_GUARD.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
Kumar Gala
7faac6a761 arch: arm: atmel_sam: Add quotes to strings in Kconfig
While not technically required, its cleaner to ensure that strings
defaults are quoted.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
David B. Kinder
44383a394b doc: fix misspellings in Kconfig files
Found some misspellings missed during normal reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-23 16:57:20 -04:00
Leandro Pereira
d4221f9a71 arch: x86: Rename MSR-handling functions to conform to convention
Rename _MsrRead() and _MsrWrite() to _x86_msr_read() and
_x86_msr_write() respectively.

Given that these functions are essentially implemented in assembly.
make them static inline.  They can be inlined by the compiler quite
well, most of the time incurring in space savings due to better
handling of the cobbled registers.

Also simplifies the inline assembly, using constraints instead of
moving registers ourselves.  Should shave off a few bytes from code
using these functions.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-23 14:38:22 -04:00
Carles Cufi
5b37cd7346 arch: arm: swap: Remove old context switch code
Remove unused context switch code from the helper assembly file that
manages the SuperVisor Call invocations (SVCs). This is no longer in use
in the code, since all calls to __swap() now go through PendSV directly.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-23 09:34:12 -07:00
Andrew Boie
99f36de0a1 arm: userspace: fix initial user sp location
The initial user stack pointer gets rounded to STACK_ALIGN_SIZE,
which can be much finer granularity than MPU regions. With
certain stack size values passed to k_thread_create(), the stack
pointer can be set past the defined region for the user thread's
stack, causing an immediate MPU fault.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Andrew Boie
9731a0cce9 arm: syscalls: fix some register issues
Upon return from a syscall handlers, the r1, r2, and r3 registers
could contain random kernel data that should not be leaked to user
mode. Zero these out before returning from _arm_do_syscall().
Fixes #7753.

The invocation macros need a clobber if r1, r2, or r3 are not used
to carry syscall arguments. This is a partial fix for #7754 but
there appear to be other issues.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Sebastian Bøe
cde6bef778 kconfig: Drop support for CONFIG_TOOLCHAIN_VARIANT
The Kconfig option TOOLCHAIN_VARIANT (not to be confused with
ZEPHYR_TOOLCHAIN_VARIANT) is a legacy configuration option that has
very few use-cases and can easily be dropped.

It's functionality is easily covered by CONFIG_X86_IAMCU and
ZEPHYR_TOOLCHAIN_VARIANT.

This commit removes all references of it from Zephyr.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-05-22 11:15:36 -04:00
Savinay Dharmappa
2ebb6a1fee dts: intel_s1000: use dts to set i2c0 priority.
patch removes Kconfig used i2c0 priority, instead use the
macro generated from dts.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 09:30:14 -04:00
Savinay Dharmappa
6701d44967 dts: xtensa: Fix build error due to dts changes for ns16550 driver.
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 08:51:59 -04:00
Kumar Gala
edf7c4fd08 arch: arm: kw41z: Set DTS fixup for CONFIG_RTC_0_NAME
Recent change to RTC core now gets CONFIG_RTC_0_NAME from device tree.
So we need a fixup for KW41Z for that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-21 14:06:57 -05:00
Maureen Helm
b5db62ca94 frdm_kl25z: Remove incorrect references to spi
The kl25z does not have the same spi hardware as the k64f and therefore
cannot use the same spi driver. Remove all references to spi for the
kl25z soc and frdm_kl25z board until we have a valid spi driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-21 13:26:10 -05:00
Alexander Wachter
e73637af24 boards: stm: Add CAN support for stm32f072b micro controller
This commit adds the can device to the stm32f072b device tree and pinmux

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-05-19 20:19:30 +02:00
Tomasz Bursztyka
60d509f3d7 arch: Use dts to set i2c priorities for quark_se/quark_d2000
Fix the qmsi i2c driver and the relevant SoCs accordingly.
Also applying relevant changes on quark_se_c1000_ss as it can use i2c
qmsi driver as well along with qmsi ss i2c driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
ed26b95746 drivers/gpio: Removing dts generated options in QMSI Kconfig
Now that all arch using QMSI gpio driver are generating the right
settings through DTS, these options can be removed from Kconfig.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
bd9706cd9b arch/arc: Use dts to set gpio priorities for quark_se_c1000_ss
Fix the qmsi ss gpio driver accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
61ef30d10e drivers/uart: Use dts to set uart options for ns16550 driver
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
17c6456678 drivers/uart: Use dts to set uart priorities for QMSI driver
Fix the qmsi uart driver and relevant SoCs accordingly.
Also: using config for irq everwhere relevantly and not an hardcoded
value in the driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
250c4a87ed arch: Use dts to set rtc priorities for Intel quark, x86 and arc
Get the name generated through dts as well.
Fix the rtc driver and relevant SoCs accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
53f91976b1 arch/x86: Use dts to set gpio options for quark_se and quark_d2000
Get the name and irq flags generated through dts as well.
Fix Kconfig for the gpio driver accordingly.

Irq priority is not set by dts for D2000 as it's irq controller does
not support it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Ramakrishna Pallala
eb0aaca64d lib: posix: Add Posix Style File System API support
Add IEEE 1003.1 Posix Style file system API support.
These API's will internally use corresponding Zephyr
File System API's.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-18 13:32:36 +03:00
Savinay Dharmappa
2948924655 dts: nios2-qemu: add device tree support
Add device tree support for nios2-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-17 14:09:15 -07:00
Savinay Dharmappa
8f908f38e0 dts: nios2f: Add device tree support
Add device tree support for nios2f soc

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-17 14:09:15 -07:00
Ulf Magnusson
4dc9e5b2de kconfig: Get rid of 'option env' bounce symbols
This commit gets rid of the 'option env="ENV_VAR"' bounce symbols.
"$FOO" now expands directly to the value of the environment variable
FOO, instead of to the value of the Kconfig symbol FOO.

This change is likely to soon appear in the C tools as well. Those
'option env' symbols always seemed kinda pointless, and have broken
dependency handling due to forcing symbol evaluation during parsing,
before all the symbols have even been seen.

Compatibility with the C tools could be retained by naming all
'option env' symbols the same as the environment variable they
reference.

This commit also updated the Zephyr documentation to explain the new
behavior. It's relevant for $ZEPHYR_BASE and out-of-tree Kconfig
extensions.

Commit message from Kconfiglib (cbf32e29a130d)
==============================================

Make "$FOO" directly reference the environment variable $FOO in e.g.
'source' statements, instead of the symbol FOO. Use os.path.expandvars()
to expand strings (which preserves "$FOO" as-is if no environment
variable FOO exists).

This gets rid of the 'option env' "bounce" symbols, which are mostly
just spam and are buggy in the C tools (dependencies aren't always
respected, due to parsing and evaluation getting mixed up). The same
change will probably appear soon in the C tools as well.

Keep accepting 'option env' to preserve some backwards compatibility,
but ignore it when expanding strings. For compatibility with the C
tools, bounce symbols will need to be named the same as the environment
variables they reference (which is the case for the Linux kernel).

This is a compatibility break, so the major version will be bumped to 6
at the next release.

The main motivation for adding this now is to allow recording properties
on each MenuNode in a clean way. 'option env' symbols interact badly
with delayed dependency propagation.

Side note: I have a feeling that recording environment variable values
might be redundant to trigger rebuilds if sync_deps() is run at each
compile. It should detect all changes to symbol values due to
environment variables changing value.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-17 23:55:07 +03:00
Stanislav Poboril
5477ee4531 mcux: Add MCUX IPM driver for lpc and kinetis socs
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-17 15:07:48 -05:00
Kumar Gala
7514a92cbe arch: arm: nxp_lpc: Added support for init of slave core
Added ability to load and bootup the slave (Cortex-M0+) core on the
LPC54xxx SoC.  Currently we expect a binary image to be specified via
Kconfig for the code that will run on the slave core.  We also specify
via Kconfig the boot/load address for the slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Kumar Gala
b7312d1bbc arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc
Add soc configuration support and dts files for nxp_lpc54xxx_m0.

Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Maureen Helm
02253c231d nxp_kinetis: Fix rtc base address in kw41z dts.fixup
Since commit 081c9c3bec,
extract_dts_includes no longer appends _0 to peripheral base addresses.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:03:50 -05:00
Maureen Helm
e9ca0a7dae nxp_kinetis: Enable mcux watchdog driver on k64, kw2xd socs
Enables the mcux kinetis watchdog driver on k64 and kw2xd socs. Adds
relevant soc-level dts fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:00:55 -05:00
Andy Gross
7b92d3fb1c rtc: nxp: Add RTC driver for NXP Kinetis
This patch adds the configuration, driver, and HAL changes required
to implement a MCUX based RTC driver for the NXP Kinetis KW41Z.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Andy Gross
1fe586f678 dts: nxp: kw41z: Fixup NXP Kinetis RTCs on KW41Z
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks.  DTS fixups were added as well to match up the driver
usage to the DTS output.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Florian Vaussard
ae71554be3 dts: stm32l4: add node and fixup for i2c4
Add the device tree node for I2C4 and the corresponding fixup.

Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
2018-05-17 13:08:36 -05:00
Ioannis Glaropoulos
b8ec6da38f arch: arm: convenience wrappers for C variable permissions checks
Declare and implement convenience wrappers to evaluate read and
write permissions of C variables using the cmse address range
intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
8e0c830dce arch: arm: implement cmse address range check
This commit contributes the implementation of the
CMSE address range permission checks based on the
ARMv8-M address range check intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
600d731c95 arch: arm: select CPU_CORTEX_M_HAS_CMSE in ARMv8-m
Select CPU_CORTEX_M_HAS_CMSE in ARMV8_M arhitectures.
Option ARMV8_M_BASELINE is introduced for this purpose,
so that CMSE API is enabled for both Cortex-M23 and
Cortex-M33 MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
c842f32ddd arch: arm: Define & implement API for test target (Non-Secure)
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Test Target (TT) instruction
support.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Johann Fischer
d6f14291ee arch: nxp_kinetis: enable USB device driver
Enable USB device driver for K64F and KW2xD512 SoC

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Johann Fischer
5dc6f99cfd drivers: usb: add usb device driver for Kinetis USBFSOTG Controller
Add usb device driver for Kinetis USBFSOTG Controller.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Johann Fischer
d8cd119562 dts: arm: nxp: use DT to configure USBD on Kinetis SoC
Add DT and fixup files to configure USB device driver on
Kinetis SoC K64F and KW24D512.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Andrew Boie
97bf001f11 userspace: get dynamic objs from thread rsrc pools
Dynamic kernel objects no longer is hard-coded to use the kernel
heap. Instead, objects will now be drawn from the calling thread's
resource pool.

Since we now have a reference counting mechanism, if an object
loses all its references and it was dynamically allocated, it will
be automatically freed.

A parallel dlist is added for efficient iteration over the set of
all dynamic objects, allowing deletion during iteration.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-16 17:32:59 -07:00
Andrew Boie
0daf69bb57 xtensa: fix CONFIG_INIT_STACKS for IRQ stack
The interrupt stack area wasn't being set to a repeating
0xAA pattern at boot as it should be. This is now done in
kernel_arch_init(), which runs before interrupts are
enabled for the first time.

Fixes #7327

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-16 12:06:31 -07:00
Andrzej Puzdrowski
11c68a10f4 boards/arm/nrf52xx_boards: makes GPIO_AS_PINRESET common
Kconfig keyword GPIO_AS_PINRESET is common for whole nrf52 series.
This patch move it to the series Kconfig.soc file.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-05-16 11:10:52 -05:00
Andrzej Puzdrowski
a5c12b6c05 arch/arm/soc/nordic_nrf/nrf52: NFCT pins configuration
It is possible to use NFCT pins as regular GPIOs.
This patch introduce option for enabling this feature.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-05-16 11:10:52 -05:00
Anas Nashif
48cc46206f boards: frdm_kw41z: enable xoroshiro on board level only
Enabling the driver on board level is sufficient. We need to find a
better way for selecting random drivers on SoC level, this is currently
not possible due to how Kconfig works.

Fixes #7097

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-16 10:36:59 -05:00
Savinay Dharmappa
48e2dba28f dts: xtensa: fix build error.
patch fix the build error due to wrong assignment of macro in
the dts.fixup file

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-16 10:25:19 -05:00
Stanislav Poboril
6871057e31 ext: Modified lpc54114 startup code from mcux for use with Zephyr.
The instructions performed by standard Zephyr startup files are removed
from the file startup_LPC54114_cm4.S. Introduced the section
_PlatformInit which will be called when platform specific initialization
is needed.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-15 15:49:15 -05:00
Stanislav Poboril
fd4759b5d7 arch: nxp: lpc54xxx: Rename SoC bits from LPC54114 to LPC54114_M4
Rename various SoC related defines and files from just being LPC54114
to LPC54114_M4.  This is in prep for supporting a build for the second
core on the LPC54114 (the Cortex-M0+).

* Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4
* Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4
* Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi
* Moved some pinmux related defines into SoC code.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 15:49:15 -05:00
Stanislav Poboril
0b7e22bdb6 arch: arm: Add platform init hook at __start
Add the ability to call platform specific code as the first thing we do.
This is needed because on some platforms we might have to figure out how
to deal with starting up secondary cores and need to do that as the
first thing we do.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-15 15:49:15 -05:00
Adithya Baglody
5ab3960c75 arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files.
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the arch files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.

In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-15 17:48:18 +03:00
Ioannis Glaropoulos
70b45c63e5 arch: arm: distinguish integrity signatures with/without FP
Distinguish between the integrity signatures depending on whether the
ARM MCU implements the Floating-Point Extension or not.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
361f4ac94b arch: arm: improve fault dump for secure firmware
This commit partially reworks the fault dump implementation
of faults in non-secure state that target Secure state. In
particular, the return address to secure state is logged along
with the non-secure address which caused the non-secure fault
(that targets the Secure state).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
0a25ad1595 arch: arm: fix bug in AIRCR config on init
Fix bug when setting SCB_AIRCR during initialization; add
Vector Key to permit write to AIRCR fields.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
9bc1dc7296 arch: arm: Secure fault handling for Cortex-M23
This commit contributes the Secure fault handling for ARMv8-m
implementations, that do not support the Main Extension, such
as the (Baseline) Cortex-M23 processor.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Wayne Ren
c13b12eb49 arch: arc: explictly list all def config
it seems regular expresssion is not supported in "source xxx" after
latest changes in build system.

So explictly list all def config

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
5eb5bb7df8 arch: arc: add the missing SPI_DW_SPI_CLOCK in dts.fixup
* the SPI share the same clk source with uart

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
47d3a90dca arch: arc: reuse GCC_M_CPU in cmake file and remove unused comments
* reuse GCC_M_CPU in cmake file
* remove unused comments in linker.ld

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
532e4d22ee dts: optimize and bug fixes the dts of em_starterkit
* add gpio, i2c, spi definitions
* optimize and bug fix the dts.fixup
* optimize and bug fix the em_starterkit related definitions
  in dts folder

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
6307b8b97d arch: arc: refactor the soc part of em_starterkit
The original em7d, em9d and em11d are different configurations of
em_starterkit. They have the same peripherals, e.g. uart, spi, gpio
, ddr. The differences of them are in arc core configurations, interrupt
number assignment.

So em7d, em9d and em11d can be viewed in the same SoC family or SoC
series.

Referring other arch's implementation, this commit merges em7d, em9d
and em11d into the same SoC, named snps_emsk. This will eliminate
unnecessary duplication and make it easier for future maintainment.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Savinay Dharmappa
e524f0b846 dts: x86: derive RAM and ROM size from dts instead of Kconfig
patch removes Kconfig defines for RAM and ROM size in x86. Instead
these values are derived from dts.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-14 17:19:23 -04:00
Karol Lasończyk
83e4947cf1 dts: nrf: Expand nRF DTS to support watchdog
Commit introduces support for watchdog configuration for Nordic
Semiconductor nRF SoCs in device tree.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
2018-05-14 10:28:23 -05:00
Yannis Damigos
87d624419d drivers/stm32f0x_ll_clock: Enable SYSCFG in clock_control
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and enable PIN pair PA11/12, used in USB device,
mapped instead of PA9/10.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:45:40 -05:00
Yannis Damigos
f6a9697923 drivers/stm32l0x_ll_clock: Enable SYSCFG in clock_control
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and internal voltage reference for 48 MHz HSI
used in USB device.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:33:29 -05:00
Yannis Damigos
c0b472132c dts/arm/st: Add USB support for stm32l072/73
Add USB support for stm32l072 and stm32l073 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:33:29 -05:00
Yannis Damigos
329c00dc6b arch/soc/st_stm32: Move STM32Cube HAL core funtions
STM32Cube HAL core initialization functions HAL_GetTick()
and HAL_Delay() are implemented in all STM32 series. This
patch moves these functions in file stm32cube_hal.c under
"common" folder to reduce code duplication.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-13 10:52:12 -05:00
Andrew Boie
42a2c96422 newlib: fix heap user mode access for MPU devices
MPU devices that enforce power-of-two alignment now
specify the size of the buffer used for the newlib heap.
This buffer will be properly aligned and a pointer
exposed in a kernel header, such that it can be added
to a user thread's memory domain configuration if
necessary.

MPU devices that don't have these restrictions allocate
the heap as normal.

In all cases, if an MPU/MMU region needs to be programmed,
the z_newlib_get_heap_bounds() API will return the necessary
information.

Given how precious MPU regions are, no automatic programming
of the MPU is done; applications will need to do this as
needed in their memory domain configurations.

On x86, the x86 MMU-specific code has been moved to arch/x86
using the new z_newlib_get_heap_bounds() API.

Fixes: #6814

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-10 15:09:02 -07:00
Maureen Helm
0d1beb2f9e boards: dts: Add mcr20a bindings and fix networking samples
Adds dts bindings for the mcr20a wireless transceiver. The frdm_k64f
board supports the mcr20a via an Arduino shield, therefore the dts node
is added to the board dts. The kw2xd is a SiP and thus the mcr20a dts
node is added to the soc dts.

The networking samples using prj_frdm_k64f_mcr20a.conf have been broken
since the refactoring of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
a88e31d2ca nxp_kinetis: Remove unused dspi irq defines from soc.h
Now that we get dspi irq numbers from dts, we can remove the defines
from soc.h.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
c7dd4f55f0 nxp_kinetis: Enable mcux dspi driver on kw40/41z socs
The kw40z and kw41z socs have the same dspi peripheral as the k64 and
kw2xd, so we can reuse the existing mcux dspi shim driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
cae9074492 spi: Refactor mcux dspi driver to use dts
Get the driver name, base address, irq number, and irq priority from
dts.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Kumar Gala
071212bec9 arch: arm: atmel_sam: Fixup build issue on sam_e70
With recent dts script change we dropped _0 from define names if there
is only a single one.  So for the MPU we need to use
CONFIG_SRAM_BASE_ADDRESS instead of CONFIG_SRAM_BASE_ADDRESS_0.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-10 12:48:14 -05:00
Kumar Gala
b493f484df arch: arm: soc: Cleanup Kconfig inclusion per SoC
When we included SoC specific Kconfig files we do something like:

gsource "arch/arm/soc/arm/*/Kconfig.soc"

However, we should do that inside an if block for that SoC family so as
to limit SoC family specific options to only being visible when that SoC
family is selected.  So we simply move the gsource and related items
inside the if SOC_FAMILY_<SOC> block.

Fixes: #7452

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-10 11:16:52 -05:00
Adithya Baglody
c136a107aa soc: sam_e70: Mpu regions should include SRAM regions.
In order to disable the execution of code from the RAM region
we need to declare it in arm_mpu_regions.c file.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-10 08:40:52 -07:00
Erwan Gouriou
e81d9b98fe arch: nxp dts bindings: Set IP clock name to matching clock controller
In dts.fixup files for used for NXP SoCs, IP clock name was
bound to SIM clock label. This is correct but would require
manual change if IP clock controller was changed in device tree.
Use reference to IP generated define "_CLOCK_CONTROLLER" to get
this value.

Besides, having all IP related values starting with the same prefix
will be easier for possible macro preprocessing (if required one day).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Erwan Gouriou
93d3a42776 scripts: extract_includes_dts: Remove usage of cell_string yaml attribute
'cell_string' yaml attribute has been introduced in order to
help enforcement of specific string during defines generation.
This adds complexity in understanding script behavior as a black
box and create additional dependency which is not strictly required.

For node specific generation functions (pinctrl and interrupts),
this could be replaced directly by an hardcoded version
(as everyone used the same 'cell_string' anyway).
For extract_cells functions, string could be replaced by extracted
property name. As a consequence, we're now able to generate defines
for properties refering to these controllers via phandle.
For instance, in following node
 	spbtle-rf@0 {
 		compatible = "st,spbtle-rf";
 		reg = <0>;
		reset-gpios = <&gpioa 8 0>;
 	};
We'll be able to generate:
 #define ST_STM32_SPI_...LE_RF_0_RESET_GPIOS_CONTROLLER	"GPIOA"
 #define ST_STM32_SPI_...PBTLE_RF_0_RESET_GPIOS_FLAGS_0		0
 #define ST_STM32_SPI_..._SPBTLE_RF_0_RESET_GPIOS_PIN_0		8

Only impact for this whole change is for NXP clocks which were the
only ones using 'cell_string' attribute with a value different than
the default one.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Erwan Gouriou
081c9c3bec scripts: extract_dts_includes: Generate'_0' defines only when needed
Indexed defines were systematically generated even when there
was only one element to generate.
So we ended up generated a lot of _0 defines.
Then we needed to generate aliases to these _0 indexed defines,
in order to get useful defines.
For instance:
 #define GPIO_LEDS_0_GPIO_FLAGS_0	4
 #define GPIO_LEDS_0_GPIO_PIN_0		5
 #define GPIO_LEDS_0_GPIO_FLAGS		GPIO_LEDS_0_GPIO_FLAGS_0
 #define GPIO_LEDS_0_GPIO_PIN		GPIO_LEDS_0_GPIO_PIN_0

This commit allows to generate _0 indexed define only if a
property has more than one elements to define.
Aliases generation to _0 indexed defines are also removed.

Note: IRQ are left untouched since this is frequent to handle
multiple IRQs in a driver

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Yannis Damigos
3bbe87e171 dts/arm/st: Add usbotg_fs node to stm32l4 DT
Add otgfs (USB) node to stm32l4.dtsi.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Pushpal Sidhu
e2b27d820d drivers: usb_dc_stm32: enable VDDUSB if needed
This is required on boards that isolate VDDUSB from the system.

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-05-10 07:47:13 -05:00
Pushpal Sidhu
816e3d8767 arch: stm32l4: add HAL_Delay for hal library hooks
Hook required for hal library to delay (in ms)

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
47fe4ee78b dts/arm/st: Add USB support for stm32f070/72
Add USB support for stm32f072 and stm32f070 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
80d69ea47f boards: stm32f3_disco: Add USB support
Add USB support to STM32F3DISCOVERY board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
38d2567e08 boards: olimexino_stm32: Add USB support
Add USB support to OLIMEXINO-STM32 board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
921bfeb05a drivers: usb_dc_stm32: Add support for all STM32 families
Add support for all STM32 families

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-05-10 07:47:13 -05:00
Ioannis Glaropoulos
47564a0971 arch: arm: feature consistency checks for Cortex M regs
This commit implements consistency checks for the core registers
in ARMv6-M, ARMv7-M, and ARMv8-M architectures, ensuring that
the user cannot accidentally select registers that are not
implemented by the selected Cortex-M processor.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 18:43:50 -05:00
Ioannis Glaropoulos
197e277300 arch: arm: improve description of ARMV7_M_ARMV8_M_MAINLINE option
The commit improves the help text of the ARMV7_M_ARMV8_M_MAINLINE
K-config option.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 18:43:50 -05:00
Ioannis Glaropoulos
dd26f285e5 arch: arm: add synchronization point after Stack Pointer switch
This commit adds a Context Synchronization Point immediately
after the reset handler switches to use the Process Stack
Pointer, during initialization.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 12:18:06 -05:00
Maureen Helm
55979aa3a5 arm: Add more flash and ram size options to i.MX RT MPU config
Adds 8 MB and 64 MB flash size options, which correspond to the two
external flashes (qspi flash and hyperflash) on the mimxrt1050_evk
board. Adds a 32 MB SRAM size option, which corresponds to the external
sdram on the board.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-08 17:39:28 -05:00
Gil Pitney
7f271b8689 cc3220sf: soc: Update PRCM call to allow use of ROM API
The API in the current SDK version is rom-patched, and uses
prcm.c code in the driverlib directory.

But, the PRCMMCU3200Init() API call should be prefixed by MAP_
to allow the option to use the ROM API in a future TI SDK version.

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-08 17:35:25 -05:00
Andrew Boie
3d69198843 arm_mpu: fix off-by-one in mpu_buffer_validate
The loop that checks the MPU region permissions incorrectly
iterates from (num_region + 1) to 1. This should be
(num_region - 1) to 0. This results in the wrong regions
being checked and possible overflow for any implementation
that uses the max region value of 0xFF.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-08 08:56:38 -07:00
Diego Sueiro
e8e76ae433 arch: Add imx7d_m4 gpio definitions
Adds all necessary gpio definitions and configurations for imx7d_m4 soc.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-05-08 06:56:56 -05:00
Ulf Magnusson
547ed9b563 kconfig: Make 'source' non-globbing and use 'gsource'
Until now, Zephyr has used a patched Kconfiglib that turns 'source' into
a globbing source (by replacing 'source' with 'gsource' at the token
level). There's two problems with this:

  - The patch needs to be maintained separately

  - Misspelled filenames are silently ignored, as they look like glob
    patterns that don't match anything

Fix it as follows:

  1. Replace all 'source' statements that use wildcards with 'gsource'

  2. Remove the custom Kconfiglib patch so that 'source' no longer globs

The sed pattern '/source.*[*?]/s/source/gsource/' was run over all
Kconfig* files to do the replacement.

source's that use environment variables that might contain glob patterns
were manually changed to gsource.

Building the docs in doc/ is a good test, as doc/Makefile deliberately
sets the environment variables to glob up as many Kconfig files as
possible.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-05-08 11:14:12 +02:00
Ioannis Glaropoulos
8d1b013f3c arch: arm: thread built-in stack guard implementation
This commit activates the built-in stack guard on the main_thread
before jumping to it upon system initialization. Stack guard is
activated if BUILTIN_STACK_GUARD is enabled by the user. The
commit also activates built-in thread stack guards at every
context switch, if BUILTIN_STACK_GUARD enabled by the user.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ioannis Glaropoulos
91dc3bd0f9 arch: arm: ignore stack pointer limit checks during HF and NMI
Ignore stack pointer limit checking during a HardFault or NMI
exception, to allow for the Fault handling function to execute
properly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ioannis Glaropoulos
4a41f42e73 arch: arm: set interrupt stack protection with MSPLIM
This commit implements the build-in interrupt stack protection
via the native MSPLIM register in ARMv8-M MCUs that support the
Main Extension. Main stack pointer overflows will cause Stack
Overflow UsageFaults. In addition, the commit introduces a new
config option, BUILTIN_STACK_GUARD, allowing the user to enable
and use the built-in stack protection in ARMv8-M firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ramakrishna Pallala
15447fa1d8 drivers: dma: Add dma driver for Nios-II MSGDMA core
Add dma driver for Nios-II Modular Scatter-Gather DMA soft IP.

This driver relies upon the Altera HAL msgdma driver for all
the dma core register programming and interrupt handling.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-03 10:38:09 -04:00
Ramakrishna Pallala
4073db79d7 arch: nios2: Add _nios2_dcache_flush_no_writeback() routine
Add _nios2_dcache_flush_no_writeback() routine to invalidate
cache contents of address provided.

This routine is ported from Altera Nios-II SDK v17.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-03 10:38:09 -04:00
Alberto Escolar Piedras
e3efbd54c6 POSIX arch: Fix linker -T warning
Modify the linker script with the command INSERT.
It instructs the linker to augment the default linker script
SECTIONS with the ones provided with the one provided in
this script.
It also modified the meaning of the -T switch, so it no longer
replaces the default linker script

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-05-02 10:19:09 -04:00
Wayne Ren
6c65ac2bb4 arch: arc: fix the typo of label which caused issue #7249
* fix the issue #7249 which is caused by a typo of label

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-02 09:31:00 -04:00
Yannis Damigos
2fd277fccf arch/arm/soc/st_stm32/stm32f1: Add I2C1 to dts.fixup
This patch adds the missing defines for I2C1.

Fixes #7248.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-02 01:11:36 -04:00
Savinay Dharmappa
7be3236ca4 dts: interrupt_controller: Add dts support for DesignWare controller
Add dts support for multilevel DW interrupt controller

Change-Id: Ia16d6870bd3a46fca933c906aedc6ba78ed5131a
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
9ee4929d56 dts: i2c: Add dts support for i2c
Change-Id: I9104f5230a4efbf1b6979e146e7ea73a76891947
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
97f721d928 dts: xtensa: Add device tree support for xtensa
Change-Id: I309bc50c6b575caa84fbc7ab98cc9890771b4274
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
5060f4bd14 driver: usb: enable usb2.0 on intel_s1000
Change-Id: I59091c465e84f1d6ba64433b7320182d83ff9589
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
5b6f02442b drivers: i2s: introduce CAVS I2S
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.

Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
cea1c75e2b boards: intel_s1000_crb: enable DMA
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.

Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
bd0d5133e4 drivers: dma: introduce Intel CAVS DMA
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.

This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.

Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
08172cdf83 xtensa: provide XCC compiler support for Xtensa
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.

ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
		RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/

Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
dadf9e7a81 xtensa: intel_s1000: implement interrupt mechanism
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.

Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
9cc381c07a intel_s1000: i2c: enable I2C for intel_s1000
intel_s1000 makes use of DesignWare IP for I2C.

Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
63d50e158e intel_s1000: gpio: enable GPIO handling
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.

Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
9ed55af2f8 arch: xtensa: set __start as entry point for Xtensa.
__start is deemed the entry point for all architectures in Zephyr.
Accordingly, Xtensa code had to be modified a bit to fall in line
with this convention.

Change-Id: If3ed344721c9f2735378b866662a68d8d5795324
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
47ff96593f intel_s1000: uart: configure UART for intel_s1000
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.

Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
c9ace83c89 xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME]
Setting CACHEATTR from _memmap_cacheattr_reset is making
the intel_s1000 SoC get into some unknown state. Removing
it for intel_s1000_crb for now.

Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
02736e5935 intel_s1000: add intel_s1000_crb board
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).

Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
1fcd39b624 intel_s1000: define memctl_default.S and memerror-vector.S files
Define memctl_default.S and memerror-vector.S files. A reference
could be found in the Xtensa toolchain directories. These are
required for using cavs21_LX6HiFi3_RF3_WB16 Xtensa CPU mainly in
simulator. On boards which have ROM, these would have been already
defined in the ROM. Hence, the contents of these files will be
developed at a later time if required.

Change-Id: Idf52397bb6880c136525e69f47e09defcba7f036
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
f14d1be67f intel_s1000: Add intel_s1000 SoC
intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which
belongs to Xtensa family. This is being used in intel_s1000_crb.

Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Andrew Boie
de7f40acfb kconfig: fix menuconfig
"depends on" cannot use expressions as arguments, this statement
didn't actually do anything for kconfiglib.py and caused an
error with menuconfig.

There's currently no way to depend on a system heap being
present, however forthcoming patches move this feature away
from using the system heap anyway.

For now, if the user enables dynamic objects without defining
a system heap, they will get a build error.

Fixes #7266.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-30 09:22:48 -07:00
Yannis Damigos
d9cdf7bf30 arch/arm/soc/st_stm32: Fix typos in soc.h
Fix typos in soc.h for stm32f1 and stm32l4 families.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-04-28 20:46:08 +05:30
Manivannan Sadhasivam
42a7c5732f arm: soc: Elaborate Kconfig strings for MPU selection
Some of the SoCs specify "Enable MPU" in Kconfig for enabling MPU
support. This will create ambiguity while selecting options via
menuconfig. Hence, append SoC family name to the selection strings
to looks more elaborative.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Manivannan Sadhasivam
c36e5ac129 arm: Fix title for SoC configuration in Kconfig
The title for selecting the configuration options for SoC's should be
"SoC Configuration" not "Board Configuration".

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Ioannis Glaropoulos
c7d808f965 arch: arm: improve help text for PROGRAMMABLE_FAULT_PRIOS option
Improve the help text of ARM k-config option
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-27 17:41:24 +05:30
Kumar Gala
ae5e11bebc arm: soc: NXP: Enable SEGGER RTT on all NXP SoCs
It seems like SEGGER is supported across all the NXP SoC families so
lets enable it across all of them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-04-26 14:49:57 -05:00
Adithya Baglody
246f03c9e6 x86: minnowboard: Enable the userspace mode
This enables the MMU with PAE mode and also enables the userspace
mode.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-25 14:46:00 -07:00
Adithya Baglody
3e3d1a1c8c x86: minnowboard: Add support for enabling MMU
The required linker and gen_mmu.py support added for minnowboard.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-25 14:46:00 -07:00
Andrew Boie
31bdfc014e userspace: add support for dynamic kernel objects
A red-black tree is maintained containing the metadata for all
dynamically created kernel objects, which are allocated out of the
system heap.

Currently, k_object_alloc() and k_object_free() are supervisor-only.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-24 12:27:54 -07:00
Maureen Helm
adf5b36a78 lpc54114: Remove unused include in soc.c
The lpc54114 soc.c file included clock_config.h unnecessarily.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Maureen Helm
57e80e5345 ext: mcux: Reorganize imported drivers into soc family subfolders
We have been combining imported mcux drivers into a flattened directory
structure to maximize driver reuse, but the introduction of additional
nxp soc families (lpc and imx) to zephyr has introduced driver naming
conflicts. This caused us to rename and modify imported files, such as
fsl_gpio.c/h, to make them unique across all three nxp soc families.
This makes updating the the mcux drivers complicated, especially for the
lpc family.

Reoganize the mcux drivers into soc family subfolders, so we can just
copy all the drivers from an mcux distribution (which is done on an
soc-basis) into the appropriate soc family folder. Undo all of the
naming changes that occurred when lpc and imx drivers were originally
imported. Undo the accidental squashing of the kinetis watchdog and dcdc
drivers that occurred when the imx drivers were introduced.

The drawback to this approach is that we have duplicate files when the
same hw ip modules exist in multiple soc families, however there are
only few cases where this occurs, such as fsl_lpuart and fsl_trng.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Leandro Pereira
16472cafcf arch: x86: Use retpolines in core assembly routines
In order to mitigate Spectre variant 2 (branch target injection), use
retpolines for indirect jumps and calls.

The newly-added hidden CONFIG_X86_NO_SPECTRE flag, which is disabled
by default, must be set by a x86 SoC if its CPU performs speculative
execution.  Most targets supported by Zephyr do not, so this is
set to "y" by default.

A new setting, CONFIG_RETPOLINE, has been added to the "Security
Options" sections, and that will be enabled by default if
CONFIG_X86_NO_SPECTRE is disabled.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-24 04:00:01 +05:30
Andy Ross
15cb5d7293 kernel: Further unify _reschedule APIs
Now that other work has eliminated the two cases where we had to do a
reschedule "but yield even if we are cooperative", we can squash both
down to a single _reschedule() function which does almost exactly what
legacy _Swap() did, but wrapped as a proper scheduler API.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Andy Ross
8606fabf74 kernel: Scheduler refactoring: use _reschedule_*() always
There was a somewhat promiscuous pattern in the kernel where IPC
mechanisms would do something that might effect the current thread
choice, then check _must_switch_threads() (or occasionally
__must_switch_threads -- don't ask, the distinction is being replaced
by real English words), sometimes _is_in_isr() (but not always, even
in contexts where that looks like it would be a mistake), and then
call _Swap() if everything is OK, otherwise releasing the irq_lock().
Sometimes this was done directly, sometimes via the inverted test,
sometimes (poll, heh) by doing the test when the thread state was
modified and then needlessly passing the result up the call stack to
the point of the _Swap().

And some places were just calling _reschedule_threads(), which did all
this already.

Unify all this madness.  The old _reschedule_threads() function has
split into two variants: _reschedule_yield() and
_reschedule_noyield().  The latter is the "normal" one that respects
the cooperative priority of the current thread (i.e. it won't switch
out even if there is a higher priority thread ready -- the current
thread has to pend itself first), the former is used in the handful of
places where code was doing a swap unconditionally, just to preserve
precise behavior across the refactor.  I'm not at all convinced it
should exist...

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Ioannis Glaropoulos
0b7c964f5f arch: arm: clear BFSR sticky bits in ARMv8-M Mainline MCUs
Contrary to ARMv7-M, in ARMv8-M MCUs with the Main Extension,
BusFault Status Register bits are sticky and must be cleared.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-23 08:40:15 -05:00
Maureen Helm
50b69fbb55 arm: nxp_kinetis: Remove unused defines from soc.h
Now that we get gpio irq numbers from dts, we can remove the defines
from soc.h

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-20 08:54:11 -05:00
Ding Tao
b4696bd7ec arch: arm: Fix coding style in file irq_relay.S
Make the code more human readable by Remove some TABs.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-04-19 14:54:28 -05:00
Wayne Ren
adf6f48e0d arch: arc: add the support of STACK_SENTINEL
* call the _check_stack_sentinel in unnested isr
return.

* for firq, _check_stack_sentinel is called in kernel
  isr stack because the limitation of banked register

* for normal irq, _check_stak_sentinel is called in
  the interruptted thread stack

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
8da51ee326 arch: arc: optimize the _SysFatalErrorHandler
* For STACK_CANERY, the processor should not hang
* as _SysFatalErrorHandler is always executed in
  isr context, so remove k_is_in_isr
* the function should return after k_thread_abort

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
24acf2a414 arch: arc: bug fixes in irq_load
remove magic numer, use IRQ_OFFLOAD macro

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
3d9ba10b5c arch: arc: bug fixes and optimization in exception handling
The original exception handling has space to optimize and
and some bugs need to be fixed.

* define NANO_ESF
   * add the definition of NANO_ESF which is an irq_stack_frame
   * add the corresponding codes in exception entry and handler
   * remove _default_esf
* implement the _ARCH_EXCEPT
   * use trap exception to raise exception by kernel
   * add corresponding trap exception entry
   * add _do_kernel_oops to handle the exception raised by
     _ARCH_EXCEPT.
* add the thread context switch in exception return
   * case: kernel oops may raise thread context switch
   * case: some tests will re-implement SysFatalHandler to raise
     thread context switch.
   * as the exception and isr are handled in kernel isr stack, so
     the thread context switch must be in the return of exception/isr
     , and the exception handler must return, should not be decorated
     with FUNC_NORETURN
* for arc, _is_in_isr should consider the case of exception

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Andy Gross
09a8810b33 arm: userspace: Rework system call arguments
This patch changes the ARM system calls to use registers for passing
or arguments.  This removes the possibility of stack issues when
callers do not adhere to the AAPCS.

Fixes #6802

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-16 10:13:20 -07:00
Adithya Baglody
95126d1af6 boards: sam_e70_xplained: Enable userspace
Enabled userspace support for Atmel SAMe70.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-16 09:01:49 -07:00
Leandro Pereira
4d5fbbc517 arch: arm: Flush pipeline after switching privilege levels
During the transition of privilege levels while performing syscalls,
the ARM documentation recommends flushing the pipeline to avoid
pre-fetched instructions from being executed with the previous
privilege level.

The manual says:
   4.16 CONTROL register
   (...) after programming the CONTROL register, an ISB instruction
   should be used.
   (...) This is not implemented in the Cortex M0 processor.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-13 15:35:45 -05:00
Andrzej Głąbek
397e52f099 arch: nrf52: Correct the number of IRQs in nRF52840
The old value does not cover the IRQ assigned to the SPIM3 peripheral.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-04-12 14:19:53 -04:00
David Leach
c563e33102 drivers: entropy: Change KW41Z to use XOROSHIRO for RNG source
The TRNG IP block in the KW41Z is really an entropy source and not
intended to be used as a general purpose random number generator
source. The block has 15 slots to read from and when the last slot
is read it has to regenerate the 15 numbers. This process takes
3-5 seconds and is blocking. The change here is to use the TRNG as
an entropy source to the XOROSHIRO pseudo random number function
and then have the KW41Z use XOROSHIRO for random number generation.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
David Leach
00885bbf28 OpenThread: Normalize IEEE802.15.4 driver name for use by L2 layers
- Removed OT_PLAT_RADIO_DEVICE_NAME
- Changed OpenThread binding to use NET_AP_IEEE802154_DEV_NAME
- Modified Kconfig chain to ensure NET_AP_IEEE802154_DEV_NAME
  is enabled for both native 802.15.4 and OpenThread configurations
- Changed default setting of NET_L2_IEEE802154 in defconfig for mkw41z4.
- Fixed OpenThread api support code to use the state of mIsCcaEnabled
  in the transmit frame to conditionally invoke radio_api->cc() on
  transmits.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
Diego Sueiro
816330239e arch: Add imx7d m4 soc support
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.

The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:

+---------------+-----------------+---------------------------+
| Memory Name   | Start Address   | Size                      |
+===============+=================+===========================+
| TCML          | 0x007F8000      | 32KB                      |
+---------------+-----------------+---------------------------+
| TCMU          | 0x20000000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM_S       | 0x20180000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM         | 0x00900000      | 128KB                     |
+---------------+-----------------+---------------------------+
| DDR           | 0x10000000      | 256MB                     |
+---------------+-----------------+---------------------------+

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-04-11 08:27:05 +02:00
Erwan Gouriou
6c2047fcd0 arch/arm: stm32: All SoCs have dts for I2C and SPI
All boards based on STM32 should use dts for I2C and SPI.
Move CONFIG flags selection from boards to arch and select them
for all STM32 SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-04-10 08:27:50 -05:00
Andrew Boie
548421828e arm_mpu: fix _get_region_attr()
srd bits start at bit 8, not bit 5.
To date we are not using sub-regions so this problem was
undetected.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-09 17:15:15 -05:00
Ilya Tagunov
77bbc42eaf arch: arm: soc: stm32l0: fix port H EXTI
Ports F and G are not present on some STM32L0 parts, so
for these parts port H external interrupt should be enabled
by writing value 0x5 instead of 0x7 to SYSCFG_EXTICRn registers
(see e.g. RM0367, 10.2.4).

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-04-05 10:31:43 -05:00
Tomasz Jurtsch
6dae38cb98 arch: riscv32: fe310: Always-On domain adress definition
Added always-on domain address definition

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-05 08:08:08 -05:00
Paolo Teti
700e4bd2e8 ARM: -march compile option is not set
Removing ${} variable evaluation fixes the issue.

For sam4s_xplained:

Before:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
/repos/zephyr/samples/hello_world/build$

After:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
...
-mthumb -mcpu=cortex-m4 -march=armv7e-m
...

Signed-off-by: Paolo Teti <paolo.teti@gmail.com>
2018-04-05 08:36:04 -04:00
Tomasz Bursztyka
a868561339 arch/quark_se: Enable SPI port 2 as a slave only
Quark SE provides a slave SPI.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
1ac6f4bd56 arch/quark_d2000: Switch to SPI DW driver
As QMSI driver does not support new SPI API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
4652f59d64 arch/quark_se_c1000_ss: Switch to SPI DW driver
As QMSI driver does not support new SPI API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
6d870ae25c arch/quark_se: Switch to native SPI DW driver
QMSI is not updated to latest SPI API. Switching to native DW driver,
until we find a way either to update the shim drivers in a
non-performant way, or updating QMSI itself enabling support for
scatter-gather type of buffers.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
324265420b api/spi: Disable legacy API by default
Let's start deprecation work of the SPI legacy API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Youvedeep Singh
4a8b2d2d2f kernel: POSIX: Compatibility layer for POSIX message queue APIs.
This patch provides POSIX message queue APIs for POSIX
1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-04-03 15:30:44 -04:00
Ulf Magnusson
c9c18fa8b0 kconfig: Do not source "arch/posix/core/Kconfig"
This file never existed.

'source' currently ignores missing files instead of throwing an error,
due to Zephyr's custom globbing logic.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-03-30 17:51:39 -04:00
Ulf Magnusson
93689bdc80 kconfig: Remove no-op selects of choice symbols
Selecting a choice symbol is always a no-op, and the latest version of
Kconfiglib prints a warning. This commit removes all selects of choice
symbols, which might make the Kconfig files a bit clearer and gets rid
of the warnings.

This is just a dumb removal. I did not try to guess the intent of each
select.

Fixes #6849

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-03-29 08:57:39 -04:00
Anas Nashif
993c350b92 cleanup: replace old jira numbers with GH issues
Replace all references to old JIRA issues (ZEP) with the corrosponding
Github issue ID.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-26 13:13:04 -04:00
Kumar Gala
8a824356e0 arch: arc: em{7,9,11}d: Add initial DTS UART support
Add support for getting some basic params from the DTS for the UART.
The ns16550 driver still needs to be updated to get IRQ and address
info from DTS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Kumar Gala
311e6b9e3e arch: arc: Use DTS for all ARC SoCs
Now that all ARC SoCs we can remove code associated with !HAS_DTS and
select HAS_DTS at the architecture level.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Kumar Gala
60ec8be309 arch: em{7,9,11}d: Add dts support
Add initial device tree support for the em{7,9,11}d SoC and associated
em_starterkit boards.  The device tree at this point specifies cpu core,
memory, interrupt controller, uart's and i2c controllers.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Tomasz Bursztyka
74d1835505 drivers/i2c: Make QMSI SS driver IRQs set via CONFIG_ options
Now that dts i2 qmsi ss nodes generate the right options, let's use
them. Apply the relevant fixup on the targeted SoC.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
7af98f5e67 drivers/i2c: Use standard bitrate settings for QMSI SS driver
Apply the change on relevant arch/boards.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
9b77741d63 drivers/i2c: Use standard bitrate settings for QMSI driver
Apply the change on relevant arch/boards.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
2e972bc867 arch/x86: Enable i2c through DTS for quark_d2000
And adapt the relevant board accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
5fc1f5ff1d arch/x86: Enable i2c through DTS for quark_se
And adapt relevant boards accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
8f891ba702 drivers/i2c: Use standard bitrate settings for DW driver
Applying the change to relevant arch/boards, either in their Kconfig or
the dts specific files.

Taking the opportunity in dw driver to rename the variable the same way
as they are everywhere else in the code (s/dev/dw and s/port/dev) in
init function.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
e35a4a2576 boards/galileo: Switch to DTS for generating i2c settings
Thus dropping SoC based generated information.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
9ddd8d1e4d arch/x86: Enable i2c through DTS for quark_se SS
And adapt relevant boards accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
6d247b5c2b drivers/i2c: Rename generic configure option in DW drivers
And adapt SoC's information relevantly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
d95fa65270 drivers/i2c: Cleanup Kconfig
Move driver specific to dedicated file when relevant (i.e.: more than
1-2 options), use if/endif also.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Carles Cufi
6656969598 arch: arm: nordic_nrf: Restore copyright years
A previous commit had mistakenly overwritten the copyright years instead
of extending the range. Fix this mistake so that the proper range is
recorded.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 13:25:44 +01:00
Carles Cufi
b2016da563 arch: arm: nrf: Rename common header to apply to all nRFx ICs
The existing nrf5_common.h now applies to other Nordic ICs that are not
part of the "5" family. Instead rename this to nrf_common.h to cover the
upcoming ICs that belong to other families.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Carles Cufi
f49150cab6 arch: arm: nrf: Rename nrf5 SoC Family to nrf
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Anas Nashif
e5f1b51f01 debug: fix RTT console Kconfig
Use HAS_ Kconfig option as intended, those are invisible option that
signify support of a certain feature that can be selected by a hardware
or platform.

For RTT and system view this was not dont in an inconsistent way.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-19 15:37:26 -04:00
Ilya Tagunov
48a5fbcaa9 drivers: flash: stm32f0: remove CONFIG_FLASH_PAGE_SIZE
STM32F0 flash driver already uses FLASH_PAGE_SIZE from HAL
in flash layout part, so CONFIG_FLASH_PAGE_SIZE is redundant
and confusing.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-18 17:02:53 -04:00
Andy Ross
9d367eeb0a xtensa, kernel/sched: Move next switch_handle selection to the scheduler
The xtensa asm2 layer had a function to select the next switch handle
to return into following an exception.  There is no arch-specific code
there, it's just scheduler logic.  Move it to the scheduler where it
belongs.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-18 16:58:12 -04:00
Andrew Boie
a967915e52 arch: add Kconfig for stack growth direction
This was previously just a #define in one header file, but we need
this expressed in Kconfig space in case some feature only works
properly with downward-growing stacks.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 16:25:22 -07:00
Leandro Pereira
2f5659d4d2 arch: x86: Unwind the stack on fatal errors
Prints up to 8 stack frames, with the following format:
  RETURN_ADDR(ARGUMENTS)

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-03-16 14:12:15 -07:00
Andrew Boie
e00564d15d x86: fix logic for thread wrappers
If we enable CONFIG_DEBUG_INFO, then we need to fixup the stack
on thread entry so that the EFLAGS value in the EBP slot doesn't
confuse the debugger or any runtime stack unwinding code.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 14:12:15 -07:00
qianfan Zhao
494bf56811 arch: arm: soc: stm32f0: add STM32F070XB SOC
Add initial support for STM32F070XB SOC

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-03-16 09:18:08 -05:00
Ilya Tagunov
00c0520247 arch: arm: soc: stm32l0: add I2C support
Add SPI support for STM32L0 series.
L0 SPI peripheral requires SCK pin speed workaround
to function properly.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-15 10:53:26 -05:00
Kumar Gala
0ecd77e435 arch: arc: quark_se_c1000_ss: Fix DCCM_SIZE
The DCCM_SIZE is defined in terms of K, not bytes, so we need to adjust
it from bytes (generated from dts) to K (used by e CONFIG_DCCM_SIZE).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-15 08:14:27 -05:00
Sundar Subramaniyan
037dddbe8f dts: arm: nrf52840_pca10056: Use DT to configure USB
Configure USB using DT for nrf52840_pca10056

Signed-off-by: Sundar Subramaniyan <sundar.subramaniyan@gmail.com>
2018-03-15 12:39:53 +01:00
Ilya Tagunov
9ae3fdc2ef arch: arm: soc: stm32l0: add I2C support
Add I2C support for STM32L0 series. LL-based driver
was already in place, so I've just enable it.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-14 09:02:25 -05:00
Kumar Gala
c9b0208552 arm: mps2_an385: Move dts.fixup to board dir
Move the dts.fixup back to board dir in prep for support mps2_an521.
The memory maps between the two mps2_an385 and mps2_an521 differ greatly
so its easier to just keep the fixup files with the board.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-13 15:29:21 -05:00
Carles Cufi
9afb0cfab0 kconfig: Remove UTF-8 character from author's name
Kconfiglib does not support UTF-8 properly yet, so avoid issues by
removing the UTF-8 character from the name until this is fixed.

See https://github.com/ulfalizer/Kconfiglib/pull/41

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-13 20:30:15 +01:00
Ioannis Glaropoulos
5475de105b arch: arm: define the ARM_SECURE_FIRMWARE option
This commit introduces the ARM_SECURE_FIRMWARE k-option,
which indicates that we are building an ARM Secure application.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ioannis Glaropoulos
a01e7903b2 arch: arm: SecureFault Handling for Cortex-M33
This commit contributes the implementation of the SecureFault
handling for ARMv8-M-based Cortex-M33. The implementation is
compiled conditionally with compile-time directive
CONFIG_ARM_SECURE_FIRMWARE, which is to signify the intention to
build a Secure image on ARMv8-M with Security Extensions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ilya Tagunov
b6da79cb82 arch: arm: soc: stm32l0: add STM32L073xZ SOC
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Ilya Tagunov
6a1cb6540f arch: arm: soc: stm32l0: fix indentation and comments in Kconfigs
Fix indentation and small comment typos in Kconfigs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Aapo Vienamo
422bc240b4 soc: nrf5: Use i2c configure options generated from dts
SoC dts fixups are added and the i2c_nrf5 driver is modified to use
the values generated from the device tree.

The I2C_*_DEFAULT_CFG and I2C_*_IRQ_PRI options are removed from board
defconfigs. Bitrate and IRQ priority are configured using using the
device tree instead.

HAS_DTS_I2C is selected on all nrf5 boards to prevent generation of
conflicting defines from Kconfig.

Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi>
2018-03-13 14:14:13 +01:00
Ioannis Glaropoulos
c028f88b37 arch: arm: remove redundant asm inline headers
This commit removes the unnecessary asm inline header for ARM.
It also adapts the stack.h and exc.h to use the ARM CMSIS inline
functions to access the IPSR and MSP registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-12 10:14:12 -05:00
Ioannis Glaropoulos
10b40ecaba arch: arm: conditionally select FP extension in cortex-m MCUs
This commit conditionally selects the ARMV7_M_ARMV8_M_FP option
in ARMv7-M/ARMv8-M Mainline processors, when the Floating Point
Extension is implemented (CPU_HAS_FPU is selected).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-11 21:53:50 -05:00
Ioannis Glaropoulos
b75b01050d arch: arm: Stack Overflow Usage Fault log for ARMv8-M Mainline
This commit contributes the Stack Overflow UsageFault dumping
for ARMv8-M implementations that support the Main Extension.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
cfab6e0806 arch: arm: define ARMv8-M Mainline K-option
This commit introduces the ARMV8_M_MAINLINE K-config option. The
option signifies the use of an ARMv8-M CPU supporting the Main
Extension. ARMv8-M Main Extension includes additional features
that are  not present in the ARMv7-M architecture.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
d2e0d975f6 arch: arm: ARMv7-M/ARMv8-M Mainline dependency for programmable prios
This commit forces CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS to
depend on ARMV7_M_ARMV8_M_MAINLINE. This allows the user to get
a build warning if he manually selects
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS for a CPU that does
not implement either ARMv7-M or ARMv8-M Mainline.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Kumar Gala
97331d1e98 arch: arm: mps2: Remove soc_irq.h
Move IRQ numbers into device tree so we can remove soc_irq.h.  We are
already using IRQ defines generated form the DTS so no point in having
soc_irq.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
fa0e8fd06d arch: arm: mps2: remove soc_memory_map.h
Further simplify the mps2 SoC code by removing soc_memory_map.h which
now only contains one define for the FPGAIO_BASE_ADDR.  We can just move
this to the once place its used.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
40b7be5197 drivers: i2c: Add DTS support to ARM SBCon I2C controller
Added device tree support to the ARM SBCon I2C controller.  We utilize
the compatiable "arm,versatile-i2c" the binding from Linux for the some
peripheral block.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
51db7b142c arch: arm: mps2: Remove unused defines and structs
Simplify the mps2 SoC code by removing defines and structs that aren't
used anywhere currently.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
ad18f84f50 arch: arm: Refactor CONFIG_CORTEX_M
Clean up Kconfig so each SoC just selects the specific Cortex-M
implementaiton rather than having to select both CORTEX_M and
CORTEX_{M0, M3, M4, etc.}.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Justin Watson
aa7c91d0c2 driver: usart: Added support for interrupt driver USART on SAM E70.
Added interrupt support in the USART SAM serial driver.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-03-10 11:42:25 -06:00
Ioannis Glaropoulos
3b2f4b399d arch: arm: add missing floating-point fault logging
This commit adds the missing fault dumping for MemManage or Bus
fault occuring during floating-point lazy state preservation. In
addition, it introduces a Kconfig option for the ARMv7-M/ARMv8-M
Floating Point Extension.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 11:42:25 -06:00
Justin Watson
b9c65e1882 drivers: GPIO Added GPIO for SAM family.
Added GPIO driver for SAM family of SoCs.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-03-10 11:42:25 -06:00
Ioannis Glaropoulos
bd0ff3092a arch: arm: cmsis: cleanup cmsis.h and update error-code macros
This commit removes the macros for ARM fault flags from
include/arch/arm/cortex_m/cmsis.h header, since they are
defined in the respective core_cmXX.h header files. It also
modifies fault.c to use the updated fault macros taken directly
from ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 11:42:25 -06:00
Philémon Jaermann
8834a8d47b arm: stm32f446: Add support for stm32f446 SoC
Support for stm32f446xe SoC

Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
2018-03-10 11:42:25 -06:00
Endre Karlson
deeb74651b arm: stm32l0: Add support for stm32l0 soc
Add necessary kconfig and minimal device tree support for
the stm32l072xz variants.

Signed-off-by: Endre Karlson <endre.karlson@gmail.com>
2018-03-10 11:42:25 -06:00
Yannis Damigos
efbb7c61a1 arch/arm/soc/stm32f4: Add STM32F412CG MCU support
Add STM32F412CG MCU support.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-03-10 11:42:25 -06:00
a8a36a23fc spi: sam0: use Device Tree for configuration.
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.

Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances

Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.

Add the APA102 LED that's on the Trinket as a test.

Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Nathan Tsoi
28758fe986 arch: arm: STM32F051X8 support
Add support for the STM32F051X8 processor on the STM32F0DISCOVERY board

Signed-off-by: Nathan Tsoi <nathan@vertile.com>
2018-03-10 11:42:25 -06:00
f2651d0cc7 usb: sam0: add a USB device driver.
Implements a USB device driver for the SAM0 series.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-03-10 08:41:39 -05:00
Andy Gross
cc69d373d1 arch: arm: Change method of __swap processing
This patch reworks the current ARM __swap() function into a C function.
Due to some issues with using svc calls withing fault handlers, we
needed to change the way we initiate a swap by removing the dependence
on svc #0.

Before __swap() is called, the system has already done an irq_lock().
Upon return from __swap(), the equivalent of an irq_lock() is done due
to restoration of the key value from the irq_lock preceeding the call.

For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are
enabled.  There is no priority masking in v6m, so it's just a global
enable.  For ARM V7M, the priority mask has to be set to 0x0 to allow
for the pendsv IRQ to be taken.  This is done for both via a call to
irq_unlock(0).

After this unlock, a pendsv irq will be taken, either at the tail end
of the current irq handling if we are in handler mode, or immediately
due to the pendsv being asserted (no other outstanding irqs).  The next
thread will be scheduled.

Upon return from the context switch to the original
thread, the priority mask will already be correct due to the pendsv
processing.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-09 21:43:23 -05:00
Wayne Ren
2c577ff90e arch: arc: fix the bug of context switch in interrupt
* the bug comes out when a context switch happens in interrupt
* the bug only affects the em7d in emsk 2.3
* the bug is caused by
  * wrong operations of stack
  * wrong setting of SEC_STAT's IRM bit

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-03-08 11:01:11 +01:00
Wayne Ren
6612c9f683 arch: arc: bug fixes in arc mpu driver
fix the bug in _is_in_region
* RDB0 -> RDP0

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-03-08 11:01:11 +01:00
Andrzej Puzdrowski
c788f84f25 drivers: flash: move FLASH_HAS_PAGE_LAYOUT Kconfig from arch
Keyword FLASH_HAS_PAGE_LAYOUT is related to flash and should
be declared in its Kconfig.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-03-08 10:18:57 +01:00
Andrew Boie
c0771ea243 arch: x86: fix integer stub comments
The comment was obsolete; we simply do not allow use of the FPU or
vector math in ISRs. There is no desire to add such support, doing
this is properly offloaded to a worker thread.

Fixes #5283.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-06 17:16:03 -05:00
Andy Ross
285c5b26dd xtensa/asm2: Save shift/loop registers on exception entry
This was a little embarassing.  The swap code got this right, and the
interrupt exit path got it right, but on entry we weren't ever saving
the shift and loop registers for the interrupted context.

This almost always worked anyway as the loop registers aren't ever
used in any Zephyr code (gcc won't generate this style of loop AFAICT)
and the SAR shift amount register is generally used only in two pairs
of adjacent instructions making the chance of hitting that exact cycle
quite low in general.

But of course we have shift-happy crypto code in our tests, so this
got caught, thankfully.

See https://github.com/zephyrproject-rtos/zephyr/issues/6470

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-06 14:13:56 -08:00
Ioannis Glaropoulos
8c0c4be16a arch: arm: remove redundant dependence on ARM_CORE_MPU
MPU_STACK_GUARD option has a direct dependence on ARM_CORE_MPU.
Therefore, it is not required to have a conditional selection
of the option (if ARM_CORE_MPU) in ARM_STACK_PROTECTION.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-06 08:36:34 -05:00
Punit Vara
a74725f1d3 kernel: Add posix API for semaphore
Add semaphore posix APIs.

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-03-05 20:51:36 -05:00
Leandro Pereira
02bc5fa8e0 soc: esp32: Enable building with newer ESP-IDF
ESP-IDF commit cb31222e added the dependency on a file named
"sdkconfig.h", which is equivalent to "autoconf.h" generated by kbuild
used in Zephyr.  It does not depend on anything from that file, though,
so just provide an empty file to keep the compiler from complaining.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-03-05 19:49:06 -05:00
Youvedeep Singh
216883ca82 kernel: POSIX: Compatibility layer for POSIX read-write lock APIs.
This patch provides POSIX read-write lock APIs for POSIX 1003.1
PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-03-05 19:27:37 -05:00
Andy Ross
bdac8d070f xtensa/asm2: Fix stack pointer during preemption spills
When returning into a different thread than we interrupted, we
obviously need to spill all the existing register windows to make sure
all their values are in the old thread's stack.  But the code to do
this forgot to reset the current stack pointer to the value it had at
interrupt time (it was still pointing to the saved context below
that), so the caller of the interrupted function was spilling to the
wrong spot.

This wouldn't show up as an instant failure, it would only happen when
switching BACK to the improperly-spilled thread.  And even then it
would be a noop if the original interrupt handler was deep enough to
have spilled that function naturally.

In practice, this happened only in some instances on ESP-32 (which has
more windowed registers than qemu) when interrupting the idle thread
(which is very shallow) with a (very simple) timer interrupt.  Trivial
to see, hard to find.

See https://github.com/zephyrproject-rtos/zephyr/issues/6346 for more
detail.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-05 19:06:07 -05:00
Ioannis Glaropoulos
571069e986 arch: arm: correct fault address logging
In ARMv7-M (and ARMv8-M) architecture it is
implementation defined whether separate MMFAR and BFAR are
implemented. This commit ensures that we always get the true
faulting address displayed in case of MemManage- or BusFault.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-27 09:38:43 -06:00
Kumar Gala
83fa6c9554 dts: arm: Refactor SoC dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into arch/arm/soc/<SOC>/dts.fixup so
we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
dc6472f868 dts: x86/atom: Refactor SoC dts.fixup into arch/x86/soc/atom
Move common SoC dts.fixup defines into arch/x86/soc/atom/dts.fixup so we
remove duplication in the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
d08661119e dts: ia32: Refactor SoC dts.fixup into arch/x86/soc/ia32
Move common SoC dts.fixup defines into arch/x86/soc/ia32/dts.fixup so we
remove duplication in the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
7e32b1d11f dts: quark_se: Refactor SoC dts.fixup into arch/x86/soc/intel_quark/<SOC>
Move common SoC dts.fixup defines into
arch/x86/soc/intel_quark/quark_se/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
6becb64dfc dts: quark_se_c1000_ss: Refactor dts.fixup into arch/arc/soc
Move common SoC dts.fixup defines into
arch/arc/soc/quark_se_c1000_ss/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arc/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Alberto Escolar Piedras
f004e0475e native: added more proper command line parameters parsing
Added a basic command line parameter parsing framework

Added the following options by now:
--stop-at=<time>: Auto-stop after <time> seconds
--seed=<seed>   : random seed for entropy device
--testargs      : any argument that follows is ignored in top level
                  and made available thru
                  native_get_test_cmd_line_args()

All command line parameters are still avaliable by calling
native_get_cmd_line_args(), but now you can also call
native_get_test_cmd_line_args() to get whatever was set after
--testargs

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-23 07:33:11 -05:00
David B. Kinder
3673698df1 doc: fix misspellings in XTENSA Kconfig
regular scan for spelling issues

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-22 15:28:04 -05:00
Youvedeep Singh
4d72e48d31 arch: POSIX: Add guard into posix_cheats file.
Some of APIs of POSIX implmentation layer has same name as
native_posix architecture. posix_cheats.h is used to handle this
duplication in API name. Adding a guard in posix_cheats.h based on
CONFIG_PTHREAD_API.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
8d040f1bcb kernel: POSIX: Compatibility layer for POSIX timer APIs.
This patch provides POSIX timer APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
d50b1fe981 kernel: POSIX: Compatibility layer for POSIX clock APIs.
This patch provides POSIX clock APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
1f2e126d4d kernel: POSIX: Compatibility layer for POSIX sleep APIs.
This patch provides POSIX sleep APIs for POSIX 1003.1 PSE52 standard.
sleep(n) is implemented using Zephyr k_sleep API.
uleep(n) is implemented using Zephyr k_sleep/k_busy_Wait API.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
7eabf1025c kernel: POSIX: Compatibility layer for scheduler APIs.
This patch provides scheduler APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
c8aa6570c1 kernel: POSIX: Compatibility layer for pthread APIs.
This patch provides pthread APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
2e7146b7a6 arch: refactor the SAM0 SoC fixups into a SoC-level file.
This prepares the way for the Trinket M0.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-02-21 16:03:10 -06:00
Kumar Gala
87a8d199d8 dts: atmel_sam: Refactor SoC dts.fixup into arch/arm/soc/atmel_sam
Move common SoC dts.fixup defines into
arch/arm/soc/atmel_sam/<BAR>/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 16:02:12 -06:00
Kumar Gala
a73e8fa083 dts: nxp: Refactor imx/rt dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into arch/arm/soc/nxp_imx/rt/dts.fixup
so we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
4c50b1f199 dts: nxp: Refactor kwx dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kwx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
8760edd6a5 dts: nxp: Refactor kl2x dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kl2x/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
29d4ea327f dts: nxp: Refactor lpc54xxx dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
340bc66f24 dts: nxp: Refactor k64 dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/k6x/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
5a5e352899 dts: ti: Refactor TI SoC dts.fixup into arch/arm/soc/ti_simplelink
Move common SoC dts.fixup defines into
arch/arm/soc/ti_simplelink/<BAR>/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 10:57:23 -06:00
Yannis Damigos
22c1018bfb dts: arm: 96b_carbon use DT to configure USB
Configure USB using DT for 96b_carbon

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-21 09:17:12 -06:00
Leandro Pereira
3beb481bab soc: esp32: Fix compile warnings when redefining BIT() macro
Include `soc.h` first, which will include the ESP-IDF headers -- which
will define the `BIT()` macro without checking if they're already
defined, like the Zephyr headers do.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-02-20 16:23:53 -05:00
Daniel Wagenknecht
44bfd32f22 dts: spi: add remaining SPI fixup defines for STM32
Add SPI fixup defines on STM32 SoC family level for all SPIs that
are supported on one or more SOCs of that SoC family.

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-02-20 09:47:43 -05:00
Andy Ross
60fd06830e xtensa: Make _arch_curr_cpu() work outside SMP
The xtensa headers use this for simplicity when SMP is not enabled.
It should still build on older platforms that don't include the
asm2-style CPU pointer scheme.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
392b3b5aa6 xtensa/asm2: Don't needlessly build asm2 sources
Non-asm2 devices without a generated SoC interrupt file will see a
compile failure due to the missing header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
57f30bd8cc esp32: Move hard firmware function addresses to the linker script
This matches the way other firmware-provided functions are done.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
0244d01fda xtensa/asm2: Don't return into dead threads
It's not impossible that something we just handled (e.g. a machine
exception) called k_thread_abort() on our current thread.  Don't try
to return into it, check the DEAD state.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
3f5027f835 xtensa: Fix noreturn attribute on error handlers in asm2
In asm2, the machine exception handler runs in interrupt context (this
is good: it allows us to defer the test against exception type until
after we have done the stack switch and dispatched any true
interrupts), but that means that the user error handler needs to be
invoked and then return through the interrupt exit code.

So the __attribute__(__noreturn__) that it was being decorated with
was incorrect.  And actually fatal, as with gcc xtensa will crash
trying to return from a noreturn call.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
c3c4ea730d nios2: Add include for _check_stack_sentinel()
This API moved into kswap.h and the resulting warning on this arch got
missed.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
245b54ed56 kernel/include: Missed nano_internal.h -> kernel_internal.h spots
Update heading naming given recent rename

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
53eceffb7f esp32: Set CPU pointer on app cpu at startup
It's not enough to wait for a switch, lots of things need this early.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
b0b9b3d16a xtensa: Report CPU number in exceptions
In SMP contexts it's good to know which CPU blew up.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
e694656345 kernel: Move per-cpu _kernel_t fields into separate struct
When in SMP mode, the nested/irq_stack/current fields are specific to
the current CPU and not to the kernel as a whole, so we need an array
of these.  Place them in a _cpu_t struct and implement a
_arch_curr_cpu() function to retrieve the pointer.

When not in SMP mode, the first CPU's fields are defined as a unioned
with the first _cpu_t record.  This permits compatibility with legacy
assembly on other platforms.  Long term, all users, including
uniprocessor architectures, should be updated to use the new scheme.

Fundamentally this is just renaming: the structure layout and runtime
code do not change on any existing platforms and won't until someone
defines a second CPU.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
9c62cc677d kernel: Add kswap.h header to unbreak cycles
The xtensa-asm2 work included a patch that added nano_internal.h
includes in lots of places that needed to have _Swap defined, because
it had to break a cycle and this no longer got pulled in from the arch
headers.

Unfortunately those new includes created new and more amusing cycles
elsewhere which led to breakage on other platforms.

Break out the _Swap definition (only) into a separate header and use
that instead.  Cleaner.  Seems not to have any more hidden gotchas.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
d3376f2781 kernel, esp32: Add SMP kconfig flag and MP_NUM_CPUS variable
Simply define the Kconfig variables in this patch so they can be used
in later patches.  Define MP_NUM_CPUS correctly on esp32.  No code
changes.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
e717267abf kernel, esp32: Add _arch_start_cpu API
This is a mostly-internal API to start a secondary system CPU, with an
implementation for the ESP-32 "APP" cpu.  Exposed in kernel.h because
it's plausibly useful for asymmetric MP code managed by an app.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
00f3d2e53a esp-32, qemu_xtensa: Use asm2 by default
Set these SoCs to use asm2 by default

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
865bbd6b69 xtensa-asm2: Handle alloca/movsp exceptions
Xtensa register windows have a special exception that happens when the
stack pointer needs to be moved, but the caller function has already
spilled its registers below it.

I thought these were unexercised in Zephyr code, but they turn out to
be thrown by the existing mem_pool tests when run in the 32-register
qemu environment (but not on 64-register hardwre).  Because the effect
of the exception is to unspill the caller, there is no good way to
handle this in a traditional handler.  Instead put a 5-instruction
stub in front of the user exception handler (i.e. incurring that cost
on every trap and every L1 interrupt) to test before doing the normal
entry.

Works, but would be nicer to optimize this in the future so that only
true alloca exceptions take that cost.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
bbd7912a6b xtensa-asm2: Exception/interrupt handler should check stack sentinel
This got forgotten.  Note that this function is empty if
CONFIG_STACK_SENTINEL is unconfigured.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
60932d1427 xtensa: Add hook to do register window spills
This macro was already available add an external symbol so C code can
access it (via CALL0 -- it's not and can't be an actual function).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
2867bfc1eb xtensa asm2: Fixup stack alignment at runtime
The API allows any byte count for stack size, and tests in fact check
that a stack with a 499 byte stack works correctly.  No choice, have
to do this at runtime.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
02b2fe1c9e xtensa: THREAD_MONITOR hooks for asm2
You'd this feature would be portable, but it's arch-specific.
Initialize the CONFIG_THREAD_MONITOR stuff, placing the __thread_entry
struct (which AFAICT is dead: nothing in the tree actually reads it)
at the top of the stack.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
7707fcfa51 xtensa: asm2 needs to honor thread preemption
Forgot to check the thread preemption status when fetching the stack
to restore.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
63ad74f833 xtensa: Fix thread entry point
The stack initilaization was calling the user-provided entry function
directly, which works fine until that function returns, at which point
it will try to unspill A0-A3 from the 16 bytes above the allocated
stack and then "return" to a NULL pointer.

The kernel provides a _thread_entry() function that does cleanup
properly, so use that.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
2c1449bc81 kernel, xtensa: Switch-specific thread return value
When using _arch_switch() context switching, the thread return value
is a generic hook and not provided by the architecture.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
bf2139331c xtensa: Add exception/interrupt vectors in asm2 mode
This adds vectors for all interrupt levels defined by core-isa.h.

Modify the entry code a little bit to select correct linker sections
(levels 1, 6 and 7 get special names for... no particularly good
reason) and to constructed the interrupted PS value correctly (no EPS1
register for exceptions since they had to have interrupted level 0
code and thus differ only in the EXCM bit).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
7de010b5e5 xtensa: Interrupt generator script and output for qemu & esp32
This python script reads the core-isa.h interrupt definitions (via
running a template file through the toolchain preprocessor to generate
an input file) and emits a fully populated, optimized C handling code
that binary searches only the declared interrupts at a given level and
correctly detects spurious interrupts (and/or incorrect core-isa.h
definitions).

The generated code, alas, turns out not to be any faster than simply
searching the interrupt mask with CLZ (er, NSAU in xtensese), though
it could be faster in theory if the compiler made different choices,
see comments.  But I like this for the robustness of the fully
populated search trees and the checking of level vs. mask.

This simply commits the script output into the source tree, including
some checking code to force a build error if the toolchain changes the
headers incompatibly.  It would be better long term to have these
headers be generated at build time, but that requires more cmake fu
than I have.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
c761ae9695 xtensa: Add Kconfig for asm2 layer
The asm2 layer will build alongside the traditional assembly, but the
reverse is not true.  Add a CONFIG_XTENSA_ASM2 to force its use at
runtime and disable the older code.

Note that the older assembly had an initialization function that is
properly part of the timer driver.  Move a C equivalent into the timer
driver itself for now to prevent a build breakage.  Long term we need
to clean that driver up in a bunch of other ways.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
6f3036091a xtensa: Implement _xt_ints_on/off for asm2
Legacy xtensa had a rather complicated implementation of en/disabling
interrupts, owing to the "software priority" feature (which plays
games with INTENABLE and INTLEVEL to allow for interrupts to interrupt
each other outside their normal priorities).  But that's not a Zephyr
feature, it's enabled by a XT_USE_SWPRI value that comes from platform
headers and isn't enabled on any of our boards.  Dead code, basically.

Replace with the obvious implementation when asm2 is in use.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
a0dd2de6fd xtensa: Remove _xt_set_exception_handler()
This was a dead API.  Nothing ever used it, it wasn't exposed in any
API headers.  It never appeared in documentation.  It's not
particularly clear why a Zephy app would want to hook
architecture-specific exceptions instead of simply using the portable
error framework anyway. And it's not supported by asm2.  Delete.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
b2c74e017e xtensa/asm2: Add a _new_thread implementation for asm2/switch
Implement _new_thread in terms of the asm2 switch mechanism.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
042d8ecca9 kernel: Add alternative _arch_switch context switch primitive
The existing __swap() mechanism is too high level for some
applications because of its scheduler-awareness.  This introduces a
new _arch_switch() mechanism, which is a simpler primitive that looks
like:

    void _arch_switch(void *handle, void **old_handle_out);

The new thread handle (typically just a stack pointer) is specified
explicitly instead of being picked up from the scheduler by
per-architecture code, and on return the "old" thread handle that got
switched out is returned through the pointer.

The new primitive (currently available only on xtensa) is selected
when CONFIG_USE_SWITCH is "y".  A new C _Swap() implementation based
on this primitive is then added which operates compatibly.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
32a444c54e kernel: Fix nano_internal.h inclusion
_Swap() is defined in nano_internal.h.  Everything calls _Swap().
Pretty much nothing that called _Swap() included nano_internal.h,
expecting it to be picked up automatically through other headers (as
it happened, from the kernel arch-specific include file).  A new
_Swap() is going to need some other symbols in the inline definition,
so I needed to break that cycle.  Now nothing sees _Swap() defined
anymore.  Put nano_internal.h everywhere it's needed.

Our kernel includes remain a big awful yucky mess.  This makes things
more correct but no less ugly.  Needs cleanup.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
a34f884f23 xtensa: New asm layer to support SMP
SMP needs a new context switch primitive (to disentangle _swap() from
the scheduler) and new interrupt entry behavior (to be able to take a
global spinlock on behalf of legacy drivers).  The existing code is
very obtuse, and working with it led me down a long path of "this
would be so much better if..."  So this is a new context and entry
framework, intended to replace the code that exists now, at least on
SMP platforms.

New features:

* The new context switch primitive is xtensa_switch(), which takes a
  "new" context handle as an argument instead of getting it from the
  scheduler, returns an "old" context handle through a pointer
  (e.g. to save it to the old thread context), and restores the lock
  state(PS register) exactly as it is at entry instead of taking it as
  an argument.

* The register spill code understands wrap-around register windows and
  can avoid spilling A4-A15 registers when they are unused by the
  interrupted function, saving as much as 48 bytes of stack space on
  the interrupted stacks.

* The "spill register windows" routine is entirely different, using a
  different mechanism, and is MUCH FASTER (to the tune of almost 200
  cycles).  See notes in comments.

* Even better, interrupt entry can be done via a clever "cross stack
  call" I worked up, meaning that the interrupted thread's registers
  do not need to be spilled at all until they are naturally pushed out
  by the interrupt handler or until we return from the interrupt into
  a different thread.  This is a big efficiency win for tiny
  interrupts (e.g. timers), and a big latency win for all interrupts.

* Interrupt entry is 100% symmetric with respect to medium/high
  interrupts, avoiding the problems seen with hooking high priority
  interrupts with the current code (e.g. ESP-32's watchdog driver).

* Much smaller code size.  No cut and paste assembly.  No use of HAL
  calls.

* Assumes "XEA2" interrupt architecture, the register window extension
  (i.e. no CALL0 ABI), and the "high priority interrupts" extension.
  Does not support the legacy processor variants for which we have no
  targets.  The old code has some stuff in there to support this, but
  it seems bitrotten, untestable, and I'm all but certain it doesn't
  work.

Note that this simply adds the primitives to the existing tree in a
form where they can be unit tested.  It does not replace the existing
interrupt/exception handling or _Swap() implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
8dca7ae587 xtensa: Make high priority interrupts optional
Xtensa has a "high priority" class of interrupt levels which ignore
the EXCM bit and can thus interrupt running exception handlers.  These
can't be used for C handlers in the general case[1] because C code
needs to be able to throw window over/underflow exceptions, which are
not reentrant.

But the high priority interrupts might be useful to a carefully
designed application, or to unit tests of low level architecture code.
So make their generation optional with this kconfig option.

[1] ESP-32 has a high priority interrupt for its watchdog, apparently.
    Which is sort of OK given that it never needs to return to the
    interrupted code.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
88538e77c1 xtensa: Move register window exception handlers into a separate file
No behavior changes, just code motion.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Wayne Ren
bb50a88045 arch: arc: apply the new thread stack layout
The new thread stack layout is as follow:

|---------------------|
|  user stack         |
|---------------------|
| stack guard (opt.)  |
|---------------------|
|  privilege stack    |
-----------------------

For MPUv2
  * user stack is aligned to the power of 2 of user stack size
  * the stack guard is 2048 bytes
  * the default size of privileg stack is 256 bytes.
  For user thread, the following MPU regions are needded
    * one region for user stack, no need of stack guard for user stack
    * one region for stack guard when stack guard is enbaled
    * regions for memory domain.
  For kernel thread, the stack guard region will be at the top, adn
  The user stack and privilege stack will be merged.

MPUv3 is the same as V2's layout, except no need of power of 2
alignment.

* reimplement the user mode enter function. Now it's possible for
kernel thread to drop privileg to user thread.

* add a separate entry for user thread

* bug fixes in the cleanup of regs when go to user mode

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
e445ab6f21 arch: arc: handle exception in privilege task when USERSPACE enabled
when USERSPACE is enabled, exception is handled in the privilege
stack of thread. This make thread context switch is possible in the
exception handler. For some case,e.g. tests, this is useful.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
4433f81b47 arch: arc: MPUv2 enables MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
enable MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT for ARC MPU v2

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
0a71b106d1 arch: arc: save user thread's context into privilege stack
disable the U bit of irq.ctrl, so the user thread's context will
be saved into privilege stack when interrupts/exception come.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
a970b5fd32 arch: arc: scrub regs of kernel context before returning to userspace
scrub all the regs of kernel context before returnning to userspace.
For sys call, ro is not cleared as it's a return value of sys call.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
7ef2506611 arch: arc: enable US bit to check user mode
Enable us bit to check user mode more efficienly.

US is read as zero in user mode. This will allow use mode sleep
instructions, and it enables a form of denial-of-service attack
by putting the processor in sleep mode, but since interrupt
level/mask can't be set from user space that's not worse than
executing a loop without yielding.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
8feca6c2ef arch: arc: modify the kconfig for mpu case
* user space support requires THREAD_INFO
* for MPU version 2, the stack align is at least 2048 bytes
  * the smallest mpu region is 2048 bytes
  * the region size must bt power of 2
  * the start address of region must be aligned to the region size

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
e91733c78b arch: arc: bug fixes and add user space support in secure mode
* bug fixes
* add user space support in secure mode

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
f81dee0b2b arch: arc: add user space support for arc
* add the implementation of syscall
  * based on 'trap_s' intruction, id = 3
* add the privilege stack
  * the privilege stack is allocted with thread stack
  * for the kernel thread, the privilege stack is also a
    part of thread stack, the start of stack can be configured
    as stack guard
  * for the user thread, no stack guard, when the user stack is
    overflow, it will fall into kernel memory area which requires
    kernel privilege, privilege violation will be raised
* modify the linker template and add MPU_ADDR_ALIGN
* add user space corresponding codes in mpu
* the user sp aux reg will be part of thread context
* When user thread is interruptted for the 1st time, the context is
  saved in user stack (U bit of IRQ_CTLR is set to 1). When nest
  interrupt comes, the context is saved in thread's privilege stack
* the arc_mpu_regions.c is moved to board folder, as it's board
  specific
* the above codes have been tested through tests/kernel/mem_protect/
  userspace for MPU version 2

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Anas Nashif
8949233390 kconfig: fix more help spacing issues
Fix Kconfig help sections and add spacing to be consistent across all
Kconfig file. In a previous run we missed a few.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-15 23:20:55 -05:00
Carles Cufi
f24f50b12e arm: cortex_m: Use new ARMV6_M_ARMV8_M_BASELINE in vector relay
The old ARMV6_M Kconfig option has been removed, and so to correctly set
the dependencies for SW_VECTOR_RELAY we need to use the new
ARMV6_M_ARMV8_M_BASELINE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-14 12:49:09 +01:00
Andy Gross
4c47d7f7e2 arch: arm: Enable stack guard before starting main
This patch fixes a hole in the stack guard configuration.  The initial
branch to main is missing the stack guard configuration.

Fixes: Issue #3718

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 13:06:41 -08:00
Andy Gross
465e04cae7 arch: arm: Fixup stack end calculations
This patch fixes calculations for the top of the interrupt and main
stacks.  Due to power of two alignment requirements for certain MPUs,
the guard size must be taken into account due to the guard being
counted against the initial stack size.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
f7ec62eb85 arm: mpu: Enable userspace support for NXP and ARM
This patch set implements the APIs and changed required to support
the user mode thread support.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
1c047c9bef arm: userspace: Add ARM userspace infrastructure
This patch adds support for userspace on ARM architectures.  Arch
specific calls for transitioning threads to user mode, system calls,
and associated handlers.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
9ccdcb9be6 arm: mpu: Add user context API placeholder
This patch adds a configure_mpu_user_context API and implements
the required function placeholders in the NXP and ARM MPU files.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Michael Scott
7a9b688526 x86: fix build warning
During compile of lwm2m_client using qemu_x86, the following build
warning was noticed:
zephyr/arch/x86/core/excstub.S:132:2: warning: "/*" within comment [-Wcomment]
  /*

In commit ff42bdd0a0 ("debug: remove option GDB_INFO"), the comment tag
was omitted.  Fix the comment end tag.

Signed-off-by: Michael Scott <michael@opensourcefoundries.com>
2018-02-12 19:21:06 -05:00
Anas Nashif
11a9625eaf debug: remove DEBUG_INFO option
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Anas Nashif
ff42bdd0a0 debug: remove option GDB_INFO
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Sean Nyekjaer
a09b6f538a arch: atmel_sam0: rename samd SoC series to samd21
Atmel SAMD21 series was classified too broadly as SAMD.
This patch names it correctly to make room,
for other members of SAMD series

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
2018-02-09 08:34:55 -06:00
247782a7b3 sam0: move the UART and SPI configuration into pinmux.
Also pull out the SERCOM pads configuration to defines.  Note that the
SAM0 has a two level configuration - a signal (like TX) is mapped to a
pad, and then a pad is mapped to a function on a pin.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-02-08 12:09:46 -06:00
Ioannis Glaropoulos
0d6fa4db0a arch: arm: define Cortex-M23, Cortex-M33 CPUs
This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Ioannis Glaropoulos
a0a03d7597 arch: arm: common Armv8-M support
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Savinay Dharmappa
98d6a9928c driver: usb_dw: Move base address and irq num of usb to soc.h
base adrress and irq number moved to soc.h

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-02-07 22:55:11 -05:00
Ramakrishna Pallala
3eb62bc905 drivers: i2c: Add i2c master driver for Nios-II i2c core
Add I2C Master driver for Nios-II I2C soft IP core.

This driver relies upon the Altera HAL I2C driver for all the bus level
transactions, interrupt handling and register programming.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-07 19:37:35 -05:00
Alberto Escolar Piedras
3b924ede3e native: coverage exclusions
Just some exclusions to coverage in code which cannot be
reached, or can only be reached in error conditions

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
66c1652fb8 native: native_posix timer + irq fix
Added possibility to reconfigure CONFIG_SYS_CLOCK_TICKS_PER_SEC
for the native_posix board (before it could only be 100)
+
Fixed tickless idle support
+
Minor fixes in irq wrapping

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
a99a14c3b7 native: added posix_get_hw_cycle()
Added function (for all ARCH_POSIX boards) to get the
the current clock cycle of the CPU

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
David B. Kinder
c2bf3af1de doc: fix misspellings in Kconfig files
Missed some misspellings during regular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-07 14:51:46 -05:00
Carles Cufi
4b23b5d589 arch: arm: Do not enable SW_VECTOR_RELAY with M0+ and VTOR
Whenever a Cortex-M0+ supports the VTOR register it makes no sense to
use the software vector relay mechanism. Therefore change the logic so
that SW_VECTOR_RELAY does not get enabled whenever a VTOR register is
present, but enable it if an M0+ has no VTOR.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-07 07:31:32 -06:00
Rajavardhan Gundi
1e6adba9ef drivers/interrupt_controller: Introduce multi-level interrupt support
In a scenario where a platform harbours multiple interrupts to the
extent the core cannot support it, an interrupt controller is added
as an additional level of interrupt. It typically combines several
sources of interrupt into one line that is then routed to the parent
controller.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-02-06 22:39:05 -05:00
Gil Pitney
3f68f2bc97 soc: ti_simplelink: cc32xx: Remove ARMV7_M guard from CMSIS_IRQn_Type
Remove unnecesary #ifdef CONFIG_ARMV7_M guard in soc.h file.

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-02-06 17:34:25 -06:00
Chunlin Han
18560a01a4 arm: Generate privileged stacks
This patch adds the generation and incorporation of privileged stack
regions that are used by ARM user mode threads.  This patch adds the
infrastructure for privileged stacks.  Later patches will utilize the
generated stacks and helper functions.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
e8860fe8be arm: Add app data section alignment constraints
This patch adds application data section alignment constraints
to match the region definition requirements for ARM MPUs.  Most MPUs
require a minimum of 32 bytes of alignment for any regions, but some
require power of two alignment to the size of a region.

This requires that the linker align the application data section to
the size of the section.  This requires a linker pass to determine the
size.  Once this is accomplished the correct value is added to a linker
include file that is utilized in subsequent linker operations.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
65ac049105 kernel: arm: core: Fix thread monitor wrapping
This fixes the wrapping of the thread monitor specific parts of the
new thread code.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Erwan Gouriou
c734c2972f flash: remove obsolete FLASH_DRIVER_NAME
Replace seldom occurrences of FLASH_DRIVER_NAME by equivalent
and commonly used FLASH_DEV_NAME.

Fixes #5919.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-02-06 11:48:53 -06:00
Ilya Tagunov
d2b09497eb arm: core: cortex_m: introduce CPU_CORTEX_M_HAS_VTOR option
Some ARMv6-M Cortex-M0+-based SOCs have VTOR register
and can relocate vector table just as ARMv7-M ones.
Vector table relocation path should be choosed
by VTOR presence, not by arch.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-02-06 08:59:36 -06:00
Yannis Damigos
5d3016aa65 boards: arm: stm32f3_disco: Enable SPI_1, SPI_2 ports
Enable SPI1 and SPI2 ports on stm32f3_disco.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-05 09:21:33 -06:00
Ramakrishna Pallala
c02a2bed61 drivers: flash: Add Nios-II QSPI flash driver
Add Altera Nios-II QSPI Flash controller driver which has
has 1024 blocks or sectors wich each sector size being 64K bytes.
This driver supports flash erase, write, read and lock operations.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-05 06:30:50 -08:00
Alberto Escolar Piedras
fb442b0d9a native: exclude from coverage not coverable code
Some code in the POSIX architecture is only meant to handle
safely errors which should never occur and therefore
are not covered.
=> We exclude them from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
c53924cfe9 native: SOC: exclude unlikely code from coverage
Some code in the POSIX SOC (inf_clock) will only be executed
if the program is terminated by receiving a SIGTERM in a particular
part. Therefore to avoid confusing developers with changing
coverage, let's exclude it from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
d9e1182f3a native: POSIX arch: Exclude unlikely code from coverage
Some code in the POSIX arch core will only be executed
in some very atypical cases depending on the host load.
To avoid confusing developers, let's exclude it from the
coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
a7e55b82dd native: arch: added recommended stack size config
Added a new config variable with the recommended stack
size for threads which are only meant for the posix architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-02 07:48:46 -08:00
Yannis Damigos
6a6a4294c2 boards: arm: olimexino_stm32: Enable SPI1 port
Enable SPI1 port on olimexino_stm32.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Yannis Damigos
af0c9fc349 drivers: spi_ll_stm32: Enable SPI driver for F1 family
Enables SPI driver for STM32F1 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Anas Nashif
9a238cd538 soc: atom: support enumerating PCI devices
This hook is needed to support enumerating PCI devices.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-01 02:19:45 -05:00
Maureen Helm
d107411820 arm: nxp_kinetis: Define FLASH_DRIVER_NAME macro for kl2x and kwx SoCs
Defines the FLASH_DRIVER_NAME macro in soc.h for kinetis kl2x and kwx
SoC series. This macro is used by the storage and dfu subsystems, as
well as the flash_shell sample.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-01-31 16:43:40 -06:00
Ramakrishna Pallala
301acb8e1b kernel: include: rename nano_internal.h to kernel_internal.h
Rename the nano_internal.h to kernel_internal.h and modify the
header file name accordingly wherever it is used.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-01-31 10:07:21 -06:00
Alberto Escolar Piedras
a35364dd1a native: minor consistency rename
rename main_clean_up() to posix_exit() for consistency
with all other global functions of this architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-01-29 23:23:56 -05:00
Adithya Baglody
77755afa19 userspace: ARM: Fixed Kconfig for ARM_USERSPACE
Currently in zephyr the support for the arm userspace has not be
merged. But the Kconfig always sets the userspace flag and causes a
build failure. This is blocking the test cases for userspace.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-01-29 23:11:11 -05:00
Carles Cufi
7361d3d74d config: bootloader: Add support for MCUboot
Add a new Kconfig option, BOOTLOADER_MCUBOOT, that automatically sets
the required options necessary to make the resulting image bootable by
the MCUboot open source bootloader. This includes the text section
offset and the vector relay table for Cortex-M0, and in the future it
might also add the DTS overlay required to link at slot0 offset in
flash.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-29 18:05:18 -05:00
Kumar Gala
b8173d960e drivers: flash: NXP KL2X/KW4xZ: Add device tree support
Add device tree support for the "nxp,kinetis-ftfa" flash controller used
on the NXP KL2X and KW4xZ SoCs.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Kumar Gala
a394693d2f drivers: flash: NXP k6x/kw2xd: Convert to use device tree
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree.  We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Anas Nashif
b8ea7c889d x86: remove HAS_DTS checking
All X86 boards are now DTS enabled.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-29 10:38:32 -06:00
Michał Kruszewski
aee2ff526d ext: nordic: Replace HAL and MDK with the ones from nrfx
The old HAL and MDK have been removed from the source tree.
Since RADIO HAL is not yet present in nrfx, the "nrf_radio.h" file
was temporarily moved to "nrfx/hal" folder. It will be replaced with
the proper file from nrfx in its next update.

Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-01-29 03:02:06 +05:30
Andrzej Głąbek
c84c2eaa82 ext: nordic: Add initial adaptation layer for nrfx
This commit adds a glue layer that adapts nrfx to be usable in Zephyr
as a host environment and files with static configuration of nrfx
drivers for several supported SoCs.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-01-29 03:02:06 +05:30
Daniel Wagenknecht
3f2b376cd6 dts: stm32l4: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 L4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

disco_l475_iot1 boards fixup blocks for devices connected via SPI
and I2C stay in board level dts.fixup file, because they are board
specific.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
080fe4d4cf dts: stm32f3: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F3 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
285c9506d5 dts: stm32f1: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F1 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
d76858f6ae dts: stm32f4: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

96b_carbon boards fixup block for Bluetooth HCI device via SPI
stays in board level dts.fixup file, because it is board specific.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
be430a05cb dts: stm32f0: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F0 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Kumar Gala
2dfee62a5e drivers: flash: atmel sam0: Convert to use device tree
Convert Atmel SAM0 flash driver to use device tree to get the flash
controller name and base address.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-27 21:09:28 -06:00
Kumar Gala
dc98605f4a drivers: flash: stm32: Convert to use device tree
Convert STM32 flash drivers to use device tree to get the flash
controller name and base address.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-26 09:25:57 -06:00
Ding Tao
bbd307edfd arch: arm: vector_table: Support vector table soft relay
For SoCs that don't support vector table relocation in hardware, may not
support bootloader like mcuboot.

We introduce a way to relocate vector table in software by forwarding
the control of incoming IRQs to a new vector table which address is save
at fixed SRAM address.

User can change the data in that fixed SRAM address in order to relocate
vector table in software way.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
bf949b0647 arch: arm: Add SW_VECTOR_RELAY Kconfig flag
Eanble soft relay IRQ handler for Cortex-M0 target if this flag set
true.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
e28db91acf arch: arm: stm32f0: Enable CONFIG_CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
Enable this flag for all stm32f0 series in order to support hardware
vector table relocation feature.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
0be502e68f arch: arm: Add CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP Kconfig flag
Cortex-M0 do not have the Vector Table Base Address Offset Register, so
Cortex-M0 vector table address can not be changed.

But in some Cortex-M0 SoCs like STM32F0 series, they have some mechanism
that can remap the vector table address to the start address of SRAM.

Use this flag to indicates whether current Cortex-M0 SoC support such a
remap or not.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Kumar Gala
b0768ec66a arm: nordic: remove last references to CONFIG_SOC_FLASH_NRF5_DEV_NAME
We use FLASH_DEV_NAME everywhere now so we can remove the use of
CONFIG_SOC_FLASH_NRF5_DEV_NAME.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-25 15:23:00 -06:00
Kumar Gala
44141f6939 arm: nordic: Refactor dts.fixup files to SoC vs board
Refactor common dts.fixup for the SoC into the SOC_SERIES dts.fixup
file.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-25 15:23:00 -06:00
Neil Armstrong
d9c00b4e68 arch: arm: soc: provide support for stm32f072
Support the ST STM32F072xB SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-01-25 15:13:53 -06:00
Carles Cufi
90a45d2eca soc: nrf51: Define flash driver name for nRF51
In order to be able to build MCUboot for nRF51 we require the flash
driver name in the nRF51 soc.h header.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-25 14:41:22 +01:00
Anas Nashif
5124711d87 native: ignore format-truncation warnings (REVERTME)
This is enabled by default in GCC 7, disable for now. Tracked in
issue #5732

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-25 04:45:35 +05:30
Andrzej Puzdrowski
ff7dfc4fb4 dts: bindings: add support for the flash driver name
So far, DT did not support the flash driver name.
Any flash-controller should have the appropriate
flash driver that should be identified by its name.

This path adds generic support for extract the description
from the flash-controller node,
adds implementation of this property for all nrf5x targets.


Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-01-23 12:29:50 -06:00
Shiksha Patel
4a892ae81a lpc: Add nxp_lpc soc family to soc directory
Add soc configuration support for lpc soc family, Kconfigs and soc files
for lpcxxx soc.

Add dtsi file for lpc54xxx.

Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-01-23 09:18:32 -06:00
Wayne Ren
5ca2c05316 arch: arc: Add _arch_mem_domain_configure
add the _arch_mem_domain_configure api to match the PR #5065 to avoid
compile failure in the future

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-18 11:50:59 -08:00
Wayne Ren
9a40bf6b7e arch: arc: Add the intial support of memory domain
Refering the ARM's implementation, the initial support of memory
domain in ARC is added:
* changes in MPU drivers
* changes in Kconfig
* codes to configure memory domain during thread swap
* changes in linker script template
* memory domain related macro definitions

the commited codes are simply tested through
samples/mpu/mem_domain_apis_test.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-18 11:50:59 -08:00
73d045e281 spi: add a SPI driver for the SAM0 series.
Impleentation is master only and uses polling to read and write.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-01-13 07:39:05 -05:00
David B. Kinder
fd04de2d10 doc: fix misspellings in Kconfig files
periodic scan for typos missed during normal reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-01-12 20:58:56 -05:00
Kumar Gala
b92a40a798 drivers: entropy: stm32: Remove STM32F411XE from building
It appears the STM32F411XE doesn't support RNG so remove enabling it
from the SoC defconfig and flag an error if attempting to build the
driver on that SoC.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-12 19:42:54 -05:00
Andrew Boie
df48e11d98 build: warn user about Meltdown vulnerability
A fix for this issue is in progress, meanwhile warn the user that
they may be susceptible to this problem if they enable user mode on
an x86-based target that is not known to be immune.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-01-12 15:12:32 -08:00
Sebastian Bøe
4b61bd1b7a kconfig: Prune kconfig files that don't match the ARCH or BOARD
When Kconfiglib was introduced it caused a significant performance
issue. This patch uses pruning to mitigate the performance issue.

The pruning exploits the fact that before the Kconfig database is
parsed we already know what ARCH and BOARD has been selected. So in
theory we could prune away all Kconfig sources that are not related to
the current ARCH or BOARD. In practice, it is only the Kconfig sources
in zephyr/arch/$ARCH and zephyr/board/$ARCH/ that are easy to prune.

Still, that is quite a few Kconfig sources. For qemu_x86 this patch
reduced the number of parsed Kconfig source files from 632 to
272. This pruning resulted in a incremental reconfiguration (time
cmake ..) speedup of 21% (0.56s to 0.46) and a clean build speedup of
4% (Using board qemu_x86 and sample hello_world).

Furthermore, it should be easier to maintain ARCH's and BOARD's
out-of-tree since the user now has a mechanism to redirect where
Kconfig sources are found. But this has not been explored.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-01-12 07:29:05 -05:00
Erwan Gouriou
164fb32cf6 drivers: entropy: stm32: limit driver to SoC supporting it
In STM32 family, RNG IP is available only on F4 and L4 series.
Besides STM32F401 does not support is neither.
Get entropy driver available on STM32 devices supporting it and
generate a compilation issue on STM32 devices that do not own
the RNG IP.

Solves #5448

Signed-Off-By: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-01-11 19:00:19 -05:00
Neil Armstrong
9c3f7e11fb arch: arm: soc: stm32f0: include LL spi header
Include the STM32Cube LL SPI Header for STM32F0

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-01-11 19:00:19 -05:00
Jonas Pfaff
1d8e7a58c0 arm: atmel: soc: Soc init can be executed twice
Signed-off-by: Jonas Pfaff <jonas.pfaff@gmail.com>
2018-01-11 19:00:19 -05:00
Kumar Gala
cd7ca95378 arm: nxp_mpu: Fix build issue when asserts enabled
When asserts are enabled we run into an issue with newlib and types of
printf style formatters not matching.  The easy fix to this is to cast
the uint32_t to u32_t to make things consistent with or without newlib
enabled.

This fixes #5645

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-11 15:20:03 -06:00
Yannis Damigos
4d2dbab036 boards: stm32f1: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
c868ac0238 boards: stm32f0: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
2cb692e7de boards: stm32f3: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
96740a0570 boards: stm32l4: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
d60dc69ee7 boards: stm32f4: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
a6f8283ecd arch: st_stm32: Add common series configuration file
Add common series configuration file

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Carles Cufi
7d764b35f3 cmake: Use path-corrected version of ZEPHYR_BASE
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.

Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-11 14:59:03 -05:00
Ilya Tagunov
935d0ce89b soc: arm: stm32: fix startup SystemCoreClock values
Current STM32 SoC initialization code sets really weird startup values
to SystemCoreClock. It should be consistent with Reference Manuals after
this change.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-01-08 08:38:17 -07:00
Anas Nashif
9f6c7838e5 arch: fix typo defafult -> default
Simple typo fix.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-08 08:08:45 -05:00
Anas Nashif
7ae749828f kconfig: fix help text indentation
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-08 08:08:45 -05:00
b69c452e6f arch: add support for the SAMD21G18A used in the Arduino Zero.
Signed-off-by: Michael Hope <mlhx@google.com>
2018-01-04 13:18:25 -05:00
Jan Van Winkel
30b65d8986 arm: stm32l4: include RNG ll header
Include low level random generator header in case stm32 random number
generator should be used by entropy driver

Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
2018-01-04 09:18:21 -05:00
Anas Nashif
61fe98c573 kconfig: rename CONFIG_BSP_SHARED_GDT_RAM_*
We stopped using BSP_ in configs long time ago, this one got stuck for
some reason.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-04 09:17:03 -05:00
Sebastian Bøe
74174809da gen_isr_tables: Minor refactoring
Minor refactor to gen_isr_tables.py; "if not" is difficult to read.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-01-04 08:55:26 -05:00
Alberto Escolar Piedras
e04764dbc7 native: Handle gracefully SIGTERM and SIGINT
When SIGTERM or SIGINT are received handle them
by gracefully exiting the program.

Fixes #5477

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-01-02 15:26:34 -05:00
Anas Nashif
72fe097bc0 testing: add option to generate coverage reports
With the native port we are able to generate coverage reports, add the
needed options to the compliler and add a kconfig option to enable this
on the supported architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Alberto Escolar Piedras
76f7644118 arch: native: Run Zephyr natively in a POSIX OS
A new arch (posix) which relies on pthreads to emulate the context
switching
A new soc for it (inf_clock) which emulates a CPU running at an
infinely high clock (so when the CPU is awaken it runs till completion
in 0 time)
A new board, which provides a trivial system tick timer and
irq generation.

Origin: Original

Fixes #1891

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Anas Nashif
5146dbbc58 arch: architecture defines kernel entry
Make defining the kernel entry architecture specific and move it to the
architecture domain.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Anas Nashif
f4ddb62bfa kconfig: move ARCH_HAS_THREAD_ABORT to arch level
Was ARM specific and could not be used by other architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2017-12-27 14:16:08 -05:00
Ramakrishna Pallala
12d614d0b8 drivers: gpio: add support for Altera Nios-II PIO controller
The PIO cores on Altera Nios-II processors can be used
for GPIOs and each PIO core can be configured as Input only,
Output only or as Bidirectional port from the Qsys tool.

The present Nios-II softcpu image on the Zephyr only has the
support for Output only port and the PIOs[0:3] are wired to
LED[0:3] on the Altera MAX10 board.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-21 12:02:24 -08:00
Adithya Baglody
9cde20aefa kernel: mem_domain: Add to current thread should configure immediately.
when a current thread is added to a memory domain the pages/sections
must be configured immediately.
A problem occurs when we add a thread to current and then drop
down to usermode. In such a case memory domain will become active
the next time a swap occurs.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-12-21 11:52:27 -08:00
Adithya Baglody
13ac4d4264 kernel: mem_domain: Add an arch interface to configure memory domain
Add an architecure specfic code for the memory domain
configuration. This is needed to support a memory domain API
k_mem_domain_add_thread.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-12-21 11:52:27 -08:00
Ramakrishna Pallala
27aced168d arch: nios2: enable System ID soft IP driver
The system ID core is a simple read-only device that
provides Qsys systems with a unique identifer.

Nios-II processor systems use the system ID core to
verify that an executable program was compiled targeting
the actual hardware image configured in the target FPGA.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-15 18:12:00 -05:00
Anas Nashif
429c2a4d9d kconfig: fix help syntax and add spaces
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-13 17:43:28 -06:00
Wayne Ren
5f349a4d4d arch: arc: fix the comments and coding style
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
cdfb59a276 arch: arc: add the support of MPU version 3
MPU version 3 is included in em7d of em_starterkit 2.3.

The differences of MPU version 3 and version 2 are:

* different aux reg interface
* The address alignment requirement is 32 bytes
* supports secure mode
* supports SID (option)
* does not support memory region overlap

This commit adds the support MPU version 3 and also make some changes to
MPU version 2 to have an unified interface.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
0892cd7f46 board: arc: em_starterkit: Add em7d support of em_starterkit 2.3
* em7d of em_starterkit 2.3 supports secure mode. add the support
  in kconfig and build system.

* change the default configuration of em_starterkit 2.3 to em7d

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
528c960ae7 arch: arc: Add the support of secure mode for em
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:

* different irq stack frame. so need to change the definition of
  _irq_stack_frame, assembly code.

* new aux regs, e.g, secure status(SEC_STAT), secure vector base
  (VECT_BASE_S)

* interrupts and exceptions, secure mode has its own vector base;
  interrupt can be configured as secure or normal through the
  interrupt priority aux reg.

* secure timers. Two secure timers (secure timer 0 and timer 1) are
  added.Here, for simplicity and backwards compatibility original
  internal timers (timer 0 and timer1) are used as sys clock of zephyr

* on reset, the processor is in secure mode and secure vector base is
  used.

Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
52e4c197f3 arch: arc: Add FIRQ option
Add FIRQ option and change the _isr_wrapper. Currently, firq is
enabled by default, but in some arc configuration, firq can be
disabled.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Andrzej Puzdrowski
d095963e73 drivers: flash: Assert implementation of Flash Page Layout
Some drivers doesn't implement flash API page layout extension
which is causing the application crash once the API was calling.
This patch introduce system termination for this in those drivers
which doesn't implement extension. This will help to discover this
problem early.

It is not done by preprocessor check because it is possible to have
enabled a driver which support and a driver which doesn't support
this API simultaneously.

Now FLASH_PAGE_LAYOUT configuration option is accessible only in case
that at last one driver which implements mentioned API is enabled.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2017-12-12 14:23:50 -06:00
Neil Armstrong
7e2fd68b1f arm: stm32f0: include I2C ll header
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Sudarsana Nagineni
aca079c9fc boards: olimex stm32-e407, stm32f407g_disc1: Enable USB OTG Support
Enable USB OTG support for olimex stm32-e407 and stm32f407g_disc1
boards by adding USB OTG to the pinmux table. Also, fix out of
range endpoint addresses in CDC ACM case for STM32F4 based boards.

Signed-off-by: Sudarsana Nagineni <sudarsana.nagineni@intel.com>
2017-12-12 12:36:08 -06:00
Neil Armstrong
22b4d19a6d ARM: stm32f030x8: fix FLASH_PAGE_SIZE
Fix to the correct flash page size for the stm32f030x8 SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Neil Armstrong
071cff7fb5 ARM: stm32f0: switch flash registers to volatile
Like other STM SoCs (L4 and F0), switch the flash registers struct
to volatile.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Ramakrishna Pallala
47595b1c10 boards: nios2: fix nios2 flashing issue
'make flash' is failing for altera_max10 board due to the
missing NIOS2_CPU_SOF environment variable. Though it is set
in arch/nios2/soc/nios2f-zephyr/CMakeLists.txt but it is not
taking effect when flashing script is run. The reason could be
following which is mentioned in https://itk.org/Wiki/CMake_FAQ

"environment variables SET in the CMakeLists.txt only
take effect for cmake itself (configure-time), so you cannot use
this method to set an environment variable that a custom command
might need (build-time)."

Now, NIOS2_CPU_SOF is set from boards/nios2/altera_max10/board.cmake
file which is more logical because all the FLASH related environment
variables are being set from board.cmake

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-12 11:40:29 -05:00
Ramakrishna Pallala
151f431efa arch: nios2: update nios2 softcpu image
Update nios2 softcpu image which supports additional
soft IP's like I2C, SPI, SGDMA, QSPI, SysID, etc...

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-12 08:25:58 -05:00
Neil Armstrong
494e1734e0 ARM: stm32f0: fix syscfg mapping to fix EXTI config
The exticrX registers were shifted by a word, so configuring
an EXTI line on a port different of PA misconfigured the EXTI line
source and could flood with unwanted events.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-07 08:08:41 -06:00
Anas Nashif
abbaac9189 cleanup: remove nanokernel/nano leftovers
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-05 09:44:23 -06:00
Piotr Mienkowski
dafdfadfbe drivers: Add Atmel SAM I2S (SSC) driver
Added Inter-IC Sound driver (based on SSC module) for Atmel
SAM MCU family.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-2509
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-11-30 10:30:33 -05:00
Piotr Mienkowski
dbcc7429e6 drivers: Add Atmel SAM DMA (XDMAC) driver
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-11-30 10:30:33 -05:00
Savinay Dharmappa
b8745dab61 dts: x86: Add device tree support for QUARK_X1000 soc based devices
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-27 22:18:20 -05:00
Anas Nashif
9c1da0dfa6 kconfig: clean CPU features and define only once
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-27 22:15:30 -05:00
Anas Nashif
a372eaedcc kconfig: move IRQ_OFFLOAD to a more generic place
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-27 22:15:30 -05:00
Adithya Baglody
808ad6101e x86: swap: save the scratch pad registers.
Save the required scratch pad register (in this case only edx)
before calling the C function.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-27 11:50:50 -05:00
Savinay Dharmappa
d77e6581e9 dts: x86: Add device tree support for atom based devices
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-24 10:10:47 -05:00
Anas Nashif
1f1143ac87 build: use kconfig to select generated artifacts
Not all boards require the various binary formats zephyr generates. So
be selective based on the arch, SoC or board and only geenrate the
binaries actually needed.

Fixes #5009

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-23 07:29:13 -05:00
Chunlin Han
d051740ee0 arm: implement API to validate user buffer
Implement API to validate user buffer. This API will iterate
all MPU regions to check if the given buffer is user accessible
or not. For #3832.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-11-17 19:01:11 -05:00
Maureen Helm
457699cd3c arm: Enable the ARM MPU on the NXP i.MX RT SoC and board
Unlike other NXP SoCs currently in Zephyr, the mimxrt1052 has the ARM
MPU rather than the NXP MPU. Start out by enabling it with a simple set
of memory regions for "flash" (ITCM), "ram" (DTCM), and the peripheral
buses. More regions will need to be added when we implement support for
external memories.

Tested with:
- samples/mpu/mpu_stack_guard_test
- tests/kernel/mem_protect/protection

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-11-15 09:09:58 -06:00
Maureen Helm
41d5808321 arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and
series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core,
512 KB TCM, and many peripherals including 2D graphics, an LCD display
controller, camera interface, SPDIF and I2S. Unlike other SoCs in
Zephyr, the mimxrt1052 has no internal flash.

This initial port to mimxrt1052 configures the system clock to operate
at 528 MHz, and enables the serial/uart and gpio interfaces to support
the hello_world and blinky samples. Support for additional Zephyr driver
interfaces will come later.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-11-15 09:09:58 -06:00
Savinay Dharmappa
7c8a23d643 dts: arc: Add dts support for arc
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-15 07:21:10 -06:00
Adithya Baglody
4a20aad15a dts: x86: RAM start address needs to be page aligned for arduino 101.
When CONFIG_X86_MMU is enabled for arduino 101 the start address
should be aligned to 4kB. If not aligned the page tables would not
be created and the build fails.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-13 10:21:58 -08:00
Anas Nashif
6d4d1ea912 arch: arm: fix EM7D makefile
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-13 10:55:26 -05:00
Sebastian Bøe
0829ddfe9a kbuild: Removed KBuild
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Sebastian Bøe
12f8f76165 Introduce cmake-based rewrite of KBuild
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.

Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.

This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.

For users that just want to continue their work with minimal
disruption the following should suffice:

Install CMake 3.8.2+

Port any out-of-tree Makefiles to CMake.

Learn the absolute minimum about the new command line interface:

$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..

$ cd build
$ make

PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html

Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
David B. Kinder
7e3ed1465f doc: fix Kconfig misspellings
Kconfig files are processed to create configuration
option documentation.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-11-08 13:50:35 -05:00
Adithya Baglody
538fa7b37c x86: MMU: Configure page tables entries for memory domain in swap.
During swap the required page tables are configured. The outgoing
thread's memory domain pages are reset and the incoming thread's
memory domain is loaded. The pages are configured if userspace
is enabled and if memory domain has been initialized before
calling swap.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Adithya Baglody
f7b0731ce4 x86: MMU: Memory domain implementation for x86
Added support for memory domain implementation.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Adithya Baglody
83bedcc912 ARM: MPU: Arch specific memory domain APIs
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Andrew Boie
2a8684f60c x86: de-couple user mode and HW stack protection
This is intended for memory-constrained systems and will save
4K per thread, since we will no longer reserve room for or
activate a kernel stack guard page.

If CONFIG_USERSPACE is enabled, stack overflows will still be
caught in some situations:

1) User mode threads overflowing stack, since it crashes into the
kernel stack page
2) Supervisor mode threads overflowing stack, since the kernel
stack page is marked non-present for non-user threads

Stack overflows will not be caught:

1) When handling a system call
2) When the interrupt stack overflows

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-11-07 09:31:49 -08:00
Gustavo Lima Chaves
9bb07ff69a jailhouse: add support for x2APIC mode for all LOAPIC accesses
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.

By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.

When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.

Here are some outputs of the the command line

  $ sudo ./tools/jailhouse cell stats tiny-demo

on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:

Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                          7         0
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_msr                            1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xapic                          0         0
vmexits_xsetbv                         0         0

Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                       4087        40
vmexits_xapic                       4080        40
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_msr                            1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xsetbv                         0         0

Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                       4087        40
vmexits_msr                         4080        40
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xapic                          0         0
vmexits_xsetbv                         0         0

See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Gustavo Lima Chaves
97a8716a4f x86: Jailhouse port, tested for UART (# 0, polling) and LOAPIC timer
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:

   - hello_world
   - philosophers
   - synchronization

The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.

Testing it is just a matter of:
  $ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
  $ sudo insmod <path to jailhouse.ko>
  $ sudo jailhouse enable <path to configs/qemu-x86.cell>
  $ sudo jailhouse cell create <path to configs/tiny-demo.cell>
  $ sudo mount -t 9p -o trans/virtio host /mnt
  $ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
  $ sudo jailhouse cell start tiny-demo
  $ sudo jailhouse cell destroy tiny-demo
  $ sudo jailhouse disable
  $ sudo rmmod jailhouse

For the hello_world demo case, one should then get QEMU's serial port
output similar to:

"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""

Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.

As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).

Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.

You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.

Other config differences from pristine QEMU defaults worth of mention
are:

   - there is no HPET when running as Jailhouse guest. We use the LOAPIC
     timer, instead
   - there is no PIC_DISABLE, because there is no 8259A PIC when running
     as a Jailhouse guest
   - XIP makes no sense also when running as Jailhouse guest, and both
     PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
     config is set to

This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.

[1] https://github.com/siemens/jailhouse

Reference to Jailhouse's booting preamble code:

Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Gustavo Lima Chaves
ca3d51b5fa build: Only have MMU_BOOT_REGION decl. for HPET if the latter is on
This would impact builds with no CONFIG_HPET_TIMER=y set.

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Youvedeep Singh
833025dd94 timer: xtensa_sys_timer: Tickless Kernel Implementation for Xtensa
Implement Tickless Kernel support for Xtensa Architecture.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-11-07 08:17:40 -05:00
Bobby Noelte
3849b36f09 arch: arm: soc: provide support for stm32f091
Support the ST STM32F091xC SoC.

Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
2017-11-06 11:39:16 -06:00
Youvedeep Singh
fc78ddf7d3 ARM: nrf52: Power Management for nrf52 series SOC
Add support for nrf52 series SOC. This patch Adds :-
1. Architecture specific Power Management APIs.
2. APIs for invoking various Power Management tasks into nrf52.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-11-06 09:29:10 -05:00
Kumar Gala
75833d4f52 arm: nxp_kinetis: cleanup soc.h - remove unused defines
Remove defines for IRQs we don't use.  We should be getting this from DT
so this gives us a list of what we need to cleanup.  Remove various
memory address offset defines to the ones we actually use.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-11-03 13:52:57 -05:00
Jan Kiszka
283a0cdafb x86: MMU: Rename gen_mmu script
It's x86-only.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2017-11-03 09:29:39 -07:00
Leandro Pereira
b007b64d30 kernel: Add option to ensure writable pages are not executable
This adds CONFIG_EXECUTE_XOR_WRITE, which is enabled by default on
systems that support controlling whether a page can contain executable
code.  This is also known as W^X[1].

Trying to add a memory domain with a page that is both executable and
writable, either for supervisor mode threads, or for user mode threads,
will result in a kernel panic.

There are few cases where a writable page should also be executable
(JIT compilers, which are most likely out of scope for Zephyr), so an
option is provided to disable the check.

Since the memory domain APIs are executed in supervisor mode, a
determined person could bypass these checks with ease.  This is seen
more as a way to avoid people shooting themselves in the foot.

[1] https://en.wikipedia.org/wiki/W%5EX

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-02 13:40:50 -07:00
Adithya Baglody
edd072e730 tests: benchmarking: cleanup of the benchmarking code.
The kernel will no longer reference the code written in the
test folder.

GH-1236

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-02 09:01:06 -04:00
Leandro Pereira
da9b0ddf5b drivers: Rename random to entropy
This should clear up some of the confusion with random number
generators and drivers that obtain entropy from the hardware.  Also,
many hardware number generators have limited bandwidth, so it's natural
for their output to be only used for seeding a random number generator.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-01 08:26:29 -04:00
Leandro Pereira
adce1d1888 subsys: Add random subsystem
Some "random" drivers are not drivers at all: they just implement the
function `sys_rand32_get()`.  Move those to a random subsystem in
preparation for a reorganization.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-01 08:26:29 -04:00
Carles Cufi
e08a5b0200 arch: arm: kinetis: Remove duplicate CLOCK_CONTROL config option
The CLOCK_CONTROL config option is already defined in
drivers/clock_control, so there's no need to redefine it in arch/.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2017-11-01 11:48:07 +01:00
Anas Nashif
035814efc6 boards: move pinmux driver to board/soc dir
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-31 12:32:34 -04:00
Anas Nashif
9b93334832 soc: ti_simplelink: rename header directory for registers
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-31 12:32:34 -04:00
Anas Nashif
780324b8ed cleanup: rename fiber/task -> thread
We still have many places talking about tasks and threads, replace those
with thread terminology.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-30 18:41:15 -04:00
Andrei Emeltchenko
b1372a857d quark_se: Enable GPIO needed for USB DW driver
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2017-10-30 08:30:48 -04:00
Andrew Boie
3f508e911e x86: fix CONFIG_DEBUG_INFO build error
This doesn't have any register operands and needs a size suffix.
Fixes: #4480

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-24 12:50:13 -07:00
Adithya Baglody
76edf8a681 x86: MMU: Enable boot time PAE page tables.
In PAE boot tables the __mmu_tables_start points to page directory
pointer (PDPT). Enable the PAE by updating the CR4.PAE and
IA32_EFER.NXE bits.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
725de70d86 x86: MMU: Create PAE page structures and unions.
Created structures and unions needed to enable the software to
access these tables.
Also updated the helper macros to ease the usage of the MMU page
tables.

JIRA: ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
d1703691c8 x86: MMU: Generation of PAE tables
If CONFIG_X86_PAE_MODE is enabled for the build, then gen_mmu.py
would generate the boot time page tables in PAE format.
This supports 3 level paging i.e Page Directory Pointer(PDPT), Page
Directory(PD) and Page Table(PT). Each Page Table Entry(PTE) maps to
a 4KB region. Each Page Directory Entry(PDE) maps a 2MB region.
Each Page Directory Pointer Entry(PDPTE) maps to a 1GB region.

JIRA: ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
efe795270d x86: MMU: Kconfig option to enable the PAE tables.
Page Address Extension(PAE) page tables would be used
if this option is enabled.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Bobby Noelte
2f7688bfd3 arch: arm: core: fix vector table relocate write to flash
Some SOCs (e.g. STM32F0) can map the flash to address 0 and
the flash base address at the same time. Prevent writing to
duplicate flash address which stops the SOC.

Allow Cortex M SOCs to create their own vector table relocation
function.

Provide a relocation function for STM32F0x SOCs.

Fixes #3923

Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-10-23 12:31:47 +02:00
Maciej Debski
db8fd88fab arch: arm: soc: provide support for stm32f0.
Fixes #3923

Signed-off-by: Maciej Debski <maciej.debski@rndity.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-10-23 12:31:47 +02:00
Piotr Mienkowski
26ba99e972 drivers: Add Atmel SAM family I2C (TWI) driver
Added I2C bus (TWI) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.

Tested on Arduino Due board.

Origin: Original

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-10-23 10:18:08 +02:00
Adam Podogrocki
61467e019e iwdg: the sample of the use of STM32 Independent Watchdog
JIRA: ZEP-2347

Change-Id: I808e9f110681735cae45d14c5802636012f018cc
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-10-23 09:51:16 +02:00
Adam Podogrocki
6d4da19602 iwdg: make independent watchdog driver compliant with STM32Cube LL API
Appropriate inclusion done for F1/F3/F4/L4 families in SoC tree.

JIRA: ZEP-2347

Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-10-23 09:51:16 +02:00
Kumar Gala
46555f17e9 i2c: stm32f3: Cleanup how we enable the specific I2C driver
Match change we made to how I2C is enabled for other stm32 platforms:

Right now we allow for the I2C subsystem to be built without any drivers
enabled that utilize it.  When we added support for the new STM32 I2C
driver we forced the I2C driver to be enabled if the I2C subsystem was
enabled.  While this makes a reasonable amount of sense, it breaks
current assumptions for various testcases that we need to cleanup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-10-22 22:05:37 -05:00
Andrew Boie
48af600a7a Revert "ARM: MPU: Arch specific memory domain APIs"
This reverts commit 7add3cdd82.
2017-10-20 15:02:59 -04:00
Andrew Boie
d7631ec7e4 Revert "x86: MMU: Memory domain implementation for x86"
This reverts commit d0f6ce2d98.
2017-10-20 15:02:59 -04:00
Andrew Boie
de777adf7b Revert "x86: MMU: Configure page tables entries for memory domain in swap."
This reverts commit a8b9353421.
2017-10-20 15:02:59 -04:00
Adithya Baglody
a8b9353421 x86: MMU: Configure page tables entries for memory domain in swap.
During swap the required page tables are configured. The outgoing
thread's memory domain pages are reset and the incoming thread's
memory domain is loaded. The pages are configured if userspace
is enabled and if memory domain has been initialized before
calling swap.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Adithya Baglody
d0f6ce2d98 x86: MMU: Memory domain implementation for x86
Added support for memory domain implementation.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Adithya Baglody
7add3cdd82 ARM: MPU: Arch specific memory domain APIs
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Erwan Gouriou
da210ba0ba driver: serial: Move STM32 UART driver to LL API
STM32 UART driver was using a mix of LL/HAL APIs.  This commit removes
calls to HAL API and replaces them with LL APIs.  No functional change
have been seen during non regression testing.

But we could note a direct gain of 1Kb of ROM

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-10-20 12:28:11 -05:00
Yannis Damigos
a172f72d84 boards: stm32f3_disco: Add I2C support
Add I2C support to STM32F3DISCOVERY board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-10-20 12:28:11 -05:00
Maureen Helm
6312b0e6a1 arm: Enable the mcux sim clock control driver on Kinetis SoCs
Because the mcux shim drivers will soon depend on a clock control
interface, enable the mcux sim clock control driver by default on all
Kinetis SoCs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-10-20 12:28:11 -05:00
Manivannan Sadhasivam
05e1d8c46a arch: arm: soc: ti_simplelink: Add MSP432P401R SoC
This patch adds SoC support for TI SimpleLink family MSP432P401R.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2017-10-19 12:16:11 -05:00
David B. Kinder
4600c37ff1 doc: Fix misspellings in header/doxygen comments
Occasional scan for misspellings missed during PR reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-10-17 19:40:29 -04:00
Andrew Boie
c5c104f91e kernel: fix k_thread_stack_t definition
Currently this is defined as a k_thread_stack_t pointer.
However this isn't correct, stacks are defined as arrays. Extern
references to k_thread_stack_t doesn't work properly as the compiler
treats it as a pointer to the stack array and not the array itself.

Declaring as an unsized array of k_thread_stack_t doesn't work
well either. The least amount of confusion is to leave out the
pointer/array status completely, use pointers for function prototypes,
and define K_THREAD_STACK_EXTERN() to properly create an extern
reference.

The definitions for all functions and struct that use
k_thread_stack_t need to be updated, but code that uses them should
be unchanged.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-17 08:24:29 -07:00
Andrew Boie
094f2cb77b x86: fix crash in _x86_mmu_get_flags
Looking up the PTE flags was page faulting if the address wasn't
marked as present in the page directory, since there is no page table
for that directory entry.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-17 08:16:14 -07:00
Pushpal Sidhu
d5cf7e0912 arch: stm32f4: Add CONFIG_GPIO_STM32_PORTD=y
Default enable PD for all stm32f4 series

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2017-10-17 08:56:15 -05:00
Loic Poulain
8a11f91252 usb: Add support for STM32 family USB driver
This is a USB controller driver for STM32F4xx devices using
the STM32 Cube HAL_PCD framework. This has been tested with
the cdc_acm driver on a 96b_carbon board (STM32F401RE).

This is a refactoring of:
usb: usb_dc_stm: Add support for STM32Cube HAL_PCD USB driver
Signed-off-by: Christer Weinigel <christer@weinigel.se>
[daniel.thompson@linaro.org: Removed STM32F40(157) defconfig changes
together with STM32F4Discovery pinmux and defconfig changes, updated
clock settings and pad configuration to match latest mainline]
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[giannis.damigos@gmail.com: Change uint*_t types to u*_t types,
change SYS_LOG_USB_DC_STM_LEVEL to SYS_LOG_USB_DRIVER_LEVEL and
update pinmux to match latest arm branch]
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2017-10-17 09:14:47 -04:00
Yannis Damigos
1f0c6118d2 arch: stm32f4: Select USB_DC_STM32 driver if USB is enabled
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-10-17 09:14:47 -04:00
Andrew Boie
73a5fe77f8 x86: fix stack overflow in double fault handler
At very low optimization levels, the call to
K_THREAD_STACK_BUFFER doesn't get inlined, overflowing the
tiny stack.

Replace with _ARCH_THREAD_STACK_BUFFER() which on x86 is
just a macro.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-16 10:53:48 -07:00
Andrew Boie
da4024b1f7 Kconfig: CONFIG_USERSPACE is experimental
Indicate to users that this feature isn't fully baked yet.
This will be reverted for 1.11 release.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-13 13:40:21 -07:00
Andrew Boie
2b6abf6f89 kernel: USERSPACE implies HW_STACK_PROTECTION
Userspace is built on top of hardware stack protection and assumes
it is there. We can't enable this unless ARCH_HAS_USERSPACE is defined
anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-11 20:27:10 -04:00
Jonas Pfaff
b62a353551 drivers: adc: Add SAM ADC driver
Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-2507

Signed-off-by: Jonas Pfaff <jonas.pfaff@gmail.com>
2017-10-10 11:56:47 -05:00
Christian Taedcke
3959282359 arm: exx32: Add Silabs EFM32WG soc files
The Silicon Labs EFM32 Wonder Gecko MCU includes:

        * Cortex-M4F core at 48MHz
        * up to 256KB of flash and 32KB of RAM
        * USB with host and OTG support
        * multiple low power peripherals

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-10-10 11:56:47 -05:00
Johann Fischer
af1a8fc9f1 arch: nxp_kinetis: initial import KW2XD SiP
Jira: ZEP-1471

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-10-10 11:56:47 -05:00
Leandro Pereira
5f22dab17a esp32: Prefix ROM routines with esp32_rom_
Also provide their prototypes in `soc.h`.  This should help
readability, since some ROM functions, with their names as provided by
Espressif, have sometimes the same prefix as Zephyr APIs.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-10-09 20:53:22 -04:00
Andrew Boie
468190a795 kernel: convert most thread APIs to system calls
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-07 10:45:15 -07:00
Marti Bolivar
313b20d648 dfu: replace FLASH_ALIGN with FLASH_WRITE_BLOCK_SIZE
Use the define generated by the DTS instead of using the FLASH_ALIGN
alias. The latter is an internal mcuboot name. We shouldn't need it in
Zephyr itself.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
c38efa668c arm: soc: stm32l4: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
92e29680c1 arm: soc: stm32f4: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
2e6744f215 arm: soc: nxp: k6x: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Thiago Silveira
e11b9fb4e3 arm: soc: nRF52: Add workaround for incorrect RESETREAS bits, errata 136
This workaround fixes the issue that, after pin reset, RESETREAS bits
other than RESETPIN might also be set.

The workaround was added to both nRF52832 and nRF52840 SoCs.

Signed-off-by: Thiago Silveira <thiago@exati.com.br>
2017-10-06 22:11:21 -04:00
Paul Sokolovsky
808b315cf6 arm: nxp: kw41z: Select IEEE802154_KW41Z driver for networking
802.15.4 is the networking hardware available in KW41Z SoC (and
supported by Zephyr). So, if networking in enabled, automatically
select the corresponding driver. This is similar to how frdm_k64f
automatically selects Ethernet driver, 96b_carbon selects BLE/IPSP
drivers, etc. (But we apply it on SoC level to reuse across the
boards.)

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2017-10-06 14:39:17 -05:00
Savinay Dharmappa
58d54c0f2d dts: x86: qemu_x86: Add device support for uart ns16550
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-10-06 08:35:42 -04:00
Savinay Dharmappa
ddf6a69577 dts: x86: Add device tree support for qemu_x86
patch add device tree support for ia32 soc and qemu_x86
board port

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-10-06 08:35:42 -04:00
Andrew Boie
3e3a237930 x86: fix stack zeroing when dropping to user mode
For 'rep stosl' ECX isn't a size value, it's how many times to repeat
the 4-byte string copy operation.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-05 18:49:09 -04:00
David B. Kinder
f00f58517b doc: replace UTF-8 chars
Some our Zephyr tools don't like seeing UTF-8 characters, as reported in
issue #4131) so a quick scan and replace for UTF-8 characters in .rst,
.h, and Kconfig files using "file --mime-encoding" (excluding the /ext
folders) finds these files to tweak.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-10-03 20:03:57 -04:00
Anas Nashif
ae2e91155e arch: riscv32: define soc family in correct Kconfig
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-03 08:43:50 -04:00
Anas Nashif
be9a0b35ee arm: atmel: define soc family in correct Kconfig
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-03 08:43:50 -04:00
Chunlin Han
e9c9702818 kernel: add memory domain APIs
Add the following application-facing memory domain APIs:

k_mem_domain_init() - to initialize a memory domain
k_mem_domain_destroy() - to destroy a memory domain
k_mem_domain_add_partition() - to add a partition into a domain
k_mem_domain_remove_partition() - to remove a partition from a domain
k_mem_domain_add_thread() - to add a thread into a domain
k_mem_domain_remove_thread() - to remove a thread from a domain

A memory domain would contain some number of memory partitions.
A memory partition is a memory region (might be RAM, peripheral
registers, flash...) with specific attributes (access permission,
e.g. privileged read/write, unprivileged read-only, execute never...).
Memory partitions would be defined by set of MPU regions or MMU tables
underneath.
A thread could only belong to a single memory domain any point in time
but a memory domain could contain multiple threads.
Threads in the same memory domain would have the same access permission
to the memory partitions belong to the memory domain.

The memory domain APIs are used by unprivileged threads to share data
to the threads in the same memory and protect sensitive data from
threads outside their domain. It is not only for improving the security
but also useful for debugging (unexpected access would cause exception).

Jira: ZEP-2281

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-09-29 16:48:53 -07:00
Andrew Boie
13ca6fe284 syscalls: reorganize headers
- syscall.h now contains those APIs needed to support invoking calls
  from user code. Some stuff moved out of main kernel.h.
- syscall_handler.h now contains directives useful for implementing
  system call handler functions. This header is not pulled in by
  kernel.h and is intended to be used by C files implementing kernel
  system calls and driver subsystem APIs.
- syscall_list.h now contains the #defines for system call IDs. This
  list is expected to grow quite large so it is put in its own header.
  This is now an enumerated type instead of defines to make things
  easier as we introduce system calls over the new few months. In the
  fullness of time when we desire to have a fixed userspace/kernel ABI,
  this can always be converted to defines.

Some new code added:

- _SYSCALL_MEMORY() macro added to check memory regions passed up from
  userspace in handler functions
- _syscall_invoke{7...10}() inline functions declare for invoking system
  calls with more than 6 arguments. 10 was chosen as the limit as that
  corresponds to the largest arg list we currently have
  which is for k_thread_create()

Other changes

- auto-generated K_SYSCALL_DECLARE* macros documented
- _k_syscall_table in userspace.c is not a placeholder. There's no
  strong need to generate it and doing so would require the introduction
  of a third build phase.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-28 08:56:20 -07:00
Chunlin Han
95d28e53bb arch: arm: add initial support for CONFIG_USERSPACE
add related configs & (stub) functions for enabling
CONFIG_USERSPACE on arm w/o build errors.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-09-26 10:00:53 -07:00
Maureen Helm
f0d50979e8 mcux: nxp_kinetis: Move HAS_TRNG config to ext
SoCs outside the Kinetis family can have the TRNG module, so move the
HAS_TRNG config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
5ba9f26b46 mcux: nxp_kinetis: Move HAS_RNGA config to ext
SoCs outside the Kinetis family can have the RNGA module, so move the
HAS_RNGA config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
694c7f5ca4 mcux: nxp_kinetis: Move HAS_FTM config to ext
SoCs outside the Kinetis family can have the FTM module, so move the
HAS_FTM config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Note that 'select HAS_FTM' was previously missing from Kconfig.soc and
is now fixed.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
f7a37cea8d mcux: nxp_kinetis: Move HAS_ADC16 config to ext
SoCs outside the Kinetis family can have the ADC16 module, so move the
HAS_ADC16 config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
fe4c3aacba mcux: nxp_kinetis: Move HAS_LPSCI config to ext
SoCs outside the Kinetis family can have the LPSCI module, so move the
HAS_LPSCI config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
bbafc833db mcux: nxp_kinetis: Move HAS_LPUART config to ext
SoCs outside the Kinetis family can have the LPUART module, so move the
HAS_LPUART config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Anas Nashif
66f1f89da9 qemu: cleanup qemu configurations
Move all QEMU related defines to the boards and cleanup xtensa platforms
which were marked to be QEMU capable by mistake.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-23 16:51:20 -07:00
Andrew Boie
df5cc172f4 gen_mmu.py: load directly
On most workstations this was unintentionally being run under Python 2.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-21 13:27:25 -04:00
Anas Nashif
db4eba64da dfu: img_util: move flash defines to SoC
mcuboot_constraints.h had FLASH information related to the SoC that
should be maintained as part of the SoC and not in the subsystem. Also
fixed Makefiles to check for IMG_UTIL Kconfig and not MCUBOOT.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-21 06:46:27 -04:00
Andrew Boie
1956f09590 kernel: allow up to 6 arguments for system calls
A quick look at "man syscall" shows that in Linux, all architectures
support at least 6 argument system calls, with a few supporting 7. We
can at least do 6 in Zephyr.

x86 port modified to use EBP register to carry the 6th system call
argument.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-20 09:18:59 -07:00
Andrew Boie
a23c245a9a userspace: flesh out internal syscall interface
* Instead of a common system call entry function, we instead create a
table mapping system call ids to handler skeleton functions which are
invoked directly by the architecture code which receives the system
call.

* system call handler prototype specified. All but the most trivial
system calls will implement one of these. They validate all the
arguments, including verifying kernel/device object pointers, ensuring
that the calling thread has appropriate access to any memory buffers
passed in, and performing other parameter checks that the base system
call implementation does not check, or only checks with __ASSERT().

It's only possible to install a system call implementation directly
inside this table if the implementation has a return value and requires
no validation of any of its arguments.

A sample handler implementation for k_mutex_unlock() might look like:

u32_t _syscall_k_mutex_unlock(u32_t mutex_arg, u32_t arg2, u32_t arg3,
                              u32_t arg4, u32_t arg5, void *ssf)
{
        struct k_mutex *mutex = (struct k_mutex *)mutex_arg;
        _SYSCALL_ARG1;

        _SYSCALL_IS_OBJ(mutex, K_OBJ_MUTEX, 0,  ssf);
        _SYSCALL_VERIFY(mutex->lock_count > 0, ssf);
        _SYSCALL_VERIFY(mutex->owner == _current, ssf);

        k_mutex_unlock(mutex);

        return 0;
}

* the x86 port modified to work with the system call table instead of
calling a common handler function. fixed an issue where registers being
changed could confuse the compiler has been fixed; all registers, even
ones used for parameters, must be preserved across the system call.

* a new arch API for producing a kernel oops when validating system call
arguments added. The debug information reported will be from the system
call site and not inside the handler function.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-15 13:44:45 -07:00
Andrew Boie
424e993b41 x86: implement userspace APIs
- _arch_user_mode_enter() implemented
- _arch_is_user_context() implemented
- _new_thread() will honor K_USER option if passed in
- System call triggering macros implemented
- _thread_entry_wrapper moved and now looks for the next function to
call in EDI

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 12:46:36 -07:00
Andrew Boie
9f70c7b281 kernel: reorganize CONFIG_USERSPACE
This now depends on a capability Kconfig.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 12:46:36 -07:00
Anas Nashif
1e8afbfe5a cleanup: remove lots of references to unified kernel
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-12 12:37:11 -04:00
Andrew Boie
d81f9c1e4d x86: revise _x86_mmu_buffer_validate
- There's no point in building up "validity" (declared volatile for some
  strange reason), just exit with false return value if any of the page
  directory or page table checks don't come out as expected

- The function was returning the opposite value as its documentation
  (0 on success, -EPERM on failure). Documentation updated.

- This function will only be used to verify buffers from user-space.
  There's no need for a flags parameter, the only option that needs to
  be passed in is whether the buffer has write permissions or not.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 08:40:41 -07:00
Andrew Boie
3bb677d6eb x86: don't set FS/GS segment selectors
We shouldn't be imposing any policy here, we do not yet use these in
Zephyr. Zero these at boot and otherwise leave alone.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 08:40:08 -07:00
Erwan Gouriou
1ded7d7b33 arch: arm: stm32: factorize stm32f417xy socs defconfig files
stm32f417xe and stm32f417xg have been introduced with 2
different defconfig files. Since same code is declared
in both files, mutualize declarations in a single file.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-09-12 11:24:56 -04:00
Yannis Damigos
0f408a003c arch: soc: st_stm32: Remove unused enumeration from F4, F3 SoCs
The enumerations stm32{f3,f4}x_pin_config_mode aren't used any
more. This patch removes them.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-09-12 11:24:56 -04:00
Andrew Boie
1e06ffc815 zephyr: use k_thread_entry_t everywhere
In various places, a private _thread_entry_t, or the full prototype
were being used. Be consistent and use the same typedef everywhere.

Signen-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-11 11:18:22 -07:00
Anas Nashif
d414e7c7ee kconfig: move fatal error handler to arch options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
8379b7b433 kconfig: move interrupt options into arch menu
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
46f66f4295 kconfig: generalised stack protection options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
939889a202 kconfig: remove unused config DEBUG_IRQS
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
261f898e8f kconfig: remove exta menu for x86 core options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
7c71608fc1 cleanup: remove commented #include
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Anas Nashif
b1991eba94 cleanup: remove the whitespaces before the # character
Indenting preprocessor directives reduces the code readability, because
it make preprocessor directives harder to spot.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Anas Nashif
8920cf127a cleanup: Move #include directives
Move all #include directives at the very top of the file, before any
code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Marti Bolivar
32482e9cb8 flash: stm32: stm32f4: add page layout support
Add flash page layout support for STM32F4 SoCs.

This almost eliminates the need for flash_map.h, except for
STM32F4X_SECTOR_MASK, so delete the file and move the define into the
F4 implementation, to keep things simple.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-09-11 11:41:57 -04:00
Adithya Baglody
609ade891b x86: MMU: Updated MMU code to use the new macros.
Use of X86_MMU_GET_PTE to increase readability of the MMU code.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-09-07 17:13:06 -07:00
Adithya Baglody
65c2432791 x86: MMU: Miscellaneous macros related to MMU.
Helper macros to ease the usage of the MMU page table structures.
Added Macros to get Page table address and Page Table Entry
values.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-09-07 17:13:06 -07:00
Andrew Boie
a34f4fb94f x86: add printk for protection faults
Most x86 exceptions that don't already have their own handlers
are fairly rare, but with the introduction of userspace
people will be seeing General Protection Faults much more
often. Report it as text so that users unfamiliar with x86
internals will know what is happening.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:35:27 -07:00
Andrew Boie
8eaff5d6d2 k_thread_abort(): assert if abort essential thread
Previously, this was only done if an essential thread self-exited,
and was a runtime check that generated a kernel panic.

Now if any thread has k_thread_abort() called on it, and that thread
is essential to the system operation, this check is made. It is now
an assertion.

_NANO_ERR_INVALID_TASK_EXIT checks and printouts removed since this
is now an assertion.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:35:16 -07:00
Andrew Boie
8eeb09765b x86: cleanup _new_thread()
Years of iterative development had made this function more complicated
than it needed to be. Fixed some errors in the documentation as well.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:33:50 -07:00
Andrew Boie
945af95f42 kernel: introduce object validation mechanism
All system calls made from userspace which involve pointers to kernel
objects (including device drivers) will need to have those pointers
validated; userspace should never be able to crash the kernel by passing
it garbage.

The actual validation with _k_object_validate() will be in the system
call receiver code, which doesn't exist yet.

- CONFIG_USERSPACE introduced. We are somewhat far away from having an
  end-to-end implementation, but at least need a Kconfig symbol to
  guard the incoming code with. Formal documentation doesn't exist yet
  either, but will appear later down the road once the implementation is
  mostly finalized.

- In the memory region for RAM, the data section has been moved last,
  past bss and noinit. This ensures that inserting generated tables
  with addresses of kernel objects does not change the addresses of
  those objects (which would make the table invalid)

- The DWARF debug information in the generated ELF binary is parsed to
  fetch the locations of all kernel objects and pass this to gperf to
  create a perfect hash table of their memory addresses.

- The generated gperf code doesn't know that we are exclusively working
  with memory addresses and uses memory inefficently. A post-processing
  script process_gperf.py adjusts the generated code before it is
  compiled to work with pointer values directly and not strings
  containing them.

- _k_object_init() calls inserted into the init functions for the set of
  kernel object types we are going to support so far

Issue: ZEP-2187
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:33:33 -07:00
Youvedeep Singh
7f2aaedfd7 arch: arm: store/restore regs r0-r3 while making function call.
In benchmark test (test_info) while making function call regs
r0 - r4 are modified into called function. Due to this value
inside r3 is getting lost.
This patch saves and restore the value in r0-r4 regs while making
function calls from assembly language.

Jira: ZEP-2314

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-08-31 14:25:31 -04:00
Youvedeep Singh
76b577e180 tests: benchmark: timing_info: Change API/variable Name.
The API/Variable names in timing_info looks very speicific to
platform (like systick etc), whereas these variabled are used
across platforms (nrf/arm/quark).
So this patch :-
1. changing API/Variable names to generic one.
2. Creating some of Macros whose implimentation is platform
depenent.

Jira: ZEP-2314

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-08-31 14:25:31 -04:00
Andy Gross
ecb0f3e159 arm: mpu: Account for stack guard size correctly
This patch fixes a couple of issues with the stack guard size and
properly constructs the STACK_ALIGN and STACK_ALIGN_SIZE definitions.

The ARM AAPCS requires that the stack pointers be 8 byte aligned.  The
STACK_ALIGN_SIZE definition is meant to contain the stack pointer
alignment requirements.  This is the required alignment at public API
boundaries (ie stack frames).

The STACK_ALIGN definition is the required alignment for the start
address for stack buffer storage.  STACK_ALIGN is used to validate
the allocation sizes for stack buffers.

The MPU_GUARD_ALIGN_AND_SIZE definition is the minimum alignment and
size for the MPU.  The minimum size and alignment just so happen to be
32 bytes for vanilla ARM MPU implementations.

When defining stack buffers, the stack guard alignment requirements
must be taken into consideration when allocating the stack memory.
The __align() must be filled in with either STACK_ALIGN_SIZE or the
align/size of the MPU stack guard.  The align/size for the guard region
will be 0 when CONFIG_MPU_STACK_GUARD is not set, and 32 bytes when it
is.

The _ARCH_THREAD_STACK_XXXXXX APIs need to know the minimum alignment
requirements for the stack buffer memory and the stack guard size to
correctly allocate and reference the stack memory.  This is reflected
in the macros with the use of the STACK_ALIGN definition and the
MPU_GUARD_ALIGN_AND_SIZE definition.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-31 11:20:26 -05:00
Andy Gross
85481d997b arch: arm: Remove redundant check and fix rounding
This patch removes the redundant stack alignment check being done.  The
stack definition macros enforce the alignment requirements via the
__align() directives.

In addition, fix the rounding down of the psp to be correct.  The
actual initial stack pointer is the end of the stack minus the size of
the __esf structure.  Rounding down after the subtraction will get us
to the correct offset.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-31 11:20:26 -05:00
Leandro Pereira
510e5d7ced arch: xtensa: Use the alternate _Level4Vector routine on ESP32
For some reason, the ESP32 HAL defines XCHAL_EXCM_LEVEL to 3.  This
enables a version of _Level4Vector that doesn't work on this hardware.

Without complete visibility if the version that should work be axed,
keep both in the tree, but build the working other version instead
if building for ESP32.

Jira: ZEP-2556
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-25 15:31:46 -04:00
Kumar Gala
e25ee68bbd arch: arm: stm32f1: Fix how we determine pull-up/pull-down for gpio
When we mask out the GPIO High impedance/Pull-up/Pull-down field we
should be shifting the mask file, not shifting the field.  This is
because all the other defines already assume the shift.

Coverity-CID: 173640

Jira: ZEP-2538

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-08-21 11:18:03 -05:00
Leandro Pereira
d52de29fba esp32: Fix redefinition of BIT() macro
Esp-idf defines the BIT macro that is also defined in Zephyr's
misc/util.h.  Fix the issue by including the esp-idf headers first, so
that a check in util.h won't redefine the macro if it's already
defined.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-19 07:50:18 -04:00
David B. Kinder
81f7c82625 doc: fix misspellings and missing EOF newlines
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-08-16 17:38:41 -05:00
Wayne Ren
480cfac4f2 arch: arc: apply STACK_GUARD_SIZE and optimize the mpu driver
* apply STACK_GUARD_SIZE, no extra space will be added if
  MPU_STACK_GUARD is disabled
* When ARC_STACK_CHECKING is enabled, MPU_STACK_GUARD will be
  disabled
* add two new api: arc_core_mpu_default and arc_core_mpu_region
  to configure mpu regions
* improve arc_core_mpu_enable and arc_core_mpu_disable

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-08-16 16:09:45 -04:00
Wayne Ren
12cc6598b0 arch: arc: Add mpu support
* add arc mpu driver
* modify the corresponding kconfig and kbuild
* currently only em_starterkit 2.2's em7d configuration
  has mpu feature (mpu version 2)
* as the minimum region size of arc mpu version 2 is 2048 bytes and
  region size should be power of 2, the stack size of threads
  (including main thread and idle thread) should be at least
  2048 bytes and power of 2
* for mpu stack guard feature, a stack guard region of 2048 bytes
  is generated. This brings more memory footprint
* For arc mpu version 3, the minimum region size is 32 bytes.
* the codes are tested by the mpu_stack_guard_test and stackprot

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-08-16 16:09:45 -04:00
Andrew Boie
e434260e19 xtensa: soc: fix IRQ table
The linker scripts were not properly updated to the new
gen_isr_tables mechanism.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-16 10:59:10 -07:00
Gil Pitney
4f67a6c76d cc3200: Remove TI cc3200 SOC and LaunchXL board support
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."

Effectively, the CC3220 SOC replaces the CC3200.

This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.

Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-15 11:02:48 -05:00
Andrew Boie
de6663f601 esp32: fix linker script issues
- .text, .text.*, .literal, .literal.* had no matching input section
   rule and were being passed to the output binary verbatim. These
   are all now in the output "text" section as intended.

- various rules in the data section were unnecessarily using KEEP().

- SW_ISR_TABLE wasn't included in linker script anywhere and was
  ending up in its own section, and not the data section as intended.

- noinit section didn't exist at all, now defined.

Issue: ZEP-2508
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-14 15:27:17 -04:00
Andrew Boie
67a51f9a9e quark_d2000: fix IDT_LIST definition
This should be the same size as other x86 boards.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-14 14:45:07 -04:00
Gil Pitney
1a5537811f cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int
Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with
the NWP interrupt number of 171 caused a hard fault during a
subsequent svc #0 instruction during _Swap().

GNU compiler is generating a bit extension instruction (sxtb) which
converts a positive IRQ value argument to a negative value when
casting to the CMSIS IRQn_Type enum parameter type.

This generates a negative index, which then writes to an SCB
control register instead of NVIC register, causing a hard
fault later on.

This issue only occurs when passing interrupt numbers > 0x80
(eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis.

The solution here is simply to redefine IRQn_Type to be an
unsigned 32 bit integer, while redefining the CMSIS IRQn_Type
enum definitions for interrupts less than zero.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-10 16:46:49 -05:00
Wayne Ren
f8d061faf7 arch: arc: add nested interrupt support
* add nested interrupt support for interrupts
   + use a varibale exc_nest_count to trace nest interrupt and exception
   + regular interrupts can be nested by regular interrupts and fast
interrupts
   + fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
   + remove the coressponding kconfig option
   + all interrupts (normal and fast) and exceptions will be handled
     in the same stack (_interrupt stack)
   + the pros are, smaller memory footprint (no firq stack), simpler
     stack management, simpler codes, etc.. The cons are, possible
     10-15 instructions overhead for the case where fast irq nests
     regular irq
* add the case of ARC in test/kernel/gen_isr_table

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-10 12:47:15 -04:00
Huaqi Fang
725c525a13 boards: em_starterkit: Move peripheral configs from soc to board level
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
7ac0a6a9d1 arc: em7d: Report error when build for 2.3's em7d
When you build application for em starterkit 2.3 em7d, it will
report error during build since it is not supported currently.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
8dfefdf310 arc: em9d/em11d: Update default configurations
Update configurations to support em9d and em11d in
em starterkit 2.2 and 2.3

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
c58aadfece arc: em9d/em11d: Modify and cleanup soc.h
em starterkit has two versions, 2.2 and 2.3.
Change soc.h to support both versions,
main changes are the interrupt connections.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
403e2803bf arc: em7d: Clean up arch/arc/soc/em7d/soc.h
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
7a1f06b374 arc: em7d: Add support for em starterkit 2.2 EM7D
Since em starterkit has different firmware versions(2.2 and 2.3),
but the EM7D of 2.3 has new secureshield feature, which is not supported
in Zephyr, but EM7D of 2.2 is a normal EM core, which can be supported,
so we add support for 2.2 EM7D.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
d4e9c97173 arc: Remove unused backslash in makefile of arc em9d
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Xiaorui Hu
eb48a0a73c arm: armv6-m: Support relocating vector table
An abnormal crash was encountered in ARMv6-M SoCs that don't have flash
starting at 0.  With Zephyr OS the reason for this crash is that, on
ARMv6-M the system requires an exception vector table at the 0 address.

We implement the relocate_vector_table function to move the vector table
code to address 0 on systems which don't have the start of code already
at 0.

[kumar.gala: reworderd commit message, tweaked how we check if we need
 to copy vector table]

Signed-off-by: Xiaorui Hu <xiaorui.hu@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-08-09 18:13:29 -04:00
Maureen Helm
469ddab780 pwm: Remove k64-specific driver and k20_sim.h
Now that we have an mcux shim driver, remove the old k64-specific
driver. Also remove include/drivers/k20_sim.h, since the old
k64-specific driver was the only thing left using it.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Maureen Helm
57bd281d4d nxp_kinetis: Switch default pwm driver to mcux
Switches the default pwm driver from the k64-specific driver to the
mcux shim, which can be used on other SoCs with the ftm peripheral.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Maureen Helm
060bf8ea6a pwm: Introduce new mcux ftm shim driver
Adds a shim layer around the mcux ftm driver to adapt it to the Zephyr
pwm interface.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Erwin Rol
8e6ebdb090 arm: support for stm32f417 SOC
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-09 14:53:47 -05:00
Leandro Pereira
99181eb661 arch: xtensa: Move exception table to xtensa_intr.c
This cleans up the exception handling by removing the table declaration
from xtensa_intr_asm.S, and removing the unused
_xt_set_exception_handler() function.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
1e506d3b42 arch: xtensa: Remove mentions of dynamic interrupt settings
Dynamic IRQ allocation has been yanked from Zephyr a few releases ago,
so there's no point in keeping these options available.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
c0c79a8041 drivers: gpio: esp32: Add ESP32 GPIO driver
This provides basic GPIO support, with interrupts, and the ability to
read and write to ports on a pin-by-pin basis.

Jira: ZEP-2286
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Erwin Rol
57746488d4 arm: support for stm32f405 SOC
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-09 14:24:21 -05:00
Andy Gross
5930e9d02d arm: mpu: Adjust to use opaque kernel data types
This patch adjusts the ARM MPU implementation to be compliant to the
recent changes that introduced the opaque kernel data types.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-09 13:36:09 -05:00
Michel Jaouen
deeaa40e1e arm: mpu: fix: align stack for mpu stack guard
The mimimum mpu size is 32 bytes, but requires mpu base address to be
aligned on 32 bytes to work. Define architecture thread macro when
MPU_STACK_GUARD config to allocate stack with 32 more bytes.

Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
2017-08-09 13:36:09 -05:00
Yannis Damigos
0848843c04 arch: arm: stm32f1: Add missing input port configuration
This patch adds missing configuration bits when GPIO is
configured as input

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-08-09 10:11:51 -05:00
Yannis Damigos
a66b92459b arch: arm: stm32f1: Shift GPIO pin configuration values only once
In the stm32_gpio_flags_to_conf function the configuration
values of the GPIO pin are shifted two times. One in the
stm32-pinctrlf1 header and one in the function. This patch
removes one of those shifts.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-08-09 10:11:51 -05:00
Adithya Baglody
ab7b02ce67 x86: MMU: Bug in _x86_mmu_buffer_validate
The value of the PTE (starting_pte_num) was not
calulated correctly. If size of the buffer exceeded 4KB,
the buffer validation API was failing.

JIRA: ZEP-2489

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-08-09 07:06:22 -07:00
Johan Hedberg
2975ca0754 Bluetooth: Kconfig: Rename CONFIG_BLUETOOTH_* to CONFIG_BT_*
The API name space for Bluetooth is bt_* and BT_* so it makes sense to
align the Kconfig name space with this. The additional benefit is that
this also makes the names shorter. It is also in line with what Linux
uses for Bluetooth Kconfig entries.

Some Bluetooth-related Networking Kconfig defines are renamed as well
in order to be consistent, such as NET_L2_BLUETOOTH.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2017-08-09 11:14:19 +03:00
Vincenzo Frascino
de81c16c5a arm: core: mpu: Add Allow write on Flash
This patch adds the allow flash write CONFIG option to the ARM MPU
configuration in privileged mode.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
2017-08-08 11:20:46 -05:00
Vincenzo Frascino
6489b9a0f2 arm: soc: nxp k6x: Add Allow write on Flash
This patch adds the allow flash write CONFIG option to the NXP MPU
configuration in privileged mode.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
2017-08-08 11:20:46 -05:00
Youvedeep Singh
24e083c5d6 arm: handle time slicing before context switch on exception.
Currently Thread time slice is getting reset at end of timer
interrupt. Due to which equal priority threads behind current thread
in ready_q are not getting chance to run and leading to starvation.

This patch handles time slice in _ExcExit section context switch is
required.

Jira: ZEP-2444

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-08 09:33:25 -04:00
Anas Nashif
09bcd8ee74 Kconfig: make all syslog variables depend on SYS_LOG
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-04 14:34:54 -05:00
Andrew Boie
80e82e7205 x86: stack overflow improvements
As luck would have it, the TSS for the main IA task has
all the information we need, populate an exception stack
frame with it.

The double-fault handler just stashes data and makes the main
hardware thread runnable again, and processing of the
exception continues from there.

We check the first byte before the faulting ESP value to see
if the stack pointer had run up to a non-present page, a sign
that this is a stack overflow and not a double fault for
some other reason.

Stack overflows in kernel mode are now recoverable for non-
essential threads, with the caveat that we hope we weren't in
a critical section updating kernel data structures when it
happened.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
25a8aef275 x86: enable MMU for application memory
Configuring the RAM/ROM regions will be the same for all
x86 targets as this is done with linker symbols.

Peripheral configuration left at the SOC level.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
0f16d98b32 x86: mmu: add runtime modification indicator
The CPU first checks the page directory entry for write
or user permissions on a particular page before looking
at the page table entry.

If a region configured all pages to be non user accessible,
and this was changed for a page within it to be accessible,
the PDE would not be updated and any access would still
return a page fault.

The least amount of runtime logic to deal with this is to
indicate at build time that some pages within a region may
be marked writable or user accessible at runtime, and to
pre-set the flags in the page directory entry accordingly.

The driving need for this is the region configuration for
kernel memory, which will have user permissions set at
runtime for stacks and user-configured memory domains.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
9ffaaae5ad x86: additional debug output for page faults
Page faults will additionally dump out some interesting
page directory and page table flags for the faulting
memory address.

Intended to help determine whether the page tables have been
configured incorrectly as we enable memory protection features.

This only happens if CONFIG_EXCEPTION_DEBUG is turned on.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Erwin Rol
cf7765327b arch: arm: stm32: f3/f4/l4: write output speed to hardware register
The ouput speed of the gpio pins passed via the 'conf' argument was
ignored, causing the speed to always be in its reset state (lowest
possible speed for most pins). This was causing problems for pins that
actually need a speed faster than the default, like the ethernet
controller pins.

Combined with the correct pinmux configuration this fixes problems
of the olimex_stm32_e407 board not being able to send ethernet data.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-02 12:28:11 -05:00
Andrew Boie
507852a4ad kernel: introduce opaque data type for stacks
Historically, stacks were just character buffers and could be treated
as such if the user wanted to look inside the stack data, and also
declared as an array of the desired stack size.

This is no longer the case. Certain architectures will create a memory
region much larger to account for MPU/MMU guard pages. Unfortunately,
the kernel interfaces treat both the declared stack, and the valid
stack buffer within it as the same char * data type, even though these
absolutely cannot be used interchangeably.

We introduce an opaque k_thread_stack_t which gets instantiated by
K_THREAD_STACK_DECLARE(), this is no longer treated by the compiler
as a character pointer, even though it really is.

To access the real stack buffer within, the result of
K_THREAD_STACK_BUFFER() can be used, which will return a char * type.

This should catch a bunch of programming mistakes at build time:

- Declaring a character array outside of K_THREAD_STACK_DECLARE() and
  passing it to K_THREAD_CREATE
- Directly examining the stack created by K_THREAD_STACK_DECLARE()
  which is not actually the memory desired and may trigger a CPU
  exception

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-01 16:43:15 -07:00
Kumar Gala
68732efe00 arm: nxp: mcux lpuart: Get IRQ info from DTS
Move to using the generated IRQ defines from the DTS instead of soc.h.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-27 09:27:47 -05:00
Kumar Gala
0ef91e4d07 arm: nxp: mcux uart: Get IRQ info from DTS
Move to using the generated IRQ defines from the DTS instead of soc.h.
This change also fixes a minor bug in that the error irq priority wasn't
getting correctly picked up from device tree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-27 09:27:47 -05:00
Erwan Gouriou
72d2960741 arch: arm: stm32f3: Rework pinmux handler
STM32F3 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
8763939763 arch: arm: stm32f4: Rework pinmux handler
STM32F4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
8d0150000c arch: stm32f1: rework pinmux driver
Rework stm32f1 pinmux code for future dts based pinmux code
generation.
Pin configuration is now done directly thanks to gpio port
configuration. Reference to pseudo alternate functions are
now removed same as the use of pins[] array.
Pins function (uart tx for instance) is set implicitly by
defining gpio mode and configuration.
This behavior is specific to stm32f10x series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
2366d23573 arch: arm: stm32l4: Rework pinmux driver
STM32L4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed and information is transferred to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
92c7ef5939 arch: stm32: l4: factorize HAS_STM32CUBE
In L4 series, select HAS_STM32CUBE is done per soc.
This could be factorized in Kconfig.series.
Aim is  to lower the steps to add a new SoC.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 09:52:59 -05:00
Andrew Boie
d944950aaa x86: install guard page for interrupt stack
We need to know when the interrupt stack overflows as well as
thread stacks.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-26 05:57:45 -04:00
Kumar Gala
0e7067c6be arm: dts: cleanup uart related Kconfig options
Now that we generate BLUETOOTH_UART_ON_DEV_NAME, UART_PIPE_ON_DEV_NAME,
and BLUETOOTH_MONITOR_ON_DEV_NAME Kconfig defines for dts enabled
platforms add those into the appropriate dts files and remove from the
various board/Kconfig.defconfig files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-25 12:23:20 -05:00
Andrew Boie
054d47b29c x86: set stack guard page non-writable
This will trigger a page fault if the guard area
is written to. Since the exception itself will try
to write to the memory, a double fault will be triggered
and we will do an IA task switch to the df_tss and panic.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
0fab8a6dc5 x86: page-aligned stacks with guard page
Subsequent patches will set this guard page as unmapped,
triggering a page fault on access. If this is due to
stack overflow, a double fault will be triggered,
which we are now capable of handling with a switch to
a know good stack.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
6101aa6220 x86: add API for modifying page tables
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
bc666ae7f7 x86: implement improved double-fault handler
We now create a special IA hardware task for handling
double faults. This has a known good stack so that if
the kernel tries to push stack data onto an unmapped page,
we don't triple-fault and reset the system.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
08c291306e x86: generate RAM-based GDT dynamically
We will need this for stack memory protection scenarios
where a writable GDT with Task State Segment descriptors
will be used. The addresses of the TSS segments cannot be
put in the GDT via preprocessor magic due to architecture
requirments that the address be split up into different
fields in the segment descriptor.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
8a102e44ed x86: allow IDT vectors to be task gates
This has one use-case: configuring the double-fault #DF
exception handler to do an IA task switch to a special
IA task with a known good stack, such that we can dump
diagnostic information and then panic.

Will be used for stack overflow detection in kernel mode,
as otherwise the CPU will triple-fault and reset.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
ddf9f4be31 x86: convert gen_idt to Python
This is one less host tool we have to compile for every build,
and makes the build tools more portable across host OSes.
The code is also much simpler to maintain.

Issue: ZEP-2063
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
dff21de082 x86: add CONFIG_X86_STACK_PROTECTION
This enables the MMU-based stack protection feature,
which will cause a fatal error if a thread overflows
its stack in kernel mode, at a nontrivial cost in memory
(4K per thread).

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
a717050140 qemu_x86: terminate emulator on fatal system error
This will cause sanitycheck runs to finish more quickly
instead of sitting there waiting on a timeout. We already
do this with the Xtensa simulator.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-22 09:46:26 -04:00
Erwan Gouriou
46d66163eb arch: arm: stm32l4: Add pin config for USART1 on PB6/PB7
With introduction of commit "pinmux: stm32: directly return error if
stm32_get_pin_config fails", pin configuration fails when
pins are not configured in pins[] array.
This was the case for configuration UART1 assigned on PB6/PB7.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-20 07:30:32 -05:00
Michał Kruszewski
fda632adec nrf5: uart: Add support for 300 and 600 baud rates.
Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
2017-07-20 07:30:04 -05:00
Savinay Dharmappa
addb12b463 arch: quark_se: select config UART_QMSI_0 by default
'commit
("devicetree: Generate BLUETOOTH_UART ,UART_PIPE etc config from dt")'
created a dependency of selecting UART_QMSI_0 on device tree.
This change is reverted as it incorrect.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-07-20 07:12:00 -05:00
Maureen Helm
db3891fc23 arm: nxp_kinetis: Enable the mcux adc16 driver for all Kinetis SoCs
If the adc driver configuration is enabled (CONFIG_ADC=y), then enable
the mcux shim driver by default for all Kinetis SoCs.

Jira: ZEP-1396

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-19 14:28:08 -05:00
Maureen Helm
8ff51559da adc: Introduce new mcux adc16 driver
Adds a shim layer around the mcux adc16 driver to adapt it to the Zephyr
adc interface.

Jira: ZEP-1396

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-19 14:28:08 -05:00
Savinay Dharmappa
c1e5cbfd41 devicetree: Generate BLUETOOTH_UART,UART_PIPE etc config from dt
patch uses chosen property zephyr,bt-uart, zephyr,uart-pipe
and zephyr,bt-mon-uart to determine the uart instance to be
used for bluetooth,uart_pipe and bluetooth_monitor and generate
appropriate configs.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-07-19 11:52:35 -04:00
Savinay Dharmappa
7578035f4c dts: x86: Add device tree support for quark_d2000 microcontroller
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-07-19 11:25:43 -04:00
Adithya Baglody
079b17b312 x86: MMU: Validate user Buffer
A user space buffer must be validated before required operation
can proceed. This API will check the current MMU
configuration to determine if the buffer held by the user is valid.

Jira: ZEP-2326

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-07-19 08:06:44 -07:00
Andrew Boie
74afcb67ae arches: move _NanoFatalErrorHandler defintion
This needs to be in <arch/cpu.h> so that it can be called
from the k_panic()/k_oops() macros in kernel.h.

Fixes build errors on these arches when using k_panic() or
k_oops().

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-18 09:34:23 +03:00
Andrew Boie
08a9fcdb80 x86: ia32: set access based on linker regions
This will set program text and rodata as read-only even in
non-XIP systems.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-15 12:17:36 -07:00
Erwin Rol
be88626695 pinmux: stm32: add ethernet controller pins
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-07-12 12:53:51 +03:00
Kumar Gala
65e72be8f7 devicetree: Generate CONFIG_UART_CONSOLE_ON_DEV_NAME from dt
We can use the chosen property "zephyr,console" to determine what uart
should be used as the console and find its name to generate a define for
CONFIG_UART_CONSOLE_ON_DEV_NAME.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-11 12:09:10 -05:00
Andrew Boie
c9814f5104 mmustructs: don't use addr to name structures
This breaks too easily, for example if &some_linker_variable
is used. The names don't matter at all, use preprocessor
__COUNTER__.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-10 11:44:56 -07:00
Andrew Boie
103d655dee qemu_x86: increase to 8MB of RAM
Previously we were instantiating QEMU with 32MB of RAM but
only enabling a small fraction of it.

Now we boot with 8MB of ram. We ignore the first 4K so we can
make that an unmapped paged to catch NULL pointer dereferences.

If XIP is enabled, the "ROM" region will be the first half of
memory, the "RAM" region the latter.

Move the IDT_LIST and MMU_LIST regions elsewhere so they don't
overlap the new memory arrangement.

Use !XIP to fix a problem where CONFIG_RAM_SIZE was set incorrectly
for XIP case.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-10 11:44:56 -07:00
Erwin Rol
2fc9dc61d4 drivers: stm32: random: Initial STM32 random number generator driver
Add a STM32 LL based driver for the RNG processor. The RNG processor
is a random number generator, based on a continuous analog noise, that
provides a random 32-bit value to the host when read. The RNG passed
the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-07-07 07:27:39 -05:00
Kumar Gala
8e8d49a620 i2c: stm32: Cleanup how we enable the specific I2C driver
Right now we allow for the I2C subsystem to be built without any drivers
enabled that utilize it.  When we added support for the new STM32 I2C
driver we forced the I2C driver to be enabled if the I2C subsystem was
enabled.  While this makes a reasonable amount of sense, it breaks
current assumptions for various testcases that we need to cleanup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-05 11:33:08 -05:00
Jorge Ramirez-Ortiz
dd2eeaf352 pinmux: stm32f4: Add SPI2 pins on PB12, PB13, PB14 & PB15
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-07-01 08:36:51 -04:00
Jorge Ramirez-Ortiz
3ebb412fa9 pinmux: stm32f4: Add SPI1 pins on PA4, PA5, PA6 & PA7
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-07-01 08:36:51 -04:00
Jorge Ramirez-Ortiz
ae4363817b stm32cube: build stm32xxx_ll_spi if CONFIG_SPI
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-07-01 08:36:51 -04:00
Jorge Ramirez-Ortiz
21fbc9b07e drivers: i2c: stm32 LL F1/F4 (v1) STM32 F3/L4X (v2)
Supports STM32 F1/F4 (v1 controller) and STM32 F3/L4X (v2
controller)

v1 could also support L1X.
v2 could also support F7X.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Reviewed-by: Yannis Damigos <giannis.damigos@gmail.com>
Tested-by: Yannis Damigos <giannis.damigos@gmail.com>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-01 08:36:51 -04:00
Yannis Damigos
220ddb9738 soc: stm32: F1/F3/F4/L4: enable I2C LL
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-01 08:36:51 -04:00
Yannis Damigos
676a82cd73 arch: stm32f1: Fix typo in soc_config
Fix typo in soc_config.c

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-07-01 08:36:51 -04:00
Yannis Damigos
ecbb3b6c04 pinmux: stm32 F1X/F3X/F4X: add I2C
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-07-01 08:36:51 -04:00
Jean-Paul Etienne
34862656b9 riscv32: fixed context restore upon exiting ISR
By now, t0 register restored value is overwritten
by mepc and mstatus values prior to returning from ISR.

Fixed by restoring mstatus and mepc registers before
restoring the caller-saved registers.

As t0 is a temporary register within the riscv ABI,
this issue was unnoticed for most applications, except
for computation intensive apps, like crypto tests.

Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-06-30 06:31:51 -04:00
Andrew Boie
2bc0fa9bd5 qemu_x86: ia32: fix ROM size with XIP enabled
The defaults of 0x100000 for ROM and 0x400000 for RAM are intended
to 'fake' a XIP configuration, this all takes place in just RAM.

The gap between these two values is 3 megabytes, specify this
properly.

Fixes numerous test cases on qemu_x86 if CONFIG_XIP is enabled.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-29 07:46:58 -04:00
Andrew Boie
3d8aaf7099 x86: implement bss zero and data copy for application
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-29 07:46:58 -04:00
Kumar Gala
534beb34c9 tests: boot_time: cleanup boot_time test to work on ARM
Enabled the boot_time test on ARM SoCs, set __start_time_stamp on ARM
since we don't have a free running counter similar to TSC on x86.
Also moved to printing the values out as %u to increase the range of
values.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-06-29 07:08:59 -04:00
Johann Fischer
08df5961b3 arch: intel_quark: use DW device driver when USB is selected
This patch allows more generic USB configuration in the samples
and removes platform dependent driver configuration.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-06-28 15:14:15 -04:00
Andrzej Puzdrowski
8b7a8448ab Drivers: flash: NRF5x: synchronous mode for co-operation with BLE radio
In added mode flash operation are performed in timeslice
(in radio idle time).
Kconfig for mode enabling CONFIG_SOC_FLASH_NRF5_RADIO_SYNC.

Erase and write API implementations were rewritten and preserved against
concurrent execution.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2017-06-28 12:29:50 +02:00
Kumar Gala
d426d122f1 boards; cc2650_sensortag: Get building with sanitycheck
Board port was done before the yaml transition, so was missing a
cc2650_sensortag.yaml.  As such when we build all the test we get a few
build errors that we also fixed up.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-06-23 15:05:10 -05:00
Siddharth Chandrasekaran
f7705af136 boards: arm: Add support for STM32 Minimum Development Board
Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.

Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
2017-06-23 15:05:10 -05:00
Siddharth Chandrasekaran
09fb996c70 arm: stm32f1: Add support for STM32F103x8 SoC
Add configuration and memory definitions to support STM32F103x8
Medium-density performance line SoC with 64 KB Flash.

Merge multiple files into single Kconfig.defconfig.stm32f103xx

Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
2017-06-23 15:05:10 -05:00
Michel Jaouen
a868fdb13d arm: soc: stm32: f3: add MPU capability
Since not all socs from f3 series (i.e stm32f334x8 no MPU) have MPU
capability, add capability only for MPU capable socs in Kconfig.soc

JIRA: ZEP-2220

Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
2017-06-23 15:05:10 -05:00
Michel Jaouen
5cdfe0fcb7 arm: soc: stm32: l4: add MPU capability for series
Since all l4 socs support MPU, add MPU capability in KConfig.series

JIRA: ZEP-2220

Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
2017-06-23 15:05:10 -05:00
Michel Jaouen
1dadfaa3b4 arm: soc: stm32: make mpu f4 config useable for other family
As other stm32 series support MPU, move common file in a file tree
useable by socs from other series

JIRA: ZEP-2220

Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
2017-06-23 15:05:10 -05:00
Savinay Dharmappa
ce1add260b dts: x86: Add dts support for x86
patch adds necessary files and does the modification to the existing
files to add device support for x86 based intel quark microcontroller

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-06-22 10:23:39 -05:00
Leandro Pereira
d19252a46d arch: xtensa: Use CONFIG_SIMULATOR_XTENSA to set XT_{BOARD,SIMULATOR}
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 18:09:13 -04:00
Leandro Pereira
0e08b946de soc: esp32: Define __start as a C function
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs.  So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.

This ESP32-specific initialization will perform the following:

  - Disable the watchdog timer that's enabled by the bootloader
  - Move exception handlers to IRAM
  - Disable normal interrupts
  - Disable the second CPU
  - Zero out the BSS segment

Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira
4ca586e62d arch: xtensa: Use Zephyr configuration options
Unconditionally use CONFIG_SIMULATOR_XTENSA to determine if XT_SIMULATOR
or XT_BOARD should be defined.

If CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, also define XT_CLOCK_FREQ.  This
isn't ideal as the clock frequency might be changed in runtime and this
effectively makes it a constant.

Until we can control the clock frequency in runtime, this will suffice.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Ivan Grokhotkov
d58d5d1265 xtensa: esp32: configure default UART using ROM functions
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Ivan Grokhotkov
f7005105e9 xtensa: esp32: place .rodata into DRAM
Until ESP32’s flash cache is utilized, .rodata must be stored in RAM.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira
37ea77173c drivers: esp32: Add minimal UART driver based on ROM routines
This is a minimal driver enabling console output during the port
bringup.  While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts.  This will most likely be superceded by a proper
driver after the port has matured.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira
88790ae71d arch: xtensa: Add ESP32 SoC
Due to the configurable nature of the Xtensa platform, the generic name of
"LX6" cannot be used to describe an SoC as far as Zephyr goes.  So ESP32 is
defined both as a SoC and as a board.

This is based on work by Rajavardhan Gundi.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Anas Nashif
397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Geoffrey Le Gourriérec
fdf1785775 arm: Add support for TI's CC2650 SoC.
Add support in arch/arm/soc/ti_simplelink, along with support
for CC32xx SoC.

Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
2017-06-16 16:18:12 -04:00
Geoffrey Le Gourriérec
6341258ef5 drivers: serial: uart_stellaris: Remove UART_IRQ_FLAGS
We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a
0 argument for the flags, and remove the UART_IRQ_FLAGS.  This is
towards support for using the driver on the TI CC2650.  (we add a
comment about that as well).

Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-06-16 16:18:12 -04:00
Piotr Mienkowski
c1c1ce3cbb arch: same70: Fix ERASE pin configuration
Correct code that allows to disable ERASE pin functionality
during boot.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-06-16 16:18:12 -04:00
Maureen Helm
257e22bf38 arm: nxp: mpu: Fix region descriptor 0 attributes
Clearing fields in the region descriptor attributes doesn't always have
the expected effect of revoking permissions. In the case of bus master
supervisor mode fields (MxSM), setting to zero actually enables read,
write, and execute access.

When we reworked handling of region descriptor 0, we inadvertently
enabled execution from RAM by clearing the MxSM fields and enabling the
descriptor. This caused samples/mpu_test run to throw a usage fault
instead of an MPU-triggered bus fault.

Fix this by setting all the MxSM fields to 2'b11, which gives supervisor
mode the same access as user mode.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-06-16 16:18:12 -04:00
Adithya Baglody
be1cb961ad tests: benchmark: boot_time: Reading time stamps made arch agnostic
1. Changed _tsc_read() to k_cycles_get_32(). Thus reading the
time stamp will be agnostic of the architecutre used.
2. Changed the variable names from *_tsc to *_time_stamp.

JIRA: ZEP-1426

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-16 07:37:37 -05:00
Adithya Baglody
05c9dd08b0 quark_se: MMU: Add linker support for MMU page table generation.
Add a separate section in the linker to place the MMU configuration
information. This location is read by the gen_mmu.py script to
create the actual page tables.

JIRA: ZEP-2095

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
aab1c1f63c quark_se: MMU: Memory regions for arduino 101(quark_se)
Define the memory regions needed to generate boot time page tables.

JIRA: ZEP-2097

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
43dfd98469 kernel: x86: MMU: Enable MMU at boot time.
In crt0.S the MMU is initialized. It uses the statically build
page tables. Here 32-bit paging scheme is used, thereby each page
table entry maps to a 4KB page. The valid regions of the memory are
specified by SOC specific file(soc.c).

JIRA: ZEP-2099

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
576c1ebba2 qemu: MMU: Memory regions for qemu_x86
Define the memory regions needed to generate boot time page
tables.

JIRA:ZEP-2098

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
83644a493e kernel: x86: MMU: Build system support for x86 MMU
Makefile rule to create the MMU page tables at boot time. This
rule invokes the gen_mmu.py script to create a binary which is
then placed into the kernel image using objcopy.
Makefile.mmu is included only when CONFIG_X86_MMU is enabled.

JIRA: ZEP-2095

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
9bbf5335b9 kernel: x86: MMU: Macros & Linker scripts for Boot time table creation
Macro is used to create a structure to specify the boot time
page table configuration. Needed by the gen_mmu.py script to generate
the actual page tables.

Linker script is needed for the following:
     1. To place the MMU page tables at 4KByte boundary.
     2. To keep the configuration structure created by
        the Macro(mentioned above).

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody
569c6e5203 kernel: MMU: kconfig definition to enable the MMU on x86.
Kconfig definition for enabling the memory management Unit
on x86 based platforms.

JIRA: ZEP-2093

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Michael R Rosen
b5d4a25a11 arc: fix balign position to properly 4byte align global vars
The .balign directives were not working correctly in their
previous positions as the directive was applying to the section
before the variable's section, causing in some builds the
variables to be misaligned, and accesses to them causing faults.
With the alignments after the section declaration, the variables
will now be aligned as specified. Any future variable declarations
should use this form instead to ensure proper alignment.

Signed-off-by: Michael R Rosen <michael.r.rosen@intel.com>
2017-06-12 23:33:31 -04:00
David B. Kinder
9faa5f2033 doc: spelling fixes in Kconfig files
regular spelling check on Kconfig.* files

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-06-12 19:40:51 -04:00
Maureen Helm
1f3f440b22 arm: nxp: mpu: Fix off-by-1 error in region index calculation
Both the ARM and NXP MPU drivers incorrectly calculated the region index
by assuming the region type (e.g., THREAD_STACK_GUARD_REGION) was
zero-indexed, when in reality it is one-indexed. This had the effect of
wasting one region.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-06-12 11:40:12 -05:00
Maureen Helm
bacbea6e21 arm: nxp: mpu: Rework handling of region descriptor 0
The NXP MPU requires special handling of region descriptor 0 to
guarantee that the debugger has access to the entire address space. It
does not allow writes from the core to affect the start or end
addresses, or the permissions associated with the debugger.

The original implementation of this driver attempted to work around
region descriptor 0, resulting in an off-by-1 error caught by Coverity.

Instead, define region descriptor 0 explicitly in the mpu_regions array,
and add some asserts to ensure that one doesn't try to change its start
or end addresses. This has an added benefit such that more permissions
can be enabled in region 0 if desired, whereas the previous
implementation always forced all writable permissions to be cleared.

Coverity-CID: 170473
Jira: ZEP-2258

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-06-12 11:40:12 -05:00
Maureen Helm
d2e38decf0 arm: nxp: mpu: Return constant number of mpu regions
The original implementation of _get_num_regions() parsed the CESR[NRGD]
register field to determine the number of mpu region descriptors
implemented in hardware. There was a possible path in the code to return
zero, which would cause underflow later on in arm_core_mpu_configure().
Coverity complained despite an assert to catch this condition. Instead,
use a preprocessor macro from mcux that defines the number of mpu region
descriptors.

Coverity-CID: 169811
Jira: ZEP-2208

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-06-12 11:40:12 -05:00
Anas Nashif
243671bcdb samples: ipm: fix macro name
replace undefined K_STACK_DECLARE with K_THREAD_STACK_DEFINE.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-09 22:36:23 -04:00
Andrew Boie
567c6c7683 misc: use K_THREAD_STACK_DEFINE macros
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-09 18:53:28 -04:00
Andrew Boie
e3550a29ff stack_sentinel: hang system on failure
Stack sentinel doesn't prevent corruption, it just notices when
it happens. Any memory could be in a bad state and it's more
appropriate to take the entire system down rather than just kill
the thread.

Fatal testcase will still work since it installs its own
_SysFatalErrorHandler.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
Andrew Boie
998f905445 arches: declare _SysFatalErrorHandler __weak
This function is intended to be easily overridable by applications.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
Andrew Boie
ae1a75b82e stack_sentinel: change cooperative check
One of the stack sentinel policies was to check the sentinel
any time a cooperative context switch is done (i.e, _Swap is
called).

This was done by adding a hook to _check_stack_sentinel in
every arch's __swap function.

This way is cleaner as we just have the hook in one inline
function rather than implemented in several different assembly
dialects.

The check upon interrupt is now made unconditionally rather
than checking if we are calling __swap, since the check now
is only called on cooperative _Swap(). The interrupt is always
serviced first.

Issue: ZEP-2244
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
chunlin
e125e5b9c6 arm: core: mpu: Prevent updating unexpected region
The REGION bits (bit[3:0]) of MPU_RBAR register can specify the number
of the region to update if the VALID bit (bit[4]) is also set.

If the bit[3:0] of "region_addr" are not zero, might cause to update
unexpected region. This could happen since we might not declare stack
memory with specific alignment.

This patch will mask the bit[4:0] of "region_addr" to prevent updating
unexpected region.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-06-06 12:21:21 -05:00
Andrew Boie
6d4763129d riscv32: update time slice before swap
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-02 14:47:01 -04:00
Andrew Boie
7b7fbf851e nios2: reset timeslice on interrupt-induced swap
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-02 14:47:01 -04:00
Andrew Boie
3989de7e3b kernel: fix short time-slice reset
The kernel tracks time slice usage with the _time_slice_elapsed global.
Every time the timer interrupt goes off and the timer driver calls
_nano_sys_clock_tick_announce() with the elapsed time, this is added to
_time_slice_elapsed. If it exceeds the total time slice, the thread is
moved to the back of the queue for that priority level and
_time_slice_elapsed is reset to zero.

In a non-tickless kernel, this is the only time _time_slice_elapsed is
reset.  If a thread uses up a partial time slice, and then cooperatively
switches to another thread, the next thread will inherit the remaining
time slice, causing it not to be able to run as long as it ought to.

There does exist code to properly reset the elapsed count, but it was
only compiled in a tickless kernel. Now it is built any time
CONFIG_TIMESLICING is enabled.

Issue: ZEP-2107
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-02 14:47:01 -04:00
Florian Vaussard
6ad43279ec arm: stm32f4: Add basic support for STM32F412
Add necessary Kconfig and minimal device tree in order to support
STM32F412ZG variant as found on the Nucleo STM32F412 board.

Origin: Original

Change-Id: Ic98a686f478ce551dc6101466ed0cf16924109e8
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-06-02 14:11:13 -04:00
Erwan Gouriou
9413c8ba4d stm32: clean up after completion of transition to ll Clock control
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-06-02 14:11:13 -04:00
Erwan Gouriou
f2e8a21d7f stm32f1xx: remove references to native driver
Following introduction of stm32cube LL based clock control driver,
remove references to former native driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-06-02 14:11:13 -04:00
Erwan Gouriou
e1a90583d4 drivers: clock_control: provide LL based driver to stm32f1xx series
Align stm32f1xx series clock driver to other parts of stm32 family.
Driver support both Connectivity and Density lines of stm32f1 series,
that are based on different Reset and Clock Control architectures.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-06-02 14:11:13 -04:00
Florian Vaussard
3540f03ef3 stm32f4: mpu: Add support for 1.5MB Flash / 320kB SRAM variants
The STM32F413ZH has 1536kB of Flash and 320kB of SRAM. This
configuration is currently not supported by ST MPU driver, so fill in
the blanks.

Note: The MPU does not support region size that is not a power-of-2 (see
the SIZE field in the MPU_RASR register). This is a problem for our
1536kB Flash region, so it was rounded up to the nearest choice. This is
possible because the memory in the range 0x0818000 - 0x0FFFFFFF is
"Reserved" and thus not mapped anyway.

Change-Id: If0c3d1db564ca45e77f8b5bafa2afdbafa85b40f
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-06-02 14:11:13 -04:00
Piotr Mienkowski
b686102465 arch: sam3x: Fix TWI pin naming
SAM3X has TWI module, not TWIHS. Pin names are corrected accordingly.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-06-02 14:11:13 -04:00
Andrew Boie
a2156fec2c arm: implement __svc on Cortex M0
This is needed for irq_offload() and k_oops()/k_panic()

Issue: ZEP-2221
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-02 02:17:32 -04:00
Anas Nashif
b330e0e4a9 Revert "x86: call gen_idt with $ZEPHYR_BASE too"
This reverts commit 37f4178f58.

This change builds gen_idt in the zephyr project tree instead of
building it in outdir of the application. The build process should all
happen inside outdir and no binaries should be placed in the zephyr
tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-01 10:26:57 -04:00
Vinayak Kariappa Chettimada
1084165158 arch: arm: Fix compile error on ARMv6-M SoCs with TICKLESS_KERNEL
pop {lr} instruction is not supported in ARMv6-M, fixed by
using pop {r0}; mov lr, r0; instructions.

Jira: ZEP-2222

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2017-06-01 08:00:46 -04:00
Michael Scott
b4b3e56a09 arm: soc: nordic nRF52: Add MPU support
We now have generic ARM M4 MPU support added to Zephyr.
Let's enable it for use with Nordic nRF52 chips.

Memory Layout was generated from Section 8.3 "Memory
Map" of nRF52 Product Specifications (for both nRF52832
and nRF52840):
0x00000000: Flash
0x10000000: Factory Information Config Registers
0x10001000: User Information Config Registers
0x20000000: SRAM
0x40000000: APB Peripherals
0x50000000: AHB Peripherals
0xE0000000: ARM M4 Private Peripheral Registers

NOT Configured:
0x60000000: External RAM
0x80000000: External RAM
0xA0000000: External Device
0xC0000000: External Device

NOTE: More work will be needed for future Nordic MWU (Memory
Watching Unit) support.

Signed-off-by: Michael Scott <michael.scott@linaro.org>
2017-05-28 09:18:54 -05:00
Justin Watson
145ef259c0 arch: arm: Fix SoC issues with Atmel SAM4S series.
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-28 09:18:54 -05:00
Vincenzo Frascino
68f3b71b5d arm: core: mpu: Add core support to NXP MPU
This patch add arm core MPU support to NXP MPU driver.

With this feature it is now possible to enable stack guarding on NXP
MPUs.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-28 09:18:54 -05:00
Johan Hedberg
9516d63836 Bluetooth: Remove support for NBLE
NBLE has been deprecated for a few releases now and can be removed.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2017-05-25 09:03:16 -07:00
Tomasz Bursztyka
62941365b0 arch/x86/quark_se: Let the possibility to use native SPI driver
Set the right definitions to be able to use SPI_DW instead of SPI_QMSI.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-05-19 18:52:25 -04:00
Anas Nashif
ce881890e3 arc: em7d/em9d: fix typo in soc flags
fixed typo: mnormm -> -mnorm

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-19 11:09:42 -04:00
Neil Armstrong
a9183cd518 flash: Rework and add flash device support for STM32L4x SoCs
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.

This particular controller has the following properties :
 - Up to 2 512KiB banks divided in 2KiB pages
 - Flash can be accessed in any sizes
 - Flash must be written in 64bit aligned 64bit double-words

The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.

To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-19 10:06:48 -04:00
Piotr Mienkowski
77a88da4fc arch: same70: hide soc.h defines from assembler
Neither ASF nor CMSIS provide defines that can be processed by
the assembler. Exclude those from soc.h. Before this was done
incorrectly in board.h file.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-05-19 10:06:48 -04:00
Piotr Mienkowski
ee66ee6c34 arch: sam3x: Use ASF library
This patch converts Atmel sam3x MCU series to use register
header files from Atmel Software Framework (ASF) library.
By using ASF different Atmel SAM MCU series can use common
device drivers.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-05-19 10:06:48 -04:00
Piotr Mienkowski
05d0726daf arch: atmel_sam: enhance gpio driver to support sam3x
This patch adds support for remaining Atmel SAM MCU series,
like sam3x to the common GPIO driver. After this update
full SAM MCU family should be supported by the driver.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-05-19 10:06:48 -04:00
Neil Armstrong
2ea6300f21 stm32f4: Add support for STM32F469XI
Add configuration, dtsi and memory configuration fixup for the
STM32F469XI High Performance SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-19 10:06:48 -04:00
Justin Watson
7b71d88ddd arch: arm: Convert Atmel SAM4S series MCU to use ASF
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-19 10:06:48 -04:00
Neil Armstrong
d6c8d819bd arm: stm32l4: Add configuration and dts for STM32L496
Add configuration and dts for the STM32L496 SoC STM32L4 variant.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-19 10:06:48 -04:00
Huaqi Fang
2bcd17e1af arc: Fix copyright year mistake in soc.h of arc em7d, em9d, em11d
Change 2016 to 2016-2017. I need to provide the starting date in
copyright header.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-05-19 15:58:41 +02:00
Wayne Ren
16028b5a38 arc: Fix the bug in _load_callee_saved_regs
load floating register first, or the value of r13 is not correct

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-05-19 15:58:41 +02:00
Huaqi Fang
9bc69a46fa boards: Update arc em_starterkit support from 2.2 to 2.3
Here are the main changes:
* board: Update EMSK onboard resources such as Button, Switch and LEDs
  + update soc.h for em7d, em9d, em11d
  + update board.h for em_starterkit board
* arc: Add floating point support and code density support
  + add kconfig configuration
  + add compiler options
  + add register definitions, marcos, assembly codes
  + fixes in existing codes and configurations.
* arc: Update detailed board configurations for cores of emsk 2.3
* script: Provide arc_debugger.sh for debugging em_starterkit board
  + make BOARD=em_starterkit debug
    This will start openocd server for emsk, and arc gdb will connect
    to this debug server, user can run `continue` command if user just
    want to run the application, or other commands if debugging needed.
  + make BOARD=em_starterkit debugserver
    This will start an openocd debugger server for emsk, and user can
    connect to this debugserver using arc gdb and do what they want to.
  + make BOARD=em_starterkit flash
    This will download the zephyr application elf file to emsk,
    and run it.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-05-19 15:58:41 +02:00
Andrew Boie
956089bcae xtensa: add config for toolchain version
Use TOOLCHAIN_VARIANT to indicate what XCC toolchain release
to use.

Set a reasonable default for the RG-2016.4 toolchain release.
D_108mini, D_212GP, D_233L are only in RF-2016.4, set that
appropriately.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-18 07:18:36 -04:00
Vincenzo Frascino
86aff09c77 arm: core: Integrate thread stack guard feature
This patch integrates the thread stack guard feature in the arm
Zephyr core.

Change-Id: I2022899cbc7a340be71cfaa52f79418292f93bae
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-16 09:28:06 -05:00
Vincenzo Frascino
726c7b545f arm: core: mpu: Add core MPU implementation
This patch adds the arm core MPU implementation.
This implementation currently supports the thread stack guard feature.

Change-Id: I8b3795ebaf1ebad38aaddc2ed2f05535ead2c09a
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-16 09:28:06 -05:00
Vincenzo Frascino
b94c5b16fe arm: core: mpu: Add core support to ARM MPU
This patch add arm core MPU support to ARM MPU driver.

Change-Id: I5a61da4615ae687bf42f1c9947e291ebfd2d2c1d
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-16 09:28:06 -05:00
Vincenzo Frascino
acc9fb29a3 arm: core: mpu: Add arm core MPU interface
This patch adds the arm core MPU interface, a common way to access the
pu functionalities by the arm zephyr kernel.

The interface can be divided in two parts:
- a core part that will be implemented by the arm_core_mpu driver and
  used directly by the kernel
- a driver part that will be implemented by the mpu drivers and used by
  the arm_core_mpu driver

Change-Id: I590bd284abc40d98b06fdf1efb5800903313aa00
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-16 09:28:06 -05:00
Vincenzo Frascino
adf0bf90b6 arm: soc: nxp k6x: Add Initial support for NXP MPU
This patch adds initial MPU support to NXP K6x family.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent from running code located in SRAM.

This driver has been tested on FRDM-K64F.

Change-Id: I907168fff0c6028f1c665f1d3c224cbeec31be32
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-16 09:28:06 -05:00
Andrew Boie
286a2c875f xtensa: fix XCC build
XCC doesn't recognize the "I" compiler constraint but GCC does. Switch
to "i" which is understood by both.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-15 13:33:12 -04:00
Kumar Gala
26811defc7 arm: dts: Cleanup HAS_DTS
Now that all ARM platforms have a device tree we can move selecting of
HAS_DTS up and remove any !HAS_DTS cases, as well as setting in all the
defconfigs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-05-15 13:22:54 -04:00
Florian Vaussard
cad822ab52 pinmux: stm32f4: Add pinmux for more UARTs
Add defines and pinmux arrays to support more UARTs on STM32F4.

Change-Id: Ib06c549bdb2b3d7065554a0a6d1a3d15441b29c9
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Florian Vaussard
55c477bb2c pinmux: stm32f4: Compile out unused pinmux
It is useless to include the pinmux for a peripheral if it is not
enabled in the Kconfig. This is unnecessary and it increases the size of
the binary.

Define macros that will default to void if the associated Kconfig is not
enabled.

Change-Id: I0857fcef335c75b8bb6d537fd859f93d5be4a228
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Florian Vaussard
4486ea0473 pinmux: stm32f4: Clean-up pinmux arrays
Clean-up the pinmux arrays as a preparatory work before adding more
pinmuxes.

This is achieved by the following two actions:
- Define the PAD macro to simplify the [x - 1] = y construct
- Reorder the declartions by bank / pin to make it easier to
  locate a pin among a high number of other pins, while minimizing the
  risk of conflict when two people add a new declaration for two
  different pins

Change-Id: I1ca0cc4f48bcd8cfd35b331e9821935f5c855876
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Florian Vaussard
0b9f6a25ed arm: stm32f4: Add basic support for STM32F413
Add necessary Kconfig and minimal device tree in order to support
STM32F413xH variants as found on the Nucleo STM32F413 board.

Origin: Original

Change-Id: I60230c240d6acb610f16a02c62048d448476e9c5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Kumar Gala
04c8709355 soc: stm32f3/f4/l4: gpio: Fix unnecessary else statement
The bitfield determining the I/O direction already defines the pin
as either input or output, cannot be none or both at the same time

This issue was reported by Coverity

Coverity-CID: 151970

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-05-15 13:22:54 -04:00
Florian Vaussard
b5ff4cdb6f arm: stm32f4: Do not enable USART1/USART2 by default
Not all the boards (for instance the Nuclo F412) use USART1 or USART2.
Let each board enable these USARTs when really used.

Change-Id: Idfe79c724bd7b1ab154310b4a8234b52eef2298d
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Florian Vaussard
eba1327719 soc: stm32f429zi: finish SOC renaming
Commit 87893ddf7ad4 ("soc: stm32f429zi: rename SOC config flag") renamed
SOC_STM32F429XX to SOC_STM32F429XI but the text of the option should be
changed as well to reflect this restriction in scope.

Change-Id: I2627b59f805e73d6c8a3534e0feec71a4269c9ab
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Florian Vaussard
fd5011ebf7 soc: stm32f407xg: finish SOC renaming
Commit 599149dfb831 ("soc: stm32f407xg: rename SOC config flag") renamed
SOC_STM32F407XX to SOC_STM32F407XG but the text of the option should be
changed as well to reflect this restriction in scope.

Change-Id: Id03529452f5ec7d7ffee214b152c4aa555e1208a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-05-15 13:22:54 -04:00
Erwan Gouriou
8986f33559 soc: stm32f407xg: rename SOC config flag
Rename SOC_STM32F407XX to SOC_STM32F407XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file).

Change-Id: I0afa16e86b7c99b9e685004f96beeb888f9e7568
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Erwan Gouriou
2a10920aaf soc: stm32f429zi: rename SOC config flag
Rename SOC_STM32F429XX to SOC_STM32F429XI to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)

Change-Id: Id188b7703d2bce0a3ded09132ff0f205efa9c143
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Erwan Gouriou
19a91c0272 soc: stm32l476rg: rename SOC config flag
Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)

Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-05-15 13:22:54 -04:00
Neil Armstrong
558d50242d arm: stm32l432: Switch to STM32L432XC to retain flash size
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-15 13:22:54 -04:00
Vincenzo Frascino
051da9fd4a dts: mps2_an385: Add ARM CMSDK support
This patch adds device tree support for ARM CMSDK IPs on MPS2
AN385.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
df3cec7641 dts: v2m_beetle: Add GPIO support
This patch adds the ARM CMSDK GPIO support to the V2M Beetle
device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
f906e7b099 dts: v2m_beetle: Add DualTimer support
This patch adds the ARM CMSDK DualTimer support to the V2M Beetle
device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
2fe95044c2 dts: v2m_beetle: Add Timer support
This patch adds the ARM CMSDK Timer support to the V2M Beetle device
tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
8219923c26 dts: v2m_beetle: Add WDOG support
This patch adds the ARM CMSDK WDOG support to the V2M Beetle device
tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Vincenzo Frascino
603c826fa4 dts: v2m_beetle: Generate Uart base addr
This patch enables the generation of the ARM CMSDK UART base address
from the device tree.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-15 10:51:13 -05:00
Andrew Boie
5dcb279df8 debug: add stack sentinel feature
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.

This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie
9175d20ceb arc: fix CONFIG_ARC_STACK_CHECKING
- There's no clear need to disable frame pointers if this feature is
used, remove this directive.
- The 'top' and 'base' terms are reversed. The 'base' is the high
address of the stack. The top is the lowest address, where we cannot
push further down. Fixup member and offset names to correspond to how
these terms are used in hardware documentation.
- Use correct pointers for stack top location
- Fatal exceptions now go through _NanoFatalErrorHandler to report the
faulting ip and thread.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie
174f301147 build: simplfy how extra build steps are specified
For various reasons its often necessary to generate certain
complex data structures at build-time by separate tools outside
of the C compiler. Data is populated to these tools by way of
special binary sections not intended to be included in the final
binary. We currently do this to generate interrupt tables, forthcoming
work will also use this to generate MMU page tables.

The way we have been doing this is to generatea "kernel_prebuilt.elf",
extract the metadata sections with objcopy, run the tool, and then
re-link the kernel with the extra data *and* use objcopy to pull
out the unwanted sections.

This doesn't scale well if multiple post-build steps are needed.
Now this is much simpler; in any Makefile, a special
GENERATED_KERNEL_OBJECT_FILES variable may be appended to containing
the filenames to the generated object files, which will be generated
by Make in the usual fashion.

Instead of using objcopy to pull out, we now create a linker-pass2.cmd
which additionally defines LINKER_PASS2. The source linker script
can #ifdef around this to use the special /DISCARD/ section target
to not include metadata sections in the final binary.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie
3d3d6a85df x86: remove hacks to include functions
None of this is currently necessary, the spurious interrupt
stubs and exception entry code is included in the binary just
fine. To make matters worse, some data referenced lives in the
.intList section which is completely stripped out of the binary.

If in the future we find certain essential functions are being
garbage collected when they should not be, the proper way to
mitigate this is with KEEP() directives in the linker script.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie
51df312abc xtensa: merge crt1-*.S
We had two assembly files to prepare for entry into C domain,
one intended for the simulator and one intended for real boards.

- Both files merged into a single crt1.S for either simulated or real
  targets
- Extra logic to populate command line arguments from simulator removed,
  we don't use it.
- BSS zeroing logic from crt1-boards.S used
- Reference to missing reset-unneeded.S removed
- exit() implementation moved to fatal.c, now invokes a kernel panic
  if we are not running under the simulator

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Andrew Boie
b7aa6b7bd0 xtensa: optionally build reset vector code
In real-world use-cases this isn't always needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-12 12:56:12 -04:00
Anas Nashif
f628c12b04 xtensa: rename SOC_SAMPLE_CONTROLLER
SOC_SAMPLE_CONTROLLER option name is too generic, make it Xtensa
specific to avoid confusion.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-12 07:00:04 -04:00
Andrew Boie
d26cf2dc33 kernel: add k_thread_create() API
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.

This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.

By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.

Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 20:24:22 -04:00
Anas Nashif
09b239102a xtensa: xt-sim: mark it as a board with simulator features
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-05-11 16:51:56 -04:00
Max Filippov
4b8419e420 xtensa: drop references to C library
C library is not actually used by the xtensa port, we only need the
'exit' function. Implement 'exit' in crt1-* and drop remaining
references to the C library.

Change-Id: I8a562363956b4755a6b5baee7acf3726485e5ce3
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov
0538dc1a1c xtensa: make sample_controller runnable on QEMU
Add QEMU_CPU_TYPE for the sample_controller, so that zephyr image could
be run on QEMU with sample_controller core.

Change-Id: Id9e97a43c4b7921142289dcf97ff782993ca0463
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Max Filippov
6a89999787 xtensa: use inline assembly instead of XT_* macros
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.

Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-05-11 16:51:56 -04:00
Andrew Boie
f57e79b6d5 xtensa: remove Kconfig.cores
This file is no longer used by the build system.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Andrew Boie
99c89e17e3 xtensa: fix coprocessor save area
A bad rebase of a patch that moved these defines around
unintentionally reverted a necessary change to the coprocessor
save area.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 12:47:23 -04:00
Vincenzo Frascino
255f19891a dts: mps2_an385: Initial device tree support
This patch adds the intial device tree support to V2M MPS2 AN385
platform.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-05-09 11:16:52 -04:00
Neil Armstrong
092be24061 arm: stm32l4: Add configuration and dts for STM32L432XX
Add configuration and dts for the STM32L432XX SoC STM32L4 variant.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-08 15:03:15 -04:00
fallrisk
20f41814de arch: Add Atmel SAM4S SoC support
Added support for Atmel SAM4S (Cortex-M4) MCU:
- Kconfig files
- Devicetree files

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-08 15:03:15 -04:00
fallrisk
44c421b4a3 boards: arduino_due: Added DTS to the Arduino Due.
Change-Id: I006f9d4080a1351534ede5cc601e43526c39aa83
Origin: Original
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-08 15:03:15 -04:00
Piotr Mienkowski
38d8c863d4 arm: dts: Add DTS support for SAME70 SoC
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-05-05 16:44:41 -05:00
kontais
3b0b7671a0 stm32f4/arm_mpu_mem_cfg.h compile error fix
Signed-off-by: kontais <kontais@aliyun.com>
2017-05-05 10:13:08 -05:00
Justin Watson
558281b096 arch: sam3x: update Kconfig options after move to SAM SoC family tree
The files for the Arduino Due needed to be updated to use the new
configuration when the SoC moved from the atmel_sam3 directory to
the atmel_sam/sam3x directory.

Jira: ZEP-2067

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-05-03 13:51:37 -04:00
Jon Medhurst
14ce362972 boards: mps2_an385: Enable I2C devices
The FPGA on the MPS2 board implements 4 SBCon devices for I2C which are
connected to:
- a touchscreen controller
- the audio device (for configuration)
- both shield connectors

Change-Id: I55ca985e18b45d68f5e7421c4768dfc9bf2fcb3f
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2017-05-03 13:51:37 -04:00
Adithya Baglody
d03b2496cd test: benchmarking: Timing metrics for the kernel
JIRA: ZEP-1822, ZEP-1823, ZEP-1825

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-05-03 08:46:30 -04:00
Kumar Gala
ac0bb050dd arm: dts: ti_lm3s6965: Add device tree support for Stellaris UART
Converted Stellaris UART driver over to utilize device tree generated
defines.  Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.

Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Kumar Gala
f6284cfbec arm: dts: ti_lm3s6965: Add Device Tree Support
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port.  We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.

Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:40 -05:00
Florian Vaussard
45dde7eb3f arm: stm32f4: Reorder Kconfig options
Reorder config entries alphabetically to make it easier to add new ones.

Change-Id: Ib118405a150a408638232513fba7198b458ecfa7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-04-28 15:26:39 -05:00
Kumar Gala
a22e5924b5 arm: dts: nrf: Remove !HAS_DTS Kconfig bits
Now that all the nRF based board/SoCs have device trees, we can remove
the Kconfig bits that are now coming from device tree.

Change-Id: Ia1a870a50582d4109070d2833660f58fd6f8691f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
ca3c7ec0a9 arm: dts: nrf: Add Device Tree Support for nRF51822 SoC & boards
Add device tree support for nRF51822 SoCs and Arduino 101-BLE,
Curie-BLE, BLE Nano, PCA10028-DK, and Quark-SE BLE boards. This
is minimal support for memory, flash, and UART.

Change-Id: I7e572bea537e384b6d66e520462f023ace0c9b35
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
9b30a9b308 arm: dts: nrf: Fixup nRF52840-QIAA SoC support for device tree
Fixup the nRF52840-QIAA to allow getting its SRAM & FLASH sizes from
device tree.

Change-Id: I67ecd7da5f0472402064f158030d9f97f49d7d20
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:39 -05:00
Kumar Gala
62b0750499 arm: soc: ti_lm3s6965: remove dead code
Nothing calls _ScpMainOscEnable, so lets remove it and associated files
that aren't used anymore.

Change-Id: Ibe900d039c531c4da56baa673d309ee961b09e52
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Kumar Gala
62d2d362ac arm: nxp: kl2x: Move to using UART_MCUX_LPSCI for UART0
Cleanup soc code to enable UART_MCUX_LPSCI to support UART0.

Change-Id: I173febffcffc902f228946124e0434f122a67607
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Kumar Gala
ed467a695a serial: mcux: Shim driver for LPSCI UART on KL25Z
Adds a shim layer around the mcux lpsci driver to adapt it to the Zephyr
serial interface.

Change-Id: I024f1605e3194f34bb57e8a121900e05b3085a82
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-28 15:26:38 -05:00
Erwan Gouriou
eee56a7c10 soc: stm32l4xx: add support for STM32L475XG
Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support

Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:38 -05:00
Erwan Gouriou
242ed389a3 stm32f4: Clean references to stm32f4 specific clock control
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.

Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:11 -05:00
Erwan Gouriou
80b7bec12c soc: stm32f4: Enable LL based clock control
This commit disables native stm32f4x clock control
driver and enables stm32 LL clock control driver
for stm32f4 family

Jira: ZEP-2039

Change-Id: I98ba6c89c4a3a1f39658c5808cd47a2d1f344130
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:26:11 -05:00
Erwan Gouriou
fda01e52c2 drivers: clock control: Provide LL based clock control for stm32f4 series
This commit enables STM32Cube LL based driver for stm32f4 series.
This generic driver provides a unified API to clock driver for all
stm32 series.
LL API allows driver to be lightweight and to keep genericity across
stm32 family to ease further devlopment and maintenance.

Change-Id: Ie31ae8f433313787f9c9eda77de41925721d54dd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-04-28 15:06:41 -05:00
Gil Pitney
c73a1eb806 cc3220sf: Add support for the TI CC3220SF SoC
The CC3220SF is a replacement for the CC3200 SoC, comprising
a network coprocessor and Cortex-M4 MPU.

This leverages the CC3220 SDK driver peripheral library in ROM,
and some files built from ext/hal/ti/.

Jira: ZEP-1958

Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-04-28 15:06:41 -05:00
Mazen NEIFER
51eb081311 xtensa port: Fixed crash on interrupt handlers when logger is enabled.
This fixes ZEP-1955. The issue was that the interrupt stack frame only
allocates 4 registers. This means that if any window overflow happens,
only 4 registers can be saved. This implies that the interrupt handler
can not call functions other than using call4. If this rule is not
honored, then it will result in the registers being overwriting other
context information and thus a stack corruption.

The fix consists on using call4 for calling even t logger function,
which is by the way more optimal as the interrupt handler does not need
to save more than 4 registers when these functions are called.

Issue: ZEP-1955

Change-Id: Iacea626443d1d61d95a52253ac8ff15fc3722d2c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-28 15:49:01 +00:00
Andrew Boie
8bfee13cd3 x86: define MMU data structures
This was more or less transplanted from old Viper codebase (Zephyr's
ancestor which supported paging) and adapted to current coding style.

Change-Id: I203e631f1dcd5f2fb4e9a2fa9339fc7521c7962d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-27 17:46:54 +00:00
Ramesh Thomas
89ffd44dfb kernel: tickless: Add tickless kernel support
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.

The implementation involves changes in the following areas

1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.

2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.

3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.

4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.

5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu

Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:28 +00:00
Ramesh Thomas
62eea121b3 kernel: tickless: Rename _Swap to allow creation of macro
Future tickless kernel patches would be inserting some
code before call to Swap. To enable this it will create
a mcro named as the current _Swap which would call first
the tickless kernel code and then call the real __swap()

Jira: ZEP-339
Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:26 +00:00
fallrisk
4792f363a4 arch: Moved atmel_sam3 to atmel_sam3x.
Found out that the SAM3 series is not a single series. There are actully
3 different series, 3U, 3A, and 3X.

Origin: Original
Jira: ZEP-2067

Change-Id: I61cdc826cc32dbdd25b5e6bafaada062c8ae8417
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-04-26 21:36:01 +00:00
Andrew Boie
73abd32a7d kernel: expose struct k_thread implementation
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.

On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.

Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-26 16:29:06 +00:00
fallrisk
94b44f03e1 arch: Moved Atmel SAM3 into the SAM SoC family tree.
Moved the Atmel SAM 3 from its own directory into
the directory tree laid out in arch/arm/soc/atmel_sam.

Origin: Original
Jira: ZEP-2067

Change-Id: I26a1a521dd7caa607c3e95a06cd574ee68ca59b8
Signed-off-by: Justin Watson <jwatson5@gmail.com>
2017-04-26 13:15:35 +00:00
Mazen NEIFER
e87564bd88 xtensa port: Removed XRC_D2PM SoC configuration
This SoC, in its default configuration, does not have any SW IRQ below
the EXCM level. This make it unsuitable to use irq_offload() and thus
almost untestable.

Decision was made to remove this configuration in favorof custom one
XRC_D2PM_5swIrq, which is the same core but with additional 4 SW IRQs
of level 1 and an additional timer.

Issue: ZEP-2029

Change-Id: Iee4f8346aa9d610e14898444f78d28ef0ac4cef2
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-26 09:50:44 +00:00
Vincenzo Frascino
5951e45580 soc: arm: stm32f4: Add Initial MPU Support
This patch adds initial MPU support to STM32F401XE.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent the application to access to the BootROM.
* Prevent from running code located in SRAM.

Change-Id: I4dc0669009bd5c0a829a69f8ff417c787b7043ed
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-04-25 21:53:19 +00:00
Vincenzo Frascino
b125767fdb soc: arm: beetle: Add Initial MPU Support
This patch adds initial MPU support to ARM Beetle.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent from running code located in SRAM.

Change-Id: I64f1001369896fffb0647de6be605a95161c4695
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-04-25 21:53:17 +00:00
Vincenzo Frascino
e37214062c arm: core: mpu: Add ARM MPU support
This patch adds an initial driver for the ARM MPU.
This driver has been tested on ARM Beetle and STM32F4.

Change-Id: I2bc4031961ec5a1d569929249237646f4a349f16
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-04-25 21:53:17 +00:00
Vincenzo Frascino
0974496d52 arm: core: Add MPU parameter to the arm core
This patch add the Memory Protection Unit parameter to the arm core
configuration.

Change-Id: Ifee8cdd5738391a6f182e8d0382d27eeb8c546ba
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Marc Moreno <marc.morenoberengue@linaro.org>
2017-04-25 21:53:16 +00:00
Vincenzo Frascino
8f6d874f59 arm: soc: beetle: Add regions for mpu configuration
This patch adds the regions for the mpu configuration to the soc.h file.

Change-Id: Ifd1ce96eeb4731ae01f5171924af92b9e236a3dc
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Marc Moreno <marc.morenoberengue@linaro.org>
2017-04-25 21:53:15 +00:00
Inaky Perez-Gonzalez
37f4178f58 x86: call gen_idt with $ZEPHYR_BASE too
When calling scripts/gen_idt, if we don't have $ZEPHYR_BASE/scripts in
the path, it will fail, so we can call it with its full path to avoid
such need.

Change-Id: I47b340c9f3204ad8740c29e663e12082208bb13b
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2017-04-25 02:32:29 +00:00
Mazen NEIFER
35a48decfa xtensa port: Fixed compilation error introduced by recent changes.
The error was introduced by
    b8823c4efd

Change-Id: Ibf930107a7a690e0cb0851b7c247d524e3cb89e5
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-24 20:41:46 +00:00
Christer Weinigel
89c23e1c72 soc: stm32f4xx: Document the flash latency values
Document the flash latency values by copying the relevant tables
from the reference manuals for each MCU.

Change-Id: Ieb2824ffd7634d917399e3e62146d9243b527f44
Signed-off-by: Christer Weinigel <christer@weinigel.se>
2017-04-24 20:16:29 +00:00
David B. Kinder
3561c73ece spell: Kconfig help typos: /arch
Fix misspellings in Kconfig help text and made spelling of
RX and TX consistent (from reviewer comments)

Change-Id: Ie9d4c3863cd210e7a17b50a85a7e64156b6bf3d7
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-24 20:14:53 +00:00
Christer Weinigel
73cf531975 soc: stm32f4xx: Make missing flash latency info a compile error
If the flash latency isn't set most STM32F4xx MCU's won't be able
to run from flash when the CPU frequency is changed.  Make this a
compile time error instead of an assert at runtime.

Change-Id: Ic3421194545f8f83bd6e00f0cd011306c8d1eedd
Signed-off-by: Christer Weinigel <christer@weinigel.se>
2017-04-24 20:14:13 +00:00
Kumar Gala
4f1e304f68 build: only build gen_idt on x86
Change-Id: I0401e2557c69f1e32ddedb79758c1dde781ea69b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-24 03:17:16 +00:00
Andrew Boie
75caa2b084 arm: exception-assisted kernel panic/oops support
Put the reason code in r0 and make a SVC #2 call, which will be
propagated to _fatal_error_handler as an exception.

The _is_in_isr() implementation had to be tweaked a bit.  User-generated
SVC exception no longer just used for irq_offload(); just because we are
in it does not mean we are in interrupt context.  Instead, have the
irq_offload code set and clear the offload_routine global; it will be
non-NULL only if it's in use. Upcoming changes to support memory
protection (which will require system calls) will need this too.

We free up some small amount of ROM deleting _default_esf struct as it's
no longer needed.

Issue: ZEP-843
Change-Id: Ie82bd708575934cffe41e64f5c128c8704ca4e48
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Andrew Boie
7827b7bf4a x86: exception-assisted panic/oops support
We reserve a specific vector in the IDT to trigger when we want to
enter a fatal exception state from software.

Disabled for drivers/build_all tests as we were up to the ROM limit
on Quark D2000.

Issue: ZEP-843
Change-Id: I4de7f025fba0691d07bcc3b3f0925973834496a0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Andrew Boie
cdb94d6425 kernel: add k_panic() and k_oops() APIs
Unlike assertions, these APIs are active at all times. The kernel will
treat these errors in the same way as fatal CPU exceptions. Ultimately,
the policy of what to do with these errors is implemented in
_SysFatalErrorHandler.

If the archtecture supports it, a real CPU exception can be triggered
which will provide a complete register dump and PC value when the
problem occurs. This will provide more helpful information than a fake
exception stack frame (_default_esf) passed to the arch-specific exception
handling code.

Issue: ZEP-843
Change-Id: I8f136905c05bb84772e1c5ed53b8e920d24eb6fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Andrew Boie
3b662555d1 arm: work around QEMU issue with _IsInIsr
The ICSR RETTOBASE bit is improperly implemented in QEMU (the polarity
is flipped) and the fix for it has not yet made it into a QEMU release,
although it is present in upstream master branch.

The symptom is that if we are not in thread mode, the system always
believes were are in a nested exception state, causing _IsInIsr() to
always return true.

Skip the nested exception check if we are building for QEMU.

This is a workaround until SDK-54 is resolved.

Issue: SDK-54
Change-Id: I06eafcc85fb76a9b23b4ba85ed6e111a08516231
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 01:08:27 +00:00
Andrew Boie
e09a04f068 arm: fix exception handling
For exceptions where we are just going to abort the current thread, we
need to exit handler mode properly so that PendSV can run and perform a
context switch. For ARM architecture this means that the fatal error
handling code path can indeed return if we were 1) in handler mode and
2) only wish to abort the current thread.

Fixes a very long-standing bug where a thread that generates an
exception, and should only abort the thread, instead takes down the
entire system.

Issue: ZEP-2052
Change-Id: Ib356a34a6fda2e0f8aff39c4b3270efceb81e54d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 01:08:07 +00:00
Kumar Gala
96ee45df8d kernel: refactor thread_monitor_init into common code
We do the same thing on all arch's right now for thread_monitor_init so
lets put it in a common place.  This also should fix an issue on xtensa
when thread monitor can be enabled (reference to _nanokernel.threads).

Change-Id: If2f26c1578aa1f18565a530de4880ae7bd5a0da2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
Kumar Gala
b8823c4efd kernel: Refactor common _new_thread init code
We do a bit of the same stuff on all the arch's to setup a new thread.
So lets put that code in a common place so we unify it for everyone and
reduce some duplicated code.

Change-Id: Ic04121bfd6846aece16aa7ffd4382bdcdb6136e3
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
Kumar Gala
5742a508a2 kernel: cleanup use of naked unsigned in _new_thread
There are a few places that we used an naked unsigned type, lets be
explicit and make it 'unsigned int'.

Change-Id: I33fcbdec4a6a1c0b1a2defb9a5844d282d02d80e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:41 +00:00
Kumar Gala
cc334c7273 Convert remaining code to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies.  We also convert the PRI printf formatters in the arch
code over to normal formatters.

Jira: ZEP-2051

Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 11:38:23 -05:00
Tomasz Bursztyka
9f3bdcedf7 arch/arc/soc: If IOAPIC is not enabled, gpio_dw should still compile
Irq flags should be set to 0.

Change-Id: I7c5104c0dc89ba79789a263649422f51a556f218
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-04-21 16:34:54 +00:00
David B. Kinder
36bb36475f spell: fix Kconfig help typos: /arch
Fix misspellings in Kconfig help text

Change-Id: I2a753b57107f09073eb84ac757ac1e180ae89349
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-21 12:30:42 +00:00
Kumar Gala
bf53ebf2c8 arch: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 12:08:12 +00:00
Kumar Gala
789081673f Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t.  This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.

We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.

We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.

Jira: ZEP-2051

Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-20 16:07:08 +00:00
Mazen NEIFER
01e9646638 xtensa port: Clear the CP descriptor of new created thread.
This commit should fix the concern about uninitialized memory of main
thread that was raised in https://gerrit.zephyrproject.org/r/#/c/12920/

The issue is more general, if it happens that the content of the
CPENABLE flag of any thread is set then any other thread using the CP
may cause a memory corruption.

I'd prefer to avoid the issue by initializing the CP descriptor to 0.
The descriptor itself is few words. We set them to 0 up to CP_ASA, which
is set to a real value.

As the dummy thread instantiated at the kernel startup does not use CP,
there is no CP area in its thread memory buffer. However it is mandatory
that it have the CP descriptor and that cpEnable in that descripot is
set to null. This is ensured by adding XT_CP_DESCR_SIZE to
_K_THREAD_NO_FLOAT_SIZEOF.

Change-Id: I6a36b5b363600ea1e6d98ab679981182b2b5a236
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-20 16:01:55 +00:00
Max Filippov
59926490be xtensa: move #include <linker/common-*.ld> up
Move linker/common-rom.ld between .rodata sections so that it's together
with other immutable data.
Move linker/common-ram.ld before the .bss section, so that .bss does not
appear between data sections, which had two consequences:
- there's a .bss-sized gap in the ELF image, and
- PHDR segment that covers .bss overlaps the segment that covers .data,
  resulting in the following xt-run warning:

  ( [ sample_controller ] load_bfd ) *WARNING* Executable segment
    [ 60004d60, 600079a7 ] overlaps an existing executable segment

Change-Id: I2db46f4656e240016fe60883057cc000b6377180
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-20 16:01:18 +00:00
David B. Kinder
690c5be381 spell: fix doxygen comment typos: /arch
Fix doxygen comment typos used to generate API docs

Change-Id: I94df2e3a2bda248824ed2aeff3dd0eb743f0bf3e
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-19 18:38:43 +00:00
Anas Nashif
8df439b40b kernel: rename nanoArchInit->kernel_arch_init
Change-Id: I094665e583f506cc71185cb6b8630046b2d4b2f8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-19 10:59:35 -05:00
Kumar Gala
fded58d2af Revert "arch: Convert formatter strings to use PRI defines"
This reverts commit da8bff6b20.

We revert this as we intent to move away from {u}int{8,16,32,64}_t types
to our own internal types for sized variables so we shouldn't need the
PRI macros anymore.

Change-Id: Ibb1fae7500bddb4772b8830d497a0e5f78b44bcc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 10:50:51 -05:00
Kumar Gala
da8bff6b20 arch: Convert formatter strings to use PRI defines
To allow for various libc implementations (like newlib) in which the way
various {u}int{8,16,32}_t types are defined vary between both libc
implementations and across architectures we need to utilize the PRI
defines.

Change-Id: Ic4e65db52c8d693228cf80584283d4d06e68b5ad
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-17 11:09:36 -05:00
Piotr Mienkowski
929c159262 drivers: Extend Atmel SAM GPIO driver
Add soc_gpio_get(), soc_gpio_debounce_length_set() functions to Atmel
SAM soc_gpio driver.

Change-Id: I541c6fead9a308dd2e67c59dabe67b87cf1628ef
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-14 05:56:54 -05:00
Piotr Mienkowski
34c16ad2f7 drivers: Add Atmel SAM serial (UART) driver
Added serial (UART) driver for Atmel SAM MCU family.

Note:
- Error handling is not implemented
- The driver works only in polling mode, interrupt mode is
  not implemented.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-1959
Change-Id: I3e770fd1feb2ddf92cf405a9aa17be92eb32e19b
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-14 05:56:54 -05:00
Piotr Mienkowski
5c83e3817d drivers: Add Atmel SAM family I2C (TWIHS) driver
Added I2C bus (TWIHS) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-1866
Change-Id: Ic5aa7b6b21295feccae883d580b38bbeaf2ce291
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-14 05:56:54 -05:00
Kumar Gala
77f65b907f arm: dts: Add DTS support for NRF52832 SoC
Add plumbing to build system and SoC level dtsi for the NRF52832 SoC.
We additionally add the necessary yaml files for the UART on the NRF52
SoCs.

Change-Id: I3b4a821b2993827e33d8e84bdbbc759d1521f8bd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:54 -05:00
Kumar Gala
6959c4516e arm: nrf52: Introduce NRF52 SoC Specific config options
Introduce SoC specific config options similar to what exists on NRF51,
this is mostly to help distinguish between SRAM & Flash sizes on
different variants.

Also deleted some unnecessary setting of CONFIG_SOC_NRF528{32,40} in the
board defconfig files.

Change-Id: I3aaedf0c15423ae12636f87b8e6a39070cbb2c6f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:54 -05:00
Maureen Helm
f487b208dd kw40z: Add kw40z SoC
Adds initial support for the kw40z SoC. This SoC has all the same
peripherals as the kw41z but with less flash and ram, so the defconfig
and dts are nearly the same.

Jira: ZEP-1388
Change-Id: Ib804451e8c2c71c4ff7d342bf23f6567d1542a2d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-04-14 05:56:53 -05:00
Kumar Gala
b0ae518933 arm: nxp: kl2x: remove HAS_DTS references
The KL2x support requires DTS so we can remove any !HAS_DTS references.
Also NUM_IRQS shouldn't have been in a !HAS_DTS ifdef block.

Change-Id: I12b0781b6eef100bfb0a94698d12fc519c759888
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Kumar Gala
4d5dcb1916 arm: st: dts: remove last !HAS_DTS from stm32 SoCs
Since all STM32 SoCs are using device tree we can remove this last bit
of !HAS_DTS for getting flash/sram sizes from Kconfig.

Change-Id: I9e706b7aba7c0edcf9fca3ddc0ddc7d820980b47
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Kumar Gala
fd733ca8f1 arm: dts: st: Convert STM32F3 based boards to dts
Converted over all STM32F3 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F3.

Boards that are now using devicetree:
* Nucleo f334r8
* STM32373C Eval

Change-Id: I081a1d83f86e417a98b6864c745354b6b32953b7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Kumar Gala
51ccb58dbb arm: dts: st: Convert STM32F1 based boards to dts
Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1.  Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder.  Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.

Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15

Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Kumar Gala
38cda7f813 arm: dts: st: Convert STM32F4 based boards to dts
Converted over all STM32F4 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F4.

Boards that are now using devicetree:
* 96b_carbon
* nucleo f401re
* nucleo f411re

Change-Id: Ibe197ca0a3f5ad78d594485a578d986403cc824a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Kumar Gala
df21ab8541 dts: arm: ST: Cleanup DTS bits on STM32L4 SoCs
Since all the L4 SoCs are using DTS we can remove the various Kconfig
bits that we now get from DTS.

Change-Id: Icdec49b478ff285dc3347b09412964a721f75bbf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-14 05:56:53 -05:00
Gustavo Denardin
32e15637af arm: Support for MKL25Z soc
In order to suppport the FRDM-KL25Z board,
it is necessary to make this soc available.

Change-Id: Id93a51dcc9ef58118e27db02c30f662eb73d5adb
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
2017-04-14 05:56:53 -05:00
Piotr Mienkowski
a8de9ff438 drivers: i2c: rename IRQ SHARED/DIRECT Kconfig options
I2C_SHARED_IRQ, I2C_0_IRQ_SHARED, I2C_0_IRQ_DIRECT Kconfig options
are DW driver specific. Its presence is confusing for a user of any
other I2C driver than DW. This patch renames these options to include
DW string and makes it visible only for DW I2C driver. This is a
similar implementation to that used by ETH DW Ethernet driver.

Change-Id: I795506f9b103c028a22317df9ad632dce5cd1343
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-14 01:58:33 +00:00
David Brown
0c476a58b7 misc: Generalize LOAD_OFFSET support
Instead of FLASH_LOAD_OFFSET being something specific to cortex-m, add
it generally to misc/Kconfig, along with a hidden config
HAS_LOAD_OFFSET which can be selected by the architectures as they add
support for the functionality.

Change-Id: I256ff8cf4e9b8493b26354c3b93fe1f7017d4887
Signed-off-by: David Brown <david.brown@linaro.org>
2017-04-14 01:35:59 +00:00
Max Filippov
a0fa4f3265 xtensa: use -mlongcalls instead of --longcalls
gcc only understands -mlongcalls form of this option, xcc understands
both. Use -mlongcalls for building with both xcc and gcc.

Change-Id: I93f65ccbc97429ae564f1986120b37ce205ee38c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-04-13 20:33:28 +00:00
Mazen NEIFER
a6e0404983 xtensa port: Fixed crash on startup on CP enabled cores
The issue was that cpStack was changed to a memory buffer by commit
https://gerrit.zephyrproject.org/r/#/c/12816
However the assembly code was expecting it to be a pointer and thus
issuing an indirection, that leads to wrong addresses.

The fix removed this unnecessary indirection and thus the inherent
invalid memory access exception.

Issue: ZEP-1997
Change-Id: I843f049212f2d116a01b05367a284209f463a5e7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-13 11:54:49 -07:00
Andrew Boie
11ee791b32 xtensa: build similar to other Zephyr arches
* CONFIG_SOC is now properly set and we do not need a separate
  XTENSA_CORE build variable

* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed

* There is no default SOC selection, it is now done explicitly in
  the board's defconfig

* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
  uppercase> to conform to established style.

Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-13 12:42:06 +00:00
Andrew Boie
b037d4d54c xtensa: fix tickless idle build
_power_save_idle_exit() was removed long ago. All arches now just
call _sys_power_save_idle_exit() if PM is enabled.

Change-Id: I9cce3eecc8cbf1cbce15a355be420e747fb978de
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-12 16:31:46 +00:00
Luiz Augusto von Dentz
0dc022f7fa x86: Increase RAM_SIZE to 256K
When running with qemu often times the developer want to enable all
sorts of debugs which end up not working with only 192K.

Change-Id: I8d784618b9a0d911944f831a4058b34abc0c3e35
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2017-04-11 16:43:22 +03:00
Anas Nashif
50553dd700 debug: rename variable CONFIG_GDB_RAM_SIZE
CONFIG_* usually come from Kconfig, rename variables that are locally
defined to avoid confusion about where they are set.

Change-Id: I402713e6f852907e75be4bc2b916a7d15dd5649c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-11 03:14:24 +00:00
Anas Nashif
fdd045b52b kconfig: rename non-Kconfig CONFIG_* variables
CONFIG_* usually come from Kconfig, rename variables that are locally
defined to avoid confusion about where they are set.

Change-Id: I83b8459913c5deb68dc1b9f5386b8934363a6d1f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-11 03:14:23 +00:00
Mazen NEIFER
cc8ffbdb44 Xtensa port: Moved coporcessor context area inside struct _k_thread
The CP context area was before on the bottom of the stack just
after the thread descriptor. Now it is moved inside the thread
descriptor to support some kind of memory protection.

Change-Id: Id3ebeaecfd9c2475899713fdc8da583a1f9121f9
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-04-11 00:05:27 +00:00
Anas Nashif
b84dc2e124 kernel: remove all remaining references to nanokernel
Change-Id: I43067508898bc092879f7fe9d656ccca6fd92ab2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:10 +00:00
Anas Nashif
d7bc60f096 kernel: remove remaining microkernel references
Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:05 +00:00
Piotr Mienkowski
f33b277e6f drivers: i2c: rename I2C_CLOCK_SPEED Kconfig option
I2C_CLOCK_SPEED Kconfig option is DW driver specific. It does not
define I2C interface speed but rather the I2C DW module clock speed.
It is confusing for a user of any other I2C driver than DW.
This patch renames this option to I2C_DW_CLOCK_SPEED and makes it
visible only for DW I2C driver.

Change-Id: I97f57332fd5cca644eabdef0968a0b2174b885ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-08 00:12:29 +00:00
Andrew Boie
bf902e6b95 x86: add a more informative page fault handler
This is only built in if CONFIG_EXCEPTION_DEBUG is turned on.

Change-Id: I91f0601e344919f3481f7f5e78cb98c6784d1ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-06 21:18:28 +00:00
Piotr Mienkowski
88eb813e73 arch: Atmel SAM E70: remove now redundant IRQ id defines
same70/soc.h provided IRQ ids as #define. This is no longer
necessary as gen_isr_tables mechanism, which was recently
introduced, supports IRQ ids as enums. These are provided
directly by Atmel ASF library.

Change-Id: I3c2573d97d81eb9a02e85fde0566622ff2ecf2cf
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-05 16:31:27 +00:00
Jon Medhurst
c27d1c88b4 mps2: Add defines and devices for FPGA system control block
These are fixed I/O registers for getting and setting the states of
LEDs, buttons, SPI chip-selects, and LCD control lines. It also contains
several free-running counters with no specific use.

Change-Id: Ib49306d5501574f7eb354165cdca6f29e3d4dad4
Signed-off-by: Jon Medhurst <tixy@linaro.org>
2017-04-04 17:55:13 -05:00
Kumar Gala
117f24f458 arm: dts: Remove !HAS_DTS Kconfig bits
For the SoCs in which all the boards for that platform are using dts we
can remove the Kconfig bits that are now coming from device tree.

Change-Id: Iccf4c84beb83fa1c516b6166f94de37b4a0162ae
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-04 17:55:13 -05:00
Gil Pitney
9b12803bf7 cc3200: Resolve DTS fixup.
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.

This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.

Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.

Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-04 17:55:12 -05:00
Kumar Gala
ffd7c9f696 dts: Remove num-irqs from the arm nvic node
Move back to getting the number of IRQs from Kconfig.  We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.

Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-04 17:55:12 -05:00
Andrew Boie
5c9f7e28a1 xtensa: remove legacy kernel cruft
fibers/tasks are now just threads and we should not be using
struct *tcs any more.

Change-Id: Iee5369abcc66b4357a0c75537025fe8edb0ffbb4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-03 16:40:48 +00:00
Jean-Paul Etienne
4ae030c7b8 riscv32: added support for the SiFive Freedom E310 SOC
The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.

It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)

Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-04-02 15:15:07 +00:00
Vincenzo Frascino
bb9c8df891 arm: core: Update core to use struct k_thread
This patch updates the ARM core to use struct k_thread instead of struct
tcs. Struct tcs has been deprecated with Zephyr 1.6.

Change-Id: I1219add0bbcca4b963ffe02cd4519eca355c7719
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-03-30 18:31:05 +00:00
Maureen Helm
aa9c14667b ext: mcux: Update to mcux 2.2 for k64
Updates the mcux drivers and device header files for the k64 from mcux
2.1 to mcux 2.2. Updates the k6x soc init and ethernet shim driver to
reflect mcux interface changes.

Origin: NXP MCUXpresso SDK 2.2
URL: mcux.nxp.com
Maintained-by: External

Change-Id: Icb578dddbe84c190e990b756193bef621010a898
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-03-27 09:05:58 -05:00
Florian Vaussard
9b6140eafc arm: stm32f4: Add FPU support
The Cortex-M4 of the STM32F4 family has an FPU. Enable the FPU support
by selecting CPU_HAS_FPU.

Change-Id: Iddae9c547df6e010562649eb0997dc61563c8fc4
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-03-27 09:05:57 -05:00
Florian Vaussard
0601d8ad2b arm: stm32f4: Fix comment in Kconfig
The comment refers to STM32F1 instead of STM32F4.

Change-Id: Ide116b712146f87a6f4d2aaafea8bd181c4d9397
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-03-27 09:05:57 -05:00
Florian Vaussard
632a07d987 gpio: stm32: Use atomic set/reset in stm32_gpio_set()
The current implementation of stm32_gpio_set() uses the GPIO output data
register to change the state of individual GPIOs. The generated
assembler needs at least 3 instructions: load / modify / store.

This opens a small race window, for example if a thread and an
interrupt both try to change the state of the same GPIO bank.

Use the GPIO bit set/reset register to perform the atomic change without
locking.

This also has the benefit of a more optimised implementation, which can
be useful for GPIO-intensive work. Compare the new version:

08000c98 <stm32_gpio_set>:
 8000c98:       f001 010f       and.w   r1, r1, #15
 8000c9c:       2301            movs    r3, #1
 8000c9e:       b902            cbnz    r2, 8000ca2 <stm32_gpio_set+0xa>
 8000ca0:       3110            adds    r1, #16
 8000ca2:       408b            lsls    r3, r1
 8000ca4:       6183            str     r3, [r0, #24]
 8000ca6:       2000            movs    r0, #0
 8000ca8:       4770            bx      lr

and the old one:

08000c98 <stm32_gpio_set>:
 8000c98:       2301            movs    r3, #1
 8000c9a:       f001 010f       and.w   r1, r1, #15
 8000c9e:       fa03 f101       lsl.w   r1, r3, r1
 8000ca2:       6943            ldr     r3, [r0, #20]
 8000ca4:       b10a            cbz     r2, 8000caa <stm32_gpio_set+0x12>
 8000ca6:       4319            orrs    r1, r3
 8000ca8:       e001            b.n     8000cae <stm32_gpio_set+0x16>
 8000caa:       ea23 0101       bic.w   r1, r3, r1
 8000cae:       6141            str     r1, [r0, #20]
 8000cb0:       2000            movs    r0, #0
 8000cb2:       4770            bx      lr

Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
2017-03-27 09:05:57 -05:00
Kumar Gala
83d8ffb2a0 spi: mcux: Rename spi driver to DSPI to match naming convention
In prep for supporting the older KL2x SoCs that use a different SPI
block, rename the current SPI driver to DSPI to match what the MCUX HAL
defines it as.

Change-Id: I9097580df5fca649ab6fd9a38212fced0b1ea6ed
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-03-27 09:05:57 -05:00
Yannis Damigos
fedf497b03 olimexino_stm32: Enable DT usage for OLIMEXINO STM32
This patch adds the necessary changes to enable use of DTS for
generating required build information.

Change-Id: I0d7aa15488339a425ffe57b6354992851212f7f3
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-03-27 09:05:57 -05:00
Gustavo Denardin
5295191b28 arm: IRQ number correction in the soc configuration
The previous file contained erroneous values of the number of IRQs
in these socs.

Change-Id: Ie7d2c19d86e247599f4924b95d9330175140d894
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
2017-03-27 09:05:57 -05:00
Carles Cufi
b4aff7dc79 arch: nrf5x: Define additional compiler macros
The current nordic hal layer in ext/ requires additional macros to
include the correct files. This will be corrected in an upcoming version
of the hal layer itself but for now add the required macros so that
users can benefit from the hal peripheral code.

Change-Id: I95127d0a98d7e882fdc779f961718fa223d504eb
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2017-03-21 13:38:59 +00:00
Jean-Paul Etienne
4b8ae8863c riscv32: riscv-privilege: Platform-Level Interrupt Controller support
Updated the riscv-privilege SOC family to account for SOCs supporting
a Platform-level Interrupt Controller (PLIC) as specified by the
riscv privilege architecture.

riscv-privilege SOCs supporting a PLIC have to implement the following
list of APIs:
void riscv_plic_irq_enable(uint32_t irq);
void riscv_plic_irq_disable(uint32_t irq);
int riscv_plic_irq_is_enabled(uint32_t irq);
void riscv_plic_set_priority(uint32_t irq, uint32_t priority);
int riscv_plic_get_irq(void);

Change-Id: I0228574967348d572afc98a79257c697efc4309e
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-20 23:19:36 +00:00
Jean-Paul Etienne
d1bd80a4a9 riscv32: added the riscv-privilege SOC_FAMILY
added the riscv-privilege SOC_FAMILY, under which all
riscv SOCs supporting the riscv privilege architecture
specifcation shall reside. These SOCs shall notably have
a common base for handling IRQs.

Moved riscv32-qemu under the riscv-privilege SOC_FAMILY

Change-Id: I5372cb38e3eaed78886f22b212ab4f881ef30b3f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-20 23:19:35 +00:00
Paul Sokolovsky
70772add28 arch/arm/core: In comments, consistently refer to "Cortex-M".
This directory now handles all of Cortex-M0, Cortex-M3/M4. So, just
consistently use "Cortex-M" (as used by number of files already)
without refering to a particular subarch. Also, consistently (letter
casing) spell it as "Cortex-M". A typo is fixed too.

Change-Id: I42ee09abc9a503381bca4ae437c83a8f48816ebc
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2017-03-13 12:53:46 +00:00
Anas Nashif
e5d1d18415 quark_se_ss: disable x86 GPIO driver by default
Change-Id: Iba35765b1500241fef62f947343ae40a16e6c443
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-03-09 14:53:17 +01:00
Souvik K Chakravarty
f98cb40179 soc: defconfig: Enable WDT for ATMEL SAM MCUs
In Atmel SAM Family of MCUs, the watchdog is enabled by default at boot.
The watchdog once disabled, cannot be re-enabled back without a reset.
Hence disabling the Watchdog needs to be handled via the Watchdog driver.

Tested on Atmel SAMV71 Xplained Ultra Evaluation Kit.

Jira: ZEP-1684

Change-Id: I5682c3f007a846b064b8d16abf0d9b67d4c8e7d6
Signed-off-by: Souvik K Chakravarty <souvik.k.chakravarty@intel.com>
2017-03-09 13:43:18 +00:00
Anas Nashif
b08d655286 quark_se: do not enable x86 SPI on ARC
Change-Id: I0583a181fc59ec14f8dbad62722f58a3c7d03390
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-03-09 10:05:38 +00:00
Andrei Emeltchenko
b973f987d8 quark_se: Fix Bluetooth settings for NBLE
Enable UART_QMSI_0 whenever NBLE is enabled the same way as it is done
for BLUETOOTH_H4.

Change-Id: Ib2f76f7e5e95620d40320891fec1b86509d1856e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2017-03-07 11:17:19 +00:00
Jean-Paul Etienne
6671911f81 riscv32: fixed build warnings for obj_tracing
Issue: ZEP-1851
Change-Id: I9c3455b3eb14d3b85bdb02827c5fc31c7338c572
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-06 21:57:53 +01:00
Andrew Boie
3cc4d41438 ipm_console: add Kconfig for receiver stack size
Change-Id: I27c1189e3bf87b4ea3dc06d38f63cab21663697b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-03-06 16:58:20 +00:00
Bogdan Davidoaia
65a029cb05 kinetis: fix Kconfig indentation
Help text in Kconfig files should be indented with <tab><space><space>.

Change-Id: Iefa5c8f4bfe329b4ee754ebfe43766f445432184
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
2017-03-02 14:13:29 +00:00
Bogdan Davidoaia
b2fddf3976 kw41z: enable TRNG driver
Change-Id: Iae4ad82d359a2195ea4ab9a7a6e329c38276cdfa
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
2017-03-02 14:13:29 +00:00
Bogdan Davidoaia
5473906993 random: add MCUX TRNG driver
Provide a random driver wrapped around the MCUX TRNG driver.

Change-Id: Icbd7ab587aa18ecbd7eae52290aaa5d8ee504cf2
Origin: Original
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
2017-03-02 14:13:27 +00:00
Bogdan Davidoaia
50cb5a6bd3 random: mcux: rename random_mcux to random_mcux_rnga
MCUX contains more than one type of random number generator,
so refrect this in config and file names.

Change-Id: Iba4482a1ae41f35d471686f8b159c113147c4df8
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
2017-03-02 14:13:25 +00:00
Andy Ross
419fc7d473 quark_se: Fix bluetooth UART dependency
Fix c6e27a05 was too aggressive.  It turns out that bluetooth on the
Quark SE boards won't enable it's own UART, because it had always been
enabled.  Apps that don't do it already will be broken.

Enable UART_QMSI_0 whenever BLUETOOTH_H4 is pulled in on this
platform.

Change-Id: I5e21c6004714adba8fb0fafa056dc2d62698a3d1
Issue: ZEP-1788
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2017-03-02 00:33:58 +00:00
Anas Nashif
ac27101f64 quark_se: arc: do not enable second I2C by default
Change-Id: Ib76edbcfd050cbf04f60aa48125117550b460195
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-02-23 13:20:38 +00:00
Jorge Ramirez-Ortiz
29a8e0292e flash/stm32: driver for STM32F4x series
Change-Id: I0f90bcda7a694de81c594a6616da0faf40306702
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2017-02-22 18:08:57 -06:00
Erwan Gouriou
d39eedbad1 arch: stm32: provide tick to Cube HAL
Cube HAL implements timeout based on 1ms tick.
This commit allows Cube HAL to get Zephyr system clock.

Change-Id: I9a59edcf6fa8e0ebfd5040348db537dadd9fcdfa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-22 18:08:57 -06:00
Gustavo Denardin
3fdfcfc94f arm: Support for new STM32F4 socs (STM32F407 and STM32F429)
In order to support the discovery STM32F4 and STM32F429 boards,
it is necessary to make these socs available.

Change-Id: I351d294fb02c4385f291a6e258a3f7d81e85627e
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
2017-02-22 18:08:57 -06:00
Marti Bolivar
bf2d34ba30 arm: cortex-m: allow configurable ROM offset
Currently, ARM Cortex-M image ROMs are linked starting at the flash
device's base address (CONFIG_FLASH_BASE_ADDRESS). This prevents XIP
Zephyr applications from being linked to run from elsewhere on the
flash device. Linking Zephyr applications to run from elsewhere can be
necessary when running under a bootloader (i.e., booting into a Zephyr
application from a bootloader, not using Zephyr as a bootloader).

To enable this use case, add a new config option: FLASH_LOAD_OFFSET.
This option directs the linker to treat ROM as if it started that many
bytes from the base of flash on Cortex-M targets. The option defaults
to zero to preserve backwards compatibility.

Change-Id: I64f82aee257c19c2451f9789b0ab56999775b761
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-02-22 18:08:57 -06:00
Andy Ross
c6e27a05c2 quark_se: Don't enable UART 0 always
The defconfigs would always create a device for UART 0, which is
problematic in circumstances where both the x86 and ARC cores are
alive and one wants to use it in a non-default configuration.

Specifically: on Arduino 101 this is the bluetooth device and it
operates at 1MBps instead of of 115200kbps.  If an x86 app sets this
up correctly, but then starts the ARC core running an app which
doesn't reference this UART at all, the device will still exist and
set up the (wrong!) configuration, clobbering the correct settings.

Just remove the "def-bool y" bits from the defconfig.  There's no
need, users of these devices (e.g. the console) will enable them
anyway.  There's no value to compiling it in without a configured
user.

Issue: ZEP-1677
Change-Id: I4a0e944f23705495433e9f3d0459065f131579cb
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2017-02-22 22:42:25 +00:00
Anas Nashif
fe118c4e95 license: replace APL2.0 license with SPDX
Some files made it through review process with full license header.

Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-02-20 16:59:46 +00:00
Jean-Paul Etienne
be856d4b13 riscv32: riscv32-qemu: provide a more generic way of filtering IRQs from exceptions
Currently, if IRQ number != RISCV_MACHINE_TIMER_IRQ (only device IRQ in qemu),
riscv32-qemu was considering the IRQ as an exception. However, fake IRQs
can also be generated by setting corresponding bits in the Machine Interrupt
Pending register (mip). With the current implementation, these IRQs were
considered as unexpected exceptions.

To circumvent the problem, update the IRQ filtering mechanism by considering
an IRQ (IRQ number as reported by the mcause register) as an exception only
if its corresponding bit is NOT set in the mip register.

Change-Id: I4c581a84d83ee0ba2c4ea35f89ba732401eb8fa4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-16 17:33:02 +00:00
Chuck Jordan
ae15a26751 arc: add _tsc_read for 64-bit timestamp
This implementation of _tsc_read returns a 64-bit value that
is derived from the 64-bit tick count multiplied by hwcycles per tick,
and then it adds the current value from the 32-bit timer.
This produces a 64-bit time. There is a bunch of math here, which
could be avoided if the CPU is built with Real-Time-Clock option.
EM Starter Kit SOCs don't have this. I don't think Arduino 101 does
either.

See ZEP-1559

Change-Id: I9f846d170246556ac40fe2f45809e457c6375d8c
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2017-02-15 05:55:09 +00:00
Andrew Boie
35fcb2736c arc: enable gen_isr_tables mechanism
Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:54:47 +00:00
Andrew Boie
3944d8313e gen_isr_tables: apply offset to irq parameter
The interrupts would be placed at incorrect offsets on systems where
some interrupt vectors are reserved for exceptions, such as ARC.

Change-Id: I5b1f00eb9e8aecb84ae66e3d0461a734ffb5fbe6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:19 +00:00
Andrew Boie
bd69c3bdf0 riscv32: enable gen_isr_tables mechanism
Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Andrew Boie
b2e136c5f0 gen_isr_tables: make vector offset a hidden option
If this is set incorrectly things will break all over the place.
Needs a default defined per-arch and left alone.

Change-Id: I3f8c842937a240297ee21589a22a7a9e51dbdfad
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-15 04:49:17 +00:00
Anas Nashif
15a6598691 Merge "Merge remote-tracking branch 'origin/core'" 2017-02-15 04:33:25 +00:00
Richard Peters
bab3aafa2d qemu_cortex_m3: fixed network connectivity
The wrong UART was set on for the qemu_cortex_m3 slip (uart pipe) device

Change-Id: If6d6af0f32ef02ccc559cd1fff90ea499cc378c4
Signed-off-by: Richard Peters <mail@richardpeters.de>
2017-02-15 01:36:27 +00:00
Jean-Paul Etienne
d0a33869a5 riscv32: move riscv privileged architecture specifics within a common header file
Added a riscv-privilege.h header file that contains common
definitions for all riscv SOCs supporting the riscv
privileged architecture specification.

This shall ease addition of future riscv SOCs supporting
the riscv privileged architecture spec.

Change-Id: I5714bf70eeda738a25967ed26d3d0d2aaa0c9989
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-14 05:23:14 +00:00
Andrew Boie
42562b9367 xtensa: fix numerous checkpatch issues
Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER
fb5299cd4a Xtensa port: Removed trailing spaces and unused macros. Reformatted comments.
Change-Id: I7f3fcba5d78c153c9b2830982e3ed6d5a1150c78
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:03 -08:00
Mazen NEIFER
ff0828faf3 Xtensa port: Fixed compilation errors caused by last rebase on master.
Change-Id: If2896bcce26652ded2059a11620370e34f98d1e4
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER
74ff1092d4 Xtensa port: Prevent preemption of locked threads.
When an IRQ is serviced, the ISR dispatcher will check for any new thread in
the ready queue and switch to it. However, if the current thread is marked as
non preemptable due to _kernel.current->base.preempt > _NON_PREEMPT_THRESHOLD
then we should not switch to another one.

Change-Id: Icdc08105cc6433da479bb95265710462a0f37c0b
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
53f66d0bf7 xtensa: remove nonexistent offset
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
de099439b1 xtensa: fix build warning if no coprocessors present
Change-Id: Ib754795eff073500a38e4b383268b4f90c1763a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER
3b95e3d729 Xtensa port: Added support for sample_controller core and set is as default.
This core is not depreciated and compilationfor it is even faster than D_233L.

Change-Id: I6b8149ca9e879770c3ed0973ffb9304e2e3c8d8d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
9249f876a9 xtensa: cleanup fatal error handling
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.

2) The human readability of the exception errors is improved.

Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER
b06115aa7c Xtensa port: Fixed memory corruption in interrupt handler exit function.
The a3 register was supposed to hold the _thread pointer but it seems that it
does not in all cases. Safe to restore it from _kernel structure.

Change-Id: Ie2ff6c3faf0fe70de4c5877ab59433d0c165145b
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:01 -08:00
Mazen NEIFER
884005673c Xtensa port: Set Swap function result to -EAGAIN.
Change-Id: I70a651012d5da873c98f6b13ada5e80e67e18e0c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
51efd6d4dc Xtensa port: Moved coprocessor stack area on bottom of stack, just after TCS.
This change should allow threads that do not access coprocessor to safely
overflow on the coprocessor save area without any issue.

Change-Id: Ic2acd20b60b6bef0b7feeb8cfb54d548eba892f0
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
ef098bf410 Xtensa port: Restore interrupted context the same way as premption resume.
This was a kind of optimization that save few cycles in the cost of code
duplication. However the path where we resume from interrupt withouch changing
the running thread is buggy and leads to many tests to fail. For now I'd prefer
to remove this optimization and have a working port. Later, once everything is
OK, I'll have time to optimize things.

Change-Id: I7af58f383848d157b9f3b3fbeceede3e83f9ce61
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
b978c70338 Xtensa port: Removed duplicate code and fixed update of current thread pointer.
Having duplicate code leads always to this kind of situation where a bug is
fixed in one place and not in the other. This bug of updating current thread
pointer was already fixed before in the Swap function, but not in the interrupt
handler.

Change-Id: I466aea2d35382446c5c82fe775ada31f0bd19492
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
6af2778136 Xtensa port: Fixed linker script for hifi_mini core.
Change-Id: I21f4ff0c136c1e72e6d36d179898bbde1b08b71f
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
f11910a7fb xtensa: Makefile: cleanup
Some options which are already defined by the build system
for the C compiler or assembler have been removed: -c,
-xassembler-with-cpp, -nostdinc.
References to deleted variable flagALongCall and flagLongCall
removed.
Formatting for 80 columns, there is now one flag per line.

Change-Id: Ieecdb75e26f64c6f58dec3cc636552e7b31a678d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
aacfd63331 Xtensa port: Removed duplicate file and renamed to sys_io.h as other platforms.
Change-Id: I293bfa9ff8c5e641c727612c56968cec901dbfec
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
bb038cc1be Xtensa port: Fixed function setting Sawp return value.
The retval field shall hold the return value itself not a pointer on its
location.

Change-Id: I3f9e225f2bdd501f88441946b5187ebbd17a71e3
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
cb745e6047 Xtensa port: Fixed RAMABLE_REGION in linker scripts.
This was introduced during a copy/paste when updating patch
https://gerrit.zephyrproject.org/r/#/c/10323/6..7

Change-Id: Id6857dd28a16974361932285b44559f702c4d910
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
b72936f305 Xtensa port: Fixed Swap function not updating _kernel.current.
Change-Id: I561967404751436717950e28a776317aea5e05c3
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
93e53da56a Xtensa port: Removed warnings related to function _NanoFatalErrorHandler.
This function needs to be decalred in a file included by _thread_entry.
It also needs to have exit function declared as not returning.

Change-Id: I2a01e7408cf70266351ae5089f45b5d9d009fabe
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
7c75da1e1a Xtensa port: Added missing initalization of thread base sturct in _new_thread.
Change-Id: Icf9e1e6d5f831c2cf6e1262c6f8e1a46356edfe7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
2f4bec77d3 Xtensa port: Removed compiler warnings about printf formats/arguments mismatch.
Change-Id: Ie430072243911dc74263dbd7afe8703d0b3c4731
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
fddb1aa016 Xtensa port: _thread_entry shall use call4 to start the thread.
The function _new_thread sets the CALLINC for _thread_entry when calling the
new thread entry point. This should be CALLINC(1) (call4) instead of previous
one CALLINC(2) (call8).

This change allows resolving a crash when starting the first thread.

Change-Id: Ie97c95c87d1219342fed09f670fcae8a6230cefe
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
6fb67ed1ac Xtensa port: Replaced call to legacy sys_thread_self_get by one to k_current_get
Change-Id: I341f6bde6f6956c9ce521c4346894ee893b8e9ae
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
de2288ac38 Xtensa port: Fixed assembly comments to be accurate with code.
Change-Id: I7e0381cbefae916db515be4c10fe820dd4eddea6
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
af2593ea7e Xtensa port: Added linker script for several Xtensa cores.
Change-Id: I7a40d5f0c3fe8d25623b88f06523cb62e4ba4706
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
aa1e95bfb2 Xtensa port: Moved XCC specific libraries out of genric Xtensa make file.
These libraries are unlikely to be uesd by GCC port and thus should not be in
a generic make file. Moved to specific toolchain make file.

Change-Id: Ib585b87700e409d678f7a5cb60cff67b6022ab05
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
b8cbd05e6b Xtensa port: Enable long calls for Xtensa vector table.
Change-Id: I2e4c9ca0742988eb9ab4ec2db7c81bc988212f2c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
e4e3cf604e Xtensa port: Added Xtensa specific code (C + S) files.
Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
e2dd006ba7 Xtensa port: Removed the need to put an empy file soc.c in arch/xtensa/soc dir.
Change-Id: I439a6c36f10c6255d15a688c8f425de0fab93912
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
9baece323e Xtensa port: Added Kbuild file for Xtensa arch.
Change-Id: I174c5736c891f94309361079cfd8b47dbb43032a
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
49b3c0028d Xtensa port: Added fields offset support for kernel and thread structures.
Change-Id: I9cc44f60757a2f988e2a6341da9591a5e5f54561
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
71b884b658 Xtensa port: Added Xtensa header generic files.
Change-Id: Ia2202080d09008fbfd4e803cd5266aa8caa16388
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
b78ceec452 Xtensa port: Added kernel arch dependent structs and functions.
Change-Id: I8b35454cdaac0087b7b68b96e6ec1780c71b1e9d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Max Filippov
f5f69c99c4 xtensa: support 'make qemu' target
Provide generic support for running zephyr kernels on xtensa QEMU and
map D_233L SoC to dc233c QEMU core.

Change-Id: Ie804588f750213a7cc54dbc95c86ee4d62ba1ea5
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
1cded67f38 Xtensa port: Started port to for Xtensa cores family.
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.

Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:26 -08:00
Qiu Peiyang
fde2b3f642 pinmux: fix default pinmux driver for quark_se_ss
Fix commit 42e1c9c, missing default pinmux driver
config for quark_se_ss.

Jira: ZEP-1665

Change-Id: I40b693c2d6cf160c470efdabf428c2597abbe881
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
2017-02-12 00:32:13 +00:00
Anas Nashif
81f61f9cdc arm: sam70: refactor clearing of exception faults to common code
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I8a9045eb46d5a23cbbd9a6bce75a0f1e78171eeb
2017-02-11 07:00:38 +00:00
Anas Nashif
110df98619 Merge "Merge arm branch into master" 2017-02-11 04:00:58 +00:00
Andrew Boie
c99c686b2c nios2: use gen_isr_tables mechanism
Change-Id: If1ffcedf86a015789b42e7aec45dae3cc58f74fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:28:00 +00:00
Andrew Boie
2752357922 arm: enable direct interrupts feature
Issue: ZEP-1038
Change-Id: I5417e516cc994e2bbe6bb987d9ed95e912941aa0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:59 +00:00
Andrew Boie
e7acd3224c arm: use gen_isr_tables mechanism for interrupts
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.

Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:58 +00:00
Andrew Boie
1927b3d020 gen_isr_tables: New static interrupt build mechanism
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:

 1) It is now possible to use enums as the IRQ line argument to
    IRQ_CONNECT(), which should ease CMSIS integration.
 2) The vector table itself is now generated, which lets us place
    interrupts directly into the vector table without having to
    hard-code them. This is a feature we have long enjoyed on x86
    and will enable 'direct' interrupts.
 3) More code is common, requiring less arch-specific code to
    support.

This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.

Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-11 01:27:58 +00:00
Sarath R Nair
8ac992bfcd quark_se: Save/restore debug registers.
In order to set breakpoints after waking up from sleep,
it is needed to save DR0/DR1/DR2/DR3 and DR6/DR7.

As DR4/DR5 are reserved or mapped to DR6/DR7, they are not saved.

Patch2 : Added compile time checks for debug build or soc_watch
build for Intel Energy analysis.

Patch3 : Avoid clobbering of edx.

JIRA: ZEP-1681

Change-Id: I62fbedca16953d57196420ecae4fb93c785bb4a5
Signed-off-by: Sarath R Nair <sarath.nandu.ramachandran.nair@intel.com>
2017-02-11 00:15:08 +00:00
Andy Gross
ac37e3e2c7 arm: include: Add DTS generated file to arch.h
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file.  This was done to simplify the
includes required for files.  Only two files will include the dts
generated include file directly: arch.h and the linker.ld

Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 15:31:26 -06:00
Kumar Gala
6ca87b576e arm: cmsis: Remove last bits of scs/scb as we've converted to CMSIS
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.

Jira: ZEP-1568

Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 15:14:23 -06:00
Kumar Gala
52cf45c62a arm: cmsis: Convert _Scb*Fault*Reset to use direct CMSIS register access
Coverted:
	_ScbMemFaultMmfarReset
	_ScbBusFaultBfarReset
	_ScbUsageFaultAllFaultsReset

To use direct CMSIS register access.

Also removed scb.h and references as there is no longer any code in it.

Jira: ZEP-1568

Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
94db819626 arm: cmsis: Convert _ClearFaults to use direct CMSIS register access
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.

Jira: ZEP-1568

Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-02-10 14:47:41 -06:00
Kumar Gala
80ed5ccc78 arm: cmsis: Convert printing of MMFSR, BFSR, and UFSR to CMSIS
Converted access to CFSR MMFSR, BFSR, and UFSR to use direct CMSIS
register access when printing out the values of those registers.

Jira: ZEP-1568

Change-Id: I7969bb81346327637140ec23d91422a6bfaef032
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-02-10 14:47:41 -06:00
Kumar Gala
737207f052 arm: cmsis: Convert _Scb*FaultAddrGet to use direct CMSIS register access
Coverted:
	_ScbBusFaultAddrGet
	_ScbMemFaultAddrGet

To use direct CMSIS register access

Jira: ZEP-1568

Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
d2679c7bbb arm: cmsis: Convert _Scb*FaultIs* & _ScbIs*Fault to use CMSIS register access
Converted:
	_ScbHardFaultIsBusErrOnVectorRead
	_ScbIsMemFault
	_ScbMemFaultIsMmfarValid
	_ScbMemFaultIsStacking
	_ScbMemFaultIsUnstacking
	_ScbMemFaultIsDataAccessViolation
	_ScbMemFaultIsInstrAccessViolation
	_ScbIsBusFault
	_ScbBusFaultIsBfarValid
	_ScbBusFaultIsStacking
	_ScbBusFaultIsUnstacking
	_ScbBusFaultIsImprecise
	_ScbBusFaultIsPrecise
	_ScbBusFaultIsInstrBusErr
	_ScbIsUsageFault
	_ScbUsageFaultIsDivByZero
	_ScbUsageFaultIsUnaligned
	_ScbUsageFaultIsNoCp
	_ScbUsageFaultIsInvalidPcLoad
	_ScbUsageFaultIsInvalidState
	_ScbUsageFaultIsUndefinedInstr

To use direct CMSIS register access

Jira: ZEP-1568

Change-Id: I2a99a4101c5960f825a502c225e511e49fe93bba
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-02-10 14:47:41 -06:00
Kumar Gala
1a146174cb arm: cmsis: Convert _ScbDivByZeroFaultEnable to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I0118f2d44d2b6fb4eac41b0c66b20c5a85e35795
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
831764a898 arm: cmsis: Convert _ScbHardFaultIsForced to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I9bf2ec4c84f87c8e9d72dc41324d7ee627d2dc2e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
a033a89d76 arm: cmsis: Convert _ScbActiveVectorGet to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: Ibbb3f71d7ee42ab62f764d45bd334c7840b3c04d
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
388c26574f arm: cmsis: Convert FaultEnable to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I1274ee206576babb4bc0b9308d1cc24d7092166a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Kumar Gala
cecdc99f38 arm: cmsis: Convert _ScbIsNestedExc to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I3d41fe88293bab2f40d9177cedb56e9265250dff
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-02-10 14:47:41 -06:00
Adam Podogrocki
ce591ac378 gpio/stm32: fix in setting alternative function
Pin number should be decremented by 8 if the pin
refers to the GPIOx_AFRH register.

Change-Id: I76e960f3b4adc3c2139ef5a88f15dbe98603228e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-02-10 14:47:41 -06:00
Erwan Gouriou
c4154fd591 soc: stm32f3x: clean up after Cube LL clock control
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.

Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-10 14:47:41 -06:00
Erwan Gouriou
dd481e2dc3 soc: stm32l4x: clean up after Cube LL clock control
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native L4 Clock control driver.

Change-Id: Ic0408d5f5ec66651d46d13dfaf447da2666367cd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-10 14:47:41 -06:00
Erwan Gouriou
7ed7ccc020 soc: stm32f3xx: support of Cube LL Clock driver
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32f3x soc.
Clean up will have to be done afterwards.

Change-Id: I20480579f12a6fc1f1f6a51589981ac3f1d63ef0
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-10 14:47:41 -06:00
Erwan Gouriou
7c7bfd3a8d soc: stm32l4xx: support of Cube LL Clock driver
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32l4x soc.
Clean up will have to be done afterwards.

Change-Id: I979a4169148c5fe5a0693d182d2d17f9ffaf1c77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-02-10 14:47:41 -06:00
Bogdan Davidoaia
5b02ba8319 kw41z: add base DTS support
This patch adds the base DTS support for the KW41Z Freedom board. The
initial set of changes include SRAM, FLASH, IRQ controller and LPUART
support.

Change-Id: Ic68c4959ddad0c5cfe70d5576a0e58372b93ec9d
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
2017-02-10 18:14:05 +00:00
Vincenzo Frascino
0da2a03234 v2m_beetle: uart: Add DTS support to UART driver
This patch adds DTS support to the ARM CMSDK UART driver.  The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.

Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:14:04 +00:00
Vincenzo Frascino
ae5dbe47f6 arm: dts: Add base DTS support for v2m_beetle
This patch adds the base DTS support for the V2M Beetle board.  The
initial set of changes include SRAM, FLASH, and IRQ controller support.

Change-Id: I06685622b9c57ac358544c71350074ce06e3371e
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:14:03 +00:00
Erwan Gouriou
1e92c22a13 nucleo_l476rg: Enable device tree usage for Nucleo
This patch adds all the necessary changes to enable use of DTS for
generating required build information.

Change-Id: Ia476fbb14c7d9d6b9db3340c73f599556a880da3
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:14:02 +00:00
Gil Pitney
b465fbe312 cc3200: Enable device tree usage for CC3200
This patch ifdef's out information that would be redefined by
information generated from DTS.  This patch also fixes up the serial
drives to work properly with the DTS generated information.

Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:14:01 +00:00
Andy Gross
ddce7dea40 dts: arm: Kinetis: Add base support for Kinetis
This patch adds DTS support and related files for the NXP Kinetis
platform.  The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms.  The YAML files provide the definitions of
the contents of the DTS nodes.

The Kconfig changes were put in place to allow for the conversion of
existing drivers.  Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.

Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:13:59 +00:00
Andy Gross
bb063164aa dts: Add support for Device Tree
This patch adds support for using device tree configuration files for
configuring ARM platforms.

In this patch, only the FLASH_SIZE, SRAM_SIZE, NUM_IRQS, and
NUM_IRQ_PRIO_BITS were removed from the Kconfig options.  A minimal set
of options were removed so that it would be easier to work through the
plumbing of the build system.

It should be noted that the host system must provide access to the
device tree compiler (DTC).  The DTC can usually be installed on host
systems through distribution packages or by downloading and compiling
from https://git.kernel.org/pub/scm/utils/dtc/dtc.git

This patch also requires the Python yaml package.

This change implements parts of each of the following Jira:
ZEP-1304
ZEP-1305
ZEP-1306
ZEP-1307
ZEP-1589

Change-Id: If1403801e19d9d85031401b55308935dadf8c9d8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-02-10 18:13:58 +00:00
Jesus Sanchez-Palencia
98d4836105 linker quark_se: Fix operator precedence bug
Without this patch, the final linker script had a memory region defined
as:

    RAM (wx) : ORIGIN = 0xA8006400, LENGTH = 55*1K - 0x20 +0x4

resulting on the wrong RAM length. Fix BSP_SHARED_RAM_SIZE definition
so the sum is always processed first.

Change-Id: I16b93adbaf27bb84b6e5d1ac433ef80f854b218c
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-09 19:58:45 +00:00
Andrew Boie
d81e033044 build: Separate out prebuilt kernel logic from toplevel
Arch-specific stuff shouldn't be in the toplevel Makefile,
forthcoming patches will soon introduce special interrupt
handling logic for other arches.

Change-Id: Ib5a86cbdf5b32ecfce9e5e234f7cbea2bc3ce9c1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-08 19:11:10 +00:00
Andrew Boie
164ba8c5cd sw_isr_table.h: clean up definition
This private data structure now no longer introduces a typedef or
uses CamelCase. It's not necessary to specify the size of extern
arrays, so we don't need a block of #ifdefs for every arch.

Change-Id: I71fe61822ecef29820280a43d5ac2822a61f7082
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-08 18:14:37 +00:00
Juan Solano
d490573933 quark_se_ss: Remove enter_arc_state and use QMSI functions
This commit removes the local implementation of enter_arc_state, where
the ARC is instructed to sleep, using instead the QMSI 1.4 functions.

Change-Id: Id489ad53851be50fc5e50add698891fcfaef3abe
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
2017-02-08 13:41:26 +00:00
Ramesh Thomas
444ecafeee kernel: Remove redundant TICKLESS_IDLE_SUPPORTED option
This flag is no longer necessary and TICKLESS_IDLE will be
enabled by default if SYS_POWER_MANAGEMENT is enabled.

Jira: ZEP-1325
Change-Id: Ic6cd4b8dc0a17c6a413cabf6509b215a4558318d
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-02-08 13:02:34 +00:00
Jesus Sanchez-Palencia
a19d4ad041 quark_d2000: Add shared GDT memory to linker
A new shared memory area has been added to the QMSI bootloader in
order to store the GDT in RAM reliably.

Add the new entry to the QUARK D2000 linker script and new
kconfig options:

 * CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
   of the GDT in RAM.

 * CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
   GDT in RAM.

This is only enabled when  CONFIG_SET_GDT is NOT set.

Change-Id: Ie084079475853dce153dd9f3e88ad4a9784bdedf
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-08 11:59:15 +00:00
Jesus Sanchez-Palencia
bcee91d70e quark_se: Add shared GDT in RAM memory to linker
A new shared memory has been added to the QMSI bootloader in order to
store the GDT in RAM reliably.

Add this new entry to the QUARK SE C1000 linker script and new kconfig
options:

 * CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
   of the GDT in RAM.

 * CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
   GDT in RAM.

Additionally, both BSP_SHARED_RAM_ADDR and BSP_SHARED_RAM_SIZE have been
renamed to BSP_SHARED_RESTORE_INFO_RAM_ADDR and
BSP_SHARED_RESTORE_INFO_SIZE respectively, in order to better resemble
what these options are for. All these configs are available
unconditionally.

Change-Id: I07ee8b440d4a3f5e9bdeb62441ff6a7bd6d4c153
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Bartlomiej Majka <bartlomiejx.majka@intel.com>
2017-02-08 11:59:14 +00:00
Jesus Sanchez-Palencia
78224e1a75 quark_se: Fix restore info address
For the next QMSI release, the shared restore info address has been
modified to 0xA8013FDC .

Change-Id: I72eaef4f15f7ef6fb8e7eb9acd7d96451623e103
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-08 11:59:13 +00:00
Kuo-Lang Tseng
23b0074012 ext qmsi: Update to QMSI 1.4 RC2
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.

Also, arch soc specific power management code were updated.

Jira: ZEP-1572

Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
2017-02-08 11:59:12 +00:00
Tim Nordell
93801c6447 arm: Adjust entry point of XIP kernels to the __reset function
The entry point specified in the elf file should always point to
executable code, and not to the interrupt vector table.  Pointing to the
vector table as the entry point in the elf file presents problems with
running the kernel against a debugger as the debugger starts the program
counter at the top of the interrupt vector table.

Change-Id: I76051f6e99a44bab72936670bead5fb8191a6ec7
Signed-off-by: Tim Nordell <tim.nordell@nimbelink.com>
2017-02-04 19:32:40 +00:00
Baohong Liu
a1b8ed0ac6 quark_se: sensor: use consistent device names for GPIO, SPI and I2C
Rename devices. For example, the two i2c devices in the
quark se sensor sub-system will have name string "I2C_0"
and "I2C_1", while the other two i2c devices accessible to
both x86 and arc will have name string "I2C_2" and "I2C_3".
This is valid only when you build arc binary. 

It does not apply if you build x86 or arm binary. Similar change is
also made for GPIO and SPI.

Jira: ZEP-1588 ZEP-1614

Change-Id: Ibad4486e70e0aaf287763514a5a9d28b43bca094
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2017-02-04 19:21:08 +00:00
Jean-Paul Etienne
47e2f4e3d7 riscv32: added a generic linker script for the riscv32 platform
Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.

Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.

Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-03 19:20:52 +01:00
Jean-Paul Etienne
c989f0b408 riscv32: timer: replace riscv_qemu_driver by the generic riscv_machine_driver
riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.

The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.

Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-02-03 19:20:52 +01:00
Andrew Boie
e01dd87377 x86: implement direct interrupts
Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-03 18:18:30 +00:00
Piotr Mienkowski
d519ef17b7 drivers: Add Atmel SAM family GMAC Ethernet driver
This is a zero-copy networking implementation of Ethernet driver.

Limitations:
- one shot PHY setup, no support for PHY disconnect/reconnect
- no support for devices with DCache enabled due to missing
  non-cacheable RAM regions in Zephyr.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-1492
Change-Id: Ib944f91193efbd12c1142b0bcf1f635388bf1b87
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-02-01 21:01:19 +00:00
Piotr Mienkowski
9d1c6de608 drivers: Add basic Atmel SAM USART driver
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
2017-02-01 21:01:18 +00:00
Piotr Mienkowski
427996050a arch: Add pmc, gpio internal Atmel SAM drivers
Added common, internal, always available SAM HAL drivers: pmc, gpio.
Note: these drivers are meant to be used by other SAM drivers, not by
a user space program directly.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-978
Change-Id: I00cca358f27790dc94cf79f840584b85ff5191f6
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
2017-02-01 21:01:17 +00:00
Piotr Mienkowski
f604480438 arch: Add support for Atmel SAM E70 SoC configuration at boot
Added support for early SoC configuration which does not belong
conceptually to system initialization. ERASE, JTAG TDI pins are
currently configured here.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-978
Change-Id: Id51adddb4c7cce22907af214461d75db83df129a
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-02-01 21:01:16 +00:00
Piotr Mienkowski
be468b0913 arch: Add Atmel SAM E70 SoC support
Added support for Atmel SAM E70 (Cortex-M7) MCU:
- Kconfig files
- device start-up code

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-978
Change-Id: Ide4fd5dadd94897303090a6507b8d048773b645e
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
2017-02-01 21:01:14 +00:00
Kumar Gala
843e3568de arm: scb: Move SCB asm defines into cpu_idle.S
As cpu_idle.S is the only bit of code that is using the SCB asm defines,
so to allow us to remove scb.h in the future lets move the defines that
are used just into cpu_idle.S

Jira: ZEP-1568

Change-Id: I3c3a6f145ec4c1a43f076d079d5fe1694c255b78
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:39 -06:00
Kumar Gala
772cbd1955 arm: cmsis: Convert _ScbIsInThreadMode to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: Idc14817ce85042ec86bdf67b8939f783224329ff
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:39 -06:00
Kumar Gala
5068e9657f arm: cmsis: Convert _ScbPendsvSet to use direct CMSIS register access
Jira: ZEP-1568

Change-Id: I25653d8fbe3842fbfa79191d388c6f6693fca39c
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:39 -06:00
Kumar Gala
f16cefea9f arm: refactor clearing of exception faults to common code
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init.  Lets refactor that into a common function so we don't have
to keep duplicating it over and over.

Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:38 -06:00
Vincenzo Frascino
1632938cfa soc: arm: mps2: Fix UART4 base address
This patch fixes the UART4 base address on the ARM MPS2 platform.

Change-Id: I14bf2a4dc2378d4b2c4295a75cd68c6c895fbd60
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-30 11:02:36 -06:00
Kumar Gala
69b9d345ae arm: cmsis: Remove nvic.h and use CMSIS NVIC calls directly
Kill of nvic.h and use either CMSIS helper functions for NVIC or direct
NVIC register access via CMSIS for IRQ handling code.

Jira: ZEP-1568

Change-Id: If21910b9293121efe85c3c9076a1c2b475ef91ef
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:36 -06:00
Kumar Gala
f85dbb1b34 arm: cmsis: Convert _ScbExcPrioSet to NVIC_SetPriority
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities.  We don't need to shift around the
priority values for NVIC_SetPriority.

Jira: ZEP-1568

Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-30 11:02:36 -06:00
Vincenzo Frascino
8831a6bff1 soc: arm: mps2: Add configuration for CMSDK Driver
This patch adds the configuration parametes required to enable CMSDK
(Cortex-M System Design Kit) Drivers at MPS2 soc level.

It provides as well the definitions for the MPS2 System Control
registers.

Change-Id: I06181dcfeb4fb887425b85ec9a99c268c857a34e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-30 11:02:36 -06:00
Maureen Helm
86a26fa0ae kw41z: Add kw41z SoC
Adds initial support for the kw41z SoC. This is the first SoC in the
Kinetis W (wireless connectivity) series added to Zephyr. The kw41z
integrates a 2.4 GHz radio transceiver, BLE link layer hardware, and an
802.15.4 packet processor with an ARM Cortex M0+. It has 512 KB flash,
128 KB SRAM, and can run the system clock at up to 48 MHz.

This SoC currently has mcux shim drivers for lpuart (serial), gpio,
pinmux, i2c, and flash.

Jira: ZEP-1389
Change-Id: I8cff6d203867ba3ace7e05c36441dc8f3cbca8d8
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-30 11:02:35 -06:00
Maureen Helm
8d5833ffaa k64: Rename security_frdm_k64f section
Renames the flash security section so it makes sense for other Kinetis
devices, not just k64. In Kinetis reference manuals, this section is
referred to as the 'flash configuration field'.

Change-Id: I2b7c7cc1ec2541419d77878d367d96c9ceb7a0cf
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-30 11:02:35 -06:00
Maureen Helm
e290006144 serial: Introduce new mcux lpuart shim driver
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.

NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.

Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:

	<interface>_mcux_<hw block>

Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.

<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.

Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-30 11:02:35 -06:00
Carles Cufi
17f7b4ed95 ext: Integrate Nordic SDK HAL files into Zephyr
Nordic Semiconductor's Software Development Kit's HAL layer
provides a set of low-level header and sourcefiles that give access
to the different hardware peripherals of Nordic ICs.

This patch includes the new files in the build and refactors the Kconfig
and Kbuild files in ext/hal/nordic to acommodate for the presence of the
new HAL layer.

Change-Id: Ie8e1a4c9fcc7e9058a9d16a2692ef1789603aa53
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2017-01-27 14:44:19 +01:00
Anas Nashif
42e1c9ca34 pinmux: make pinmux_dev the default pinmux driver for quark
Jira: ZEP-958
Change-Id: Ib6c528a103372d5084efa5ae8635803e2912e0dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-01-25 20:43:18 +00:00
Marcus Shawcroft
cf94f6144d gpio/stm32: Move from the OPEN_DRAIN interface to the DRIVE_STRENGTH interface
The STM32 GPIO driver extended the generic GPIO driver interace with
the concept of OPEN_DRAIN.  There is previous discussion about
representing such concepts in the GPIO interface in a more general
fashion here:

https://lists.zephyrproject.org/archives/list/devel@lists.zephyrproject.org/thread/6DCFUAKCOOOBHUO3ZK45ES6IQXOEOFWN/

The DRIVE STRENGTH interface supports the concepts of OPEN DRAIN and
other variants supports by other vendors hardware.

Adjust the STM32 GPIO driver to use the DRIVE STRENGTH interface.  A
following patch will address the simplication of gpio.h

Change-Id: I56b0792ec2b21f1adc673dff019288dc8573d005
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-25 08:47:22 +00:00
Andre Guedes
6f141a5576 quark_se: PM: Add multicore support
This patch changes Quark SE power drivers to support multicore scenarios
e.g. both LMT and ARC core are enabled and manage power.

Handling LPS states in multicore scenarios are dead simple because LPS
states are core-specific states. It means that putting the LMT core in
LPS doesn't affect the ARC core, and vice-versa. DEEP_SLEEP state, on
the other hand, affects both cores since it turns power off from the SoC
and both cores are shutdown. It means that if LMT puts the system in
DEEP_SLEEP, ARC core is shutdown even if it is busy handling some task.

In order to support the multicore scenario, this patch introduces the
SYS_POWER_STATE_DEEP_SLEEP_2 state to both ARC and x86 power drivers.

On ARC, this state works as following:
1) Save ARC execution context;
2) Raise a flag to inform the x86 core that ARC is ready to enter in
   DEEP_SLEEP;
3) Enter in the lowest core-specific power state, which in this case is
   LPSS.

On x86, DEEP_SLEEP_2 is very similar to DEEP_SLEEP. The difference relies
in the post_ops() which calls _arc_init() in order to start ARC core so
it can restore its context.

This patch also adds the test/power/multicore/ directory which provides
sample application to x86 and ARC cores in order to easily verify the
multicore support. In test/power/multicore/README.rst you can find more
details regarding the applications.

Jira: ZEP-1103

Change-Id: Ie28ba6d193ea0e58fca69d38f8d3c38ca259a9ef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2017-01-24 13:36:55 +00:00
Benjamin Walsh
ee659ae1a1 build: add _ASMLANGUAGE to all asm files
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.

Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:51 +00:00
Benjamin Walsh
ed240f2796 kernel/arch: streamline thread user options
The K_<thread option> flags/options avaialble to users were hidden in
the kernel private header files: move them to include/kernel.h to
publicize them.

Also, to avoid any future confusion, rename the k_thread.execution_flags
field to user_options.

Change-Id: I65a6fd5e9e78d4ccf783f3304b607a1e6956aeac
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:50 +00:00
Benjamin Walsh
4b65502448 kernel/x86: move INT_ACTIVE/EXC_ACTIVE to thread_state
They are internal states, not user-facing.

Also prepend an underscore since they are kernel internal symbols.

Change-Id: I53740e0d04a796ba1ccc409b5809438cdb189332
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:50 +00:00
Benjamin Walsh
a8978aba8f kernel: rename thread states symbols
They are not part of the API, so rename from K_<state> to
_THREAD_<state>.

Change-Id: Iaebb7d3083b80b9769bee5616e0f96ed2abc5c56
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:49 +00:00
Kumar Gala
6782c3ea23 arm: cmsis: Convert relocate_vector_table to use CMSIS
Replace _scs_relocate_vector_table with direct CMSIS register access and
use of __ISB/__DSB routinues.  We also cleanup the code a little bit to
just have one implentation of relocate_vector_table() on ARMv7-M.

Jira: ZEP-1568

Change-Id: I088c30e680a7ba198c1527a5822114b70f10c510
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:55 -06:00
Kumar Gala
82027c68f9 arm: cmsis: Convert DO_REBOOT to use CMSIS
CMSIS provides a complete implentation for reboot, we can utilize it
directly and reduce zephyr specific code.

Jira: ZEP-1568

Change-Id: Ia9d1abd5c1e02e724423b94867ea452bc806ef79
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:55 -06:00
Carles Cufi
88bbd6ccb1 arm: cmsis: Convert enable_floating_point to use CMSIS
As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().

Jira: ZEP-1568

Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:54 -06:00
Kumar Gala
457a5988c4 arm: cmsis: Introduce CMSIS layer
Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.

We provide defaults in the case for:
	IRQn_Type enum
	*_REV define (set to 0)
	__MPU_PRESENT define (set to 0 - no MPU)
	__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
	__Vendor_SysTickConfig (set to 0 - standard SysTick)

Jira: ZEP-1568

Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:54 -06:00
Kumar Gala
375a0ef393 arm: cmsis: Remove unused code from scb/scs layers
In preperation for removing the scb/scs layers and using CMSIS directly
lets remove all the _Scb* and _Scs* functions that are not currently
used.

Jira: ZEP-1568

Change-Id: If4641fb9a6de616b4b8793d4678aaaed48e794bc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:54 -06:00
Jon Medhurst
cd8fd42de9 arm: soc: Add SoC series for ARM's Cortex-M Prototyping System (MPS2)
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).

All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.

In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.

ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).

[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html

Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-23 15:15:54 -06:00
Maureen Helm
8769cd585e spi: k64: Remove the k64 spi driver
Now that we have a more generic mcux spi driver that can be used across
multiple Kinetis SoCs, remove the specific k64 spi driver.

Jira: ZEP-1374
Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-23 15:15:54 -06:00
Maureen Helm
e1c9dfcee5 k64: Change the default spi driver to the mcux shim
Jira: ZEP-1374
Change-Id: I8ae160e32b0f46120138025e373724ad97cb0cd6
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-23 15:15:54 -06:00
Vincenzo Frascino
8971da0375 soc: arm: beetle: Add Timers IRQ map
This patch adds the timers IRQ map to the ARM Beetle SoC platform.

Jira: ZEP-1300
Change-Id: If38a197210f71ae90c7ee6274395f064116faf72
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2017-01-23 15:15:53 -06:00
David Brown
dee8ef6f4f arm: cortex-m: Implement CONFIG_TEXT_SECTION_OFFSET
On other targets, CONFIG_TEXT_SECTION_OFFSET allows the entire image to
be moved in memory to allow space for some type of header.  The Mynewt
project bootloader prepends a small header, and this config needs to be
supported for this to work.

The specific alignment requirements of the vector table are chip
specific, and generally will be a power of two larger than the size of
the vector table.

Change-Id: I631a42ff64fb8ab86bd177659f2eac5208527653
Signed-off-by: David Brown <david.brown@linaro.org>
2017-01-23 15:15:53 -06:00
Maureen Helm
294fdab7bd serial: k64: Remove the uart_k20 driver
Now that we have a more generic mcux serial driver, remove the uart_k20
driver.

Jira: ZEP-719
Change-Id: I51a3237454140feabbfe18ac2c8ee451e572c7be
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-23 15:15:53 -06:00
Maureen Helm
8c3d4f770a k64: Change the default serial driver to the mcux one
Stop using the specific uart_k20 driver by default and start using the
more generic mcux uart driver instead.

Jira: ZEP-719
Change-Id: I7b107ea7118887591362159283ebb5413b45595a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-23 15:15:53 -06:00
Erwan Gouriou
8890b73b6e license: Replace Apache boilerplate with SPDX tag
Apply JIRA: ZEP-1457 to STM32F3X family porting patchset.

Change-Id: I352267a47847143e557a4016de12bb9a14a20067
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:53 -06:00
Kumar Gala
05f717e71b uart/stm32: add STM32F3X support for uart
Change-Id: I9796c6a2841c972eeab15894a6d7f38ae93606d1
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-23 15:15:53 -06:00
Adam Podogrocki
726d11a5a2 pinmux/stm32: extend pinmux driver functionality to support STM32F3X series MCUs
Change-Id: Ifc4c93e03b6593f1b6c7e664fdf719f9344fe1ee
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-23 15:15:52 -06:00
Adam Podogrocki
f23492a059 gpio/stm32: provide GPIO driver implementation for STM32F3X family
Implementation includes adding some defines in the pinmux,
adjusting gpio driver to specific defines for STM32F3X family,
adding specific functionality in the F3X SoC definition.

Change-Id: I465c66eb93e7afb43166c4585c852e284b0d6e67
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-23 15:15:52 -06:00
Adam Podogrocki
61cc74c425 flash/stm32: flash driver for STM32F3x series microcontrollers
Change-Id: I0b41a50507a09a513a67d13374323d831a0ec86a
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-23 15:15:52 -06:00
Adam Podogrocki
c514f671c7 clock/stm32: add STM32F3X reset and clock control
Change-Id: Ie5f3ffec0b3aaf15f9d9f8063d2bab6be5aebb6e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-23 15:15:52 -06:00
Adam Podogrocki
42a4615973 soc/stm32: add initial support for STM32F3X series
Supported SoCs:
- STM32F303XC
- STM32F334X8
- STM32F373XC

Change-Id: I74b9561272d54e270ae1a1f602fd389d4c86539a
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-23 15:15:52 -06:00
Ricardo Salveti
6e14642c1e arm/nordic_nrf5: enable SOC_FLASH_NRF5 by default if FLASH is enabled
SOC_FLASH_NRF5 is compatible with any nrf5 device, so enable the driver
by default if CONFIG_FLASH is also enabled.

Change-Id: I6ddf7cc41bb28071f682e78661b184a8e2ee7aa9
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2017-01-23 15:15:52 -06:00
Ricardo Salveti
58460a52c9 arm: set default vector table address in prep_c when XIP
It is called before early SoC initialization, so remove the duplicated
code from other boards and just set it by default when using XIP.

This can later be used when adding bootloader support, as an
additional option could be created to move the VTOR offset to a
different address.

Change-Id: Ia1f5d9a066de61858ee287215cefdd58596b6b1c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2017-01-23 15:15:52 -06:00
David B. Kinder
ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Anas Nashif
003a46a2f2 riscv32: fix KConfig selection of ATOMIC_OPERATIONS_C
Jira: ZEP-1583
Change-Id: Icc06b8531b74dd884e4b1224c77fa5a9cabbd629
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-01-17 15:37:21 +00:00
Jean-Paul Etienne
dae36b97e8 riscv32: added support for the riscv32-qemu soc
Change-Id: I7cf71f7a99fed7c83ed761ead9295697929d767d
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:57:51 +00:00
Jean-Paul Etienne
2a8cfca4cf riscv32: added support for the pulpino soc
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)

Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:55:05 +00:00
Jean-Paul Etienne
cd83e85edc arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.

1) exceptions/interrupts/faults are handled at the architecture
   level via the __irq_wrapper handler. Context saving/restoring
   of registers can be handled at both architecture and SOC levels.
   If SOC-specific registers need to be saved, SOC level needs to
   provide __soc_save_context and __soc_restore_context functions
   that shall be accounted by the architecture level, when
   corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.

2) As RISC-V architecture does not provide a clear ISA specification
   about interrupt handling, each RISC-V SOC handles it in its own
   way. Hence, at the architecture level, the __irq_wrapper handler
   expects the following functions to be provided by the SOC level:
   __soc_is_irq: to check if the exception is the result of an
                 interrupt or not.
   __soc_handle_irq: handle pending IRQ at SOC level (ex: clear
                     pending IRQ in SOC-specific IRQ register)

3) Thread/task scheduling, as well as IRQ offloading are handled via
   the RISC-V system call ("ecall"), which is also handled via the
   __irq_wrapper handler. The _Swap asm function just calls "ecall"
   to generate an exception.

4) As there is no conventional way of handling CPU power save in
   RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
   functions just unlock interrupts and return to the caller, without
   issuing any CPU power saving instruction. Nonetheless, to allow
   SOC-level to implement proper CPU power save, nano_cpu_idle and
   nano_cpu_atomic_idle functions are defined as __weak
   at the architecture level.

Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:52:23 +00:00
Benjamin Walsh
3c39e55ab1 arc: fix unaligned variables resulting in unaligned k_cpu_sleep_mode
Force-align all variables defined via asm .word to ensure 4-byte
alignment.

The straddled_tick_on_idle_enter variable was a bool, which resolved in
an one-byte quantity. Changing it to a 32-bit integer. It would have
occupied 4 bytes anyway with alignment.

Fixes ZEP-1549.

Change-Id: If5e0aa1a75dbc73d896b44616f059d221fe191c6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-13 01:36:08 +00:00
Maureen Helm
eb0a2f8516 k64: Remove port clock enables from the soc init
The mcux pinmux driver enables the port clocks, so the soc init no
longer needs to enable them. Also removes some soc defines that were
used only by the legacy k64 pinmux driver.

Change-Id: I63174bef4024b5a09a73f941cea0aec691c759d3
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:28 -06:00
Maureen Helm
7682a0d7ca gpio: Remove the k64 gpio driver
Now that we have a more generic mcux gpio driver that can be used across
multiple Kinetis SoCs, remove the specific k64 gpio driver.

Jira: ZEP-1394
Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:27 -06:00
Maureen Helm
fc012feadb k64: Change the default gpio driver to the mcux one
Stop using the specific k64 gpio driver by default and start using the
more generic mcux gpio driver instead.

Jira: ZEP-1394
Change-Id: I54ec9b62cc8790b8973efc34fa36d17da523971e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:27 -06:00
Maureen Helm
4184c7f82e k64: Move uart console pins to board pinmux tables
Moves the uart console pins from the k64 soc init to the frdm_k64f and
hexiwear_k64 board pinmux tables. Not having these pins in the board
pinmux tables led one to believe that no pins in PORTB were being used
on the hexiwear_k64 board, and thus the port was incorrectly disabled by
default.

Also fixes PORTB to be enabled by default if the uart console is used.

Change-Id: Ide6b7b34dfba8a75a02a8f2bf37cce843afb92f1
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:27 -06:00
Adam Podogrocki
72782f542c clock/stm32: add STM32F107 reset and clock control
Change-Id: If2280187c866c130212ea22c3d406501f37133b2
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-01-12 09:46:27 -06:00
Adam Podogrocki
10b350d854 soc/stm32f1: Add the new type of SoC STM32F107
This patch provides initial support for the SoC STM32F107. This SoC
belongs to the Connectivity Line devices.

Connectivity line family incorporates up to 14 communication
interfaces such as: 2 x I2C, 5 x USART, 3 x SPI, 2 x CAN, USB 2.0,
10/100 Ethernet MAC.

Change-Id: I5cb2c458bce9ec1558b4168e87a7003ad9f606a5
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-12 09:46:27 -06:00
Maureen Helm
2e6350bfe3 ksdk: mcux: Remove config HAS_KSDK
Now that all the ksdk/mcux shim drivers use the config HAS_MCUX, we can
remove the config HAS_KSDK.

Change-Id: I94b7db41efae10c9234681aeb57f94e67a33c262
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:27 -06:00
Maureen Helm
4183dae89b pinmux: Rename ksdk to mcux
Renames the ksdk pinmux driver to mcux.

Change-Id: I7a519318b5b580c47b6f6652a2ae763067d85033
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:27 -06:00
Maureen Helm
e17adf377b flash: Rename ksdk to mcux
Renames the ksdk soc flash driver to mcux.

Change-Id: I835e36f25d8bc3e3aa6286718452528174378907
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:26 -06:00
Maureen Helm
aa995f8d2f random: Rename ksdk to mcux
Renames the ksdk random generator shim driver to mcux.

Change-Id: I8bc376937fed3024c809782139a0a72c7332f89a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:26 -06:00
Maureen Helm
b22bc6e69b i2c: Rename ksdk to mcux
Renames the ksdk i2c shim driver to mcux.

Change-Id: I1bcae2fa30cb698af32d6abc609d77dee42c608d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:26 -06:00
Maureen Helm
40f5de5a56 ethernet: Rename ksdk to mcux
Renames the ksdk ethernet shim driver to mcux.

Change-Id: Ief03eabe4ce39be0d0896543c1cb660ff380b439
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:26 -06:00
Maureen Helm
9f61bfce9a pinmux: Remove stale ksdk pinmux dev references
The ksdk pinmux dev driver was previously merged into the regular ksdk
pinmux driver, and the config PINMUX_DEV_KSDK was removed. Two
references were inadvertantly left behind, so remove them now.

Change-Id: I77394be5459d55a9f16e7bd2b3c9d688c4605b4f
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-01-12 09:46:25 -06:00
Erwan Gouriou
219a1e7f0b stm32f4: Update flash to support higher sysclock frequencies
stm32f411re SoC could run at system clock above 84MHz.
This was not taken into account in __setup_flash function which configure
flash latency depending on system clock. This is now corrected.
Assert added to ease error detection.


Change-Id: I49b92256d611ef464171fb1d8812a4c4d3c27ab8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-01-12 09:46:25 -06:00
Gil Pitney
9bc293c827 cc3200: Use peripheral driver library functions from ROM
Previously, CC3200 drivers had two options to use the peripheral
driver library APIs:
1) Build driverlib SDK files in Zephyr, in ext/hal/ti/cc3200/*
2) Link directly with the driverlib.a, from an externally installed
   TI CC3200 SDK.

A new option is added to replace option 2), and is now the default:
3) Use the driverlib functions already provided in ROM.

This enables a savings in code size, which will depend on the
types of device drivers configured and the number of SDK
APIs actually used.

A rom_report build of the shell sample application showed
a savings of about 2kb in code space using this new config option.

Change-Id: Ie1ede6f7aacd23db20f5292e776f1dfeab5c7fe0
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-12 09:46:25 -06:00
Marcus Shawcroft
84cb997c62 arm: Adjust cortex-m7 support to reflect its ARMv7-M architecture.
The cortex-m7 is an implementation of armv7-m.  Adjust the Kconfig
support for cortex-m7 to reflect this and drop the unnecessary,
explicit, conditional compilation.

Change-Id: I6ec20e69c8c83c5a80b1f714506f7f9e295b15d5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-12 09:46:25 -06:00
Marcus Shawcroft
ef8200dfcd arm: Replace CONFIG_CPU_CORTEX_M3_M4 with CONFIG_ARMV7_M
Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.

Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-12 09:46:25 -06:00
Marcus Shawcroft
727dc2c5d6 arm: Replace CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M
Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.

Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-12 09:46:25 -06:00
Marcus Shawcroft
e2d3cc4b81 arm: Restructure ARM cpu related preprocessor conditionals.
The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices.  M0_M0PLUS,
M3_M4 and M7.  Throughout the code base we have conditional
compilation gated around these three choices.  Adjust the form of this
conditional compilation to adopt a uniform structure.  The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.

Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.

Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for.  This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.

This change is mechanical in nature involving two transforms:

1)

  #if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...

2)

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #else
  ...
  #endif

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...
  #else
  #error Unknown ARM architecture
  #endif

Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-12 09:46:25 -06:00
Marcus Shawcroft
3de84ae88e arm: Fix assembler layout.
Adjust the layout of various ARM assember files to conform to the norm
used in the majority of files.

Change-Id: Ia5007628be5ad36ef587946861c6ea90a8062585
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2017-01-12 09:46:25 -06:00
Chuck Jordan
ce368f72a4 arc: i-cache init moved much earlier
I've moved the call for icache_setup from nanoArchInit() to
_PrepC(), because there is a lot of code executed now before
nanoArchInit() is called, and all this time the i-cache would
be off.  It should be turned on as early as possible to make
initialization faster.

Change-Id: I76a809d57a1bf9aacf51e7bb9fe8c8425f37aa13
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2017-01-11 15:22:04 +00:00
Anas Nashif
6bea1becab build: move qemu definitions to boards
Change-Id: I4e87dbd6eea8320f23e5691c1762a7353240a5c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-01-10 20:20:47 +00:00
Johan Hedberg
183e417efa arch: arm: Use smaller ISR stack size for 16k nRF51 SoCs
The 16k RAM nRF51 variants pose a challenge to get applications to fit
within the available memory. Make the default ISR stack size smaller
than the previous 2k default, but big enough to run fully functional
Bluetooth controller and host stacks.

Change-Id: Ie7c5bb21a3ba620d283e6228a2482d280f85119d
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2017-01-09 21:28:23 +00:00
Kumar Gala
b7386c3a26 arm: nordic_nrf5: Cleanup Kconfig dependencies for timer and clocks
On the nRF5x platforms we need always need the NRF_RTC_TIMER and it
depends on the CLOCK_CONTROL_NRF5.  So enable all of these always.

Fixes issues if one tries to build nRF5x platforms w/o CONFIG_BLUETOOTH.

Change-Id: I0f9af785e785f37ec289a935ddf70ee6dec08cd4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-09 20:55:10 +00:00
Benjamin Walsh
168695c7ef kernel/arch: inspect prio/sched_locked together for preemptibility
These two fields in the thread structure control the preemptibility of a
thread.

sched_locked is decremented when the scheduler gets locked, which means
that the scheduler is locked for values 0xff to 0x01, since it can be
locked recursively. A thread is coop if its priority is negative, thus
if the prio field value is 0x80 to 0xff when looked at as an unsigned
value.

By putting them end-to-end, this means that a thread is non-preemptible
if the bundled value is greater than or equal to 0x0080. This is the
only thing the interrupt exit code has to check to decide to try a
reschedule or not.

Change-Id: I902d36c14859d0d7a951a6aa1bea164613821aca
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-09 20:52:25 +00:00
Benjamin Walsh
f955476559 kernel/arch: optimize memory use of some thread fields
Some thread fields were 32-bit wide, when they are not even close to
using that full range of values. They are instead changed to 8-bit fields.

- prio can fit in one byte, limiting the priorities range to -128 to 127

- recursive scheduler locking can be limited to 255; a rollover results
  most probably from a logic error

- flags are split into execution flags and thread states; 8 bits is
  enough for each of them currently, with at worst two states and four
  flags to spare (on x86, on other archs, there are six flags to spare)

Doing this saves 8 bytes per stack. It also sets up an incoming
enhancement when checking if the current thread is preemptible on
interrupt exit.

Change-Id: Ieb5321a5b99f99173b0605dd4a193c3bc7ddabf4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-09 20:52:24 +00:00
Benjamin Walsh
1774f62eda nios2: remove unused INT_ACTIVE/EXC_ACTIVE thread flags
Change-Id: I884e87107cf30a6b8a064bc1da3c1ea26380fe03
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-06 17:32:25 +00:00
Benjamin Walsh
d779f3d240 kernel/arch: streamline thread flag bits used
Use least significant bits for common flags and high bits for
arch-specific ones.

Change-Id: I982719de4a24d3588c19a0d30bbe7a27d9a99f13
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-06 17:32:24 +00:00
Benjamin Walsh
e6a69cae54 kernel/arch: reverse polarity on sched_locked
This will allow for an enhancement when checking if the thread is
preemptible when exiting an interrupt.

Change-Id: If93ccd1916eacb5e02a4d15b259fb74f9800d6f4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-06 17:32:24 +00:00
Juro Bystricky
af6d817428 Makefile (arc/soc/quark_se): New compiler options
GCC 6.x for ARC does not recognize the options
    -mARCv2EM and -mav2em anymore.

Both options replaced in Makefile by -mcpu=quarkse_em.

Change-Id: I9dec26dd64b4738976704a39455fe4241406db9e
Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-05 11:26:21 -08:00
Juro Bystricky
51859d27e9 Makefile (arc/soc/em*): New compiler options
GCC 6.x for ARC does not recognize the options
-mARCv2EM and -mav2em anymore.

Both options replaced in Makefile by -mcpu=arcem.

Change-Id: Ic86bf51cd5fb1a67ba2cd75998cd907e26996347
Signed-off-by: Juro Bystricky <juro.bystricky@intel.com>
2017-01-05 11:26:21 -08:00
Andrew Boie
fb2e5a4479 arc: add -fno-delete-null-pointer-checks
This option has side effects. It also tells the compiler not to generate
these checks in the first place. The checks call abort() which doesn't
exist in our environment.

This patch gets rid of linker errors due to missing abort() in the 0.9 SDK.

Change-Id: Ibc5aeb5458d0bded714c9c074cdf08112733428b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-01-04 19:06:41 +00:00
Carles Cufi
b6109496ff arm: Cortex-M0: Adapt core register code to M0
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.

Jira: ZEP-1497

Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-03 22:44:35 +00:00
Anas Nashif
fad7e2dd8d logging: move event_logger to subsys/logging
Jira: ZEP-1337
Change-Id: If1690e19a882cf53caaa3418ccabeb49c783f63d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-25 14:34:43 -05:00
Anas Nashif
c1347b4730 kernel: replace all remaining nanokernel occurances
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.

Keep the legacy samples/tests as is.

Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-25 14:34:43 -05:00
Baohong Liu
db09c2905b drivers: i2c_shim: grant arc the access to i2c on I/O fabric
Enable arc to access the i2c controller on I/O fabric.

There are two i2c controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the i2c controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.

1. Add i2c_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
   and do interrupt unmasking automatically based on the
   compilation targets.
3. Add new symbols in Kconfig including driver names for both
   controllers

Jira: ZEP-1189

Change-Id: I317da6038c50e0c8bd16f446182c1f8bdf6d3ba2
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-12-22 01:22:52 +00:00
Baohong Liu
e1153004f9 drivers: spi_shim: grant arc the access to spi on I/O fabric
Enable arc to access the spi controller on I/O fabric.

There are two spi controllers on quark se SoC. One is attached
to the I/O fabric and the other one is in the sensor system.
X86 cpu is only able to access the spi controller on the I/O
fabric and the access is supported by existing code. HW allows
arc to access both controllers. But, the existing code only
gives arc access to the controller in the sensor sub-system.
Let's grant arc the access to the controller on I/O fabric as
well by the following changes.

1. Add spi_qmsi.c into arc compilation.
2. Use the already defined macros to choose interrupt numbers
   and do interrupt unmasking automatically based on the
   compilation targets.
3. Add new symbols in Kconfig including driver names for both
   controllers

Jira: ZEP-1190

Change-Id: I40a5d423d4b7986a897834d1a3831938005eda6f
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-12-22 01:22:26 +00:00
Baohong Liu
b4114259d6 driver: pwm: give arc the access to pwm
HW allows both arc and x86 to access the pwm attached to the
quark soc I/O fabric. The existing code only allows x86 to
do this. Let's give arc the access.

Change-Id: Ie88649fea41bf86b84876c260f97dd4c12fd0b81
Signed-off-by: Baohong liu <baohong.liu@intel.com>
2016-12-22 01:21:23 +00:00
Benjamin Walsh
bfa5653e9a arch: remove instances of fiberRtnValueSet()
Obsolete, replaced by _set_thread_return_value().

Change-Id: I23e9cfc07e43542f0965817edc3552d456fd2ef3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-21 19:50:08 +00:00
Anas Nashif
3d8e86c12c drivers: eliminate nano/micro kernel usage
Jira: ZEP-1415

Change-Id: I4a009ff57edb799750175aef574a865589f96c14
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-21 18:45:02 +00:00
Flavio Santes
d8083e92ab arch/arc, usb, ztest: Add the ARG_UNUSED macro
Add the ARG_UNUSED macro to avoid compiler warnings.

Change-Id: Ie07f52e742bdb93fb35301bd50cce3865f229623
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-21 12:54:54 +00:00
Matthias Boesl
ffa67b77c6 board: add initial support for Nucleo-64 with Soc STM32F411RE
Change-Id: I698693bccce1e9599c20e57f5d4172643ca38cc9
Signed-off-by: Matthias Boesl <matthias.boesl@gmail.com>
2016-12-20 09:15:19 -06:00
Gil Pitney
8b93aaa229 cc3200: Move UART peripheral clock enable into soc init
Previously, UART clock enable was done in pinmux init.

This is now moved into soc initialization, along with other
power related initialization routines.

Change-Id: I1f9464655ad966e9caac2d238006f12a06b202ab
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-12-20 09:14:49 -06:00
Carles Cufi
3655291d5f boards: arm: Refactor the GPIO and UART dependencies
To make way for the upcoming blinky and GPIO support for nRF5x-based
boards, this change addresses the hardcoded dependencies in Kconfig
default configurations of the different boards, moving the common option
defaults to the SoC default configuration itself.

Change-Id: I8db0750311ad5a12b76237b39438376f20f6f496
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-20 09:14:48 -06:00
Gil Pitney
f18cced2c1 cc3200: Add a GPIO driver for the TI CC3200 LaunchXL
The pinmux configuration is done during board initialization.

This was validated using the following Zephyr apps:
 - samples/basic/blinky
 - samples/basic/disco
 - samples/basic/button

All 4 GPIO ports are supported.

Change-Id: If8599a23c1d56cfd678a6e2e5339f7e093c6061a
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-12-20 09:14:48 -06:00
Carles Cufi
ce8629c92b arch: arm: Add support for the Nordic nRF52840 IC
The new Nordic nRF52840 IC is the latest member of the nRF52 family.
It supports the following features among others:

    * Cortex-M4F core at 64MHz
    * 1024KB of flash and 256KB of RAM
    * Bluetooth 5-ready and 802.15.4 compatible radio
    * USB device support
    * NFC Tag support
    * Quad-SPI
    * Hardware accelerated crypto engine

http://www.nordicsemi.com/eng/Products/nRF52840

JIRA: ZEP-1418

Change-Id: I677c787bb33d02695e057d5dced7e3455b9f6c50
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-12-20 09:14:48 -06:00
Carles Cufi
c5d2c4a65d arch: arm: Refactor and cleanup nRF52 series arch code
In preparation for the upcoming nRF52840 support, this patch refactors
the nRF52 series support code to allow for future members of the IC
family to be added, while keeping everything that is common together.

JIRA: ZEP-1418

Change-Id: I4200064ca888d72ba0b8629ce94e4ea6384099ad
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-20 09:14:48 -06:00
Anas Nashif
87133d5def debug: gdb: move to new kernel APIs
Change-Id: Ifed1fe7c60fa150ee3ef4fefabafeb95312bf8bc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 14:59:35 -05:00
Anas Nashif
d687a95611 kernel: move kernel code to kernel/ directly
Also remove mentions of unified kernel in various places in the kernel,
samples and documentation.

Change-Id: Ice43bc73badbe7e14bae40fd6f2a302f6528a77d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 14:59:35 -05:00
Anas Nashif
0d775bcd9c x86: remove obsolete comment about tasks/fibers
Change-Id: Iff911329f5c981d0d47880924e8a4d52478423fd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:42 +00:00
Anas Nashif
569f0b4105 debug: move debug features from misc to subsys/debug
Change-Id: I446be0202325cf3cead7ce3024ca2047e3f7660d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:40 +00:00
Anas Nashif
a9e879e273 logging: move sys_log to subsys/logging
Move logging out of misc/ to its own subsystem. Anything related to
logging and any new logging features or backends could be added here
instead of the generic location in misc/ which is overcrowded with
options that are not related to eachother.

Jira: ZEP-1467
Change-Id: If6a3ea625c3a3562a7a61a0ba5fd7e6ca75518ba
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:39 +00:00
Anas Nashif
cfbe9b05a1 kernel: rename NANOKERNEL_TICKLESS_IDLE_SUPPORTED
rename NANOKERNEL_TICKLESS_IDLE_SUPPORTED to
TICKLESS_IDLE_SUPPORTED and remove nanokernel occurances in Kconfig
files.

Make TICKLESS_IDLE depend on hardware that supports it.

Change-Id: I6a2e4fb0f7cf4b45475b48e71823ea089ee98759
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:35 +00:00
Anas Nashif
f855d3558f kernel: remove unused and obsolete headers
Change-Id: I25fd7c9e3db2d171a4118a57c4d9544d2424b819
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:03 +00:00
Anas Nashif
cb888e6805 kernel: remove nano/micro wording and usage
Also remove some old cflags referencing directories that do not exist
anymore.
Also replace references to legacy APIs in doxygen documentation of
various functions.

Change-Id: I8fce3d1fe0f4defc44e6eb0ae09a4863e33a39db
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:03 +00:00
Anas Nashif
5ad2905532 arm: remove old GDB_INFO support
That module is not used anymore: it was introduced pre-Zephyr to add
some kind of awareness when debugging ARM Cortex-M3 code with GDB but
was never really used by anyone. It has bitrotted, and with the recent
move of the tTCS and tNANO data structures to common _kernel and
k_thread, it does not even compile anymore.

Jira: ZEP-1284, ZEP-951

Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:17:30 +00:00
Marcus Shawcroft
6f74a4a3dc k64f: Default the ETH_KSDK on if NET_L2_ETHERNET enabled.
The K64F board has the ENET ethernet driver.  Behavior consistently
with other driver selection logic and default the KSDK ethernet driver
on if ETHERNET drivers are enabled.

Change-Id: I2fbed7fdef22d75cf163b61b3e0530ce00d988f0
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-19 10:25:57 +00:00
Benjamin Walsh
cef368f578 kernel/arch: rename ARCH_HAS_NANO_FIBER_ABORT to ARCH_HAS_THREAD_ABORT
And also remove now obsolete ARCH_HAS_TASK_ABORT.

ARC does not need the options either.

Change-Id: Ie52d63178a367ce12b911dacfe2d389f4f75ed2d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-17 22:44:40 +00:00
Benjamin Walsh
b12a8e0914 kernel: introduce single-threaded kernel
For very constrained systems, like bootloaders.

Only the main thread is available, so a main() function must be
provided. Kernel objects where pending is in play will not behave as
expected, since the main thread cannot pend, it being the only thread in
the system. Usage of objects should be limited to using K_NO_WAIT as the
timeout parameter, effectively polling on the object.

Change-Id: Iae0261daa98bff388dc482797cde69f94e2e95cc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:39 -05:00
Benjamin Walsh
48db0b3443 arch/all: simpler _SysFatalErrorHandler()
- does not pull in printk(), for potential footprint gain
- does not pull in k_thread_abort(), for single-threaded systems

Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: Ibc6a198b81a6cd73117d1e85aa05b92a4501a34d
2016-12-15 16:17:39 -05:00
Benjamin Walsh
8e4a534ea1 kernel: enable and optimize coop-only configurations
Some kernel operations, like scheduler locking can be optmized out,
since coop threads lock the scheduler by their very nature. Also, the
interrupt exit path for all architecture does not have to do any
rescheduling, again by the nature of non-preemptible threads.

Change-Id: I270e926df3ce46e11d77270330f2f4b463971763
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh
c3a2bbba16 kernel: add k_cpu_idle/k_cpu_atomic_idle()
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.

The kernel internals now make use of these APIs instead of the legacy
ones.

Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh
88b3691415 kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.

However, this caused two problems:

1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.

2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.

To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.

On the ARM FRDM K64F board, this improvement is seen:

Before:

1- Measure time to switch from ISR back to interrupted task

   switching time is 215 tcs = 1791 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 315 tcs = 2625 nsec

After:

1- Measure time to switch from ISR back to interrupted task

   switching time is 130 tcs = 1083 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 225 tcs = 1875 nsec

These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.

Fixes ZEP-1401.

Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:50:02 -05:00
Benjamin Walsh
e6ebe3a8b4 arm: relinquish one IRQ priority reserved by kernel
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.

Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:10 +00:00
Benjamin Walsh
c016252108 arm: add CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS kconfig flag
Cortex-M0/M0+ do not have other faults than the hard fault at priority
-1, so they do not need to reserve a priority to allow exceptions to
trigger during handling of ISRs.

Change-Id: I479e439f7bcac70b4b2b787bcd744a4c65437e80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:09 +00:00
Benjamin Walsh
f5d0cbe8ad arm: move IRQ_PRIORITY_OFFSET to header file, rename to _IRQ_PRIO_OFFSET
This allows using it in _EXC_PRIO() instead of hardcoding 2 and 3.

Change-Id: I3549be54602643e06823ba63beb6a6992f39f776
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:08 +00:00
Benjamin Walsh
194a2e3a12 arm: add CPU_CORTEX_M_HAS_BASEPRI kconfig flag
Use it to flag which CPUs can do zero latency interrupts, which depend
on being able to lock up to a specific interrupt priority.

Change-Id: I09f71366ea1d05486e38c513a09abc270884879f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:57:07 +00:00
Julien Delayen
176d184fb8 power: Add ARC core suspend and resume support
When going into DEEP_SLEEP mode, the ARC core now saves
its context. This includes:
- All core registers
- Stack pointer
- Program counter (restored by jumping to the restore code)

The arc reset code now checks if the GPS0 bit 2 is set.
This is similar to the behavior of the x86 core done by
the QMSI bootloader which is setting GPS0 bit 1 in order
to call the restore path instead of cold boot path.

The sample has been adapted in order to support the ARC.

Jira: ZEP-1222

Change-Id: I375f03b16b8a5fd1f07ead55cf7e4947d6290c9f
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:33 +00:00
Julien Delayen
cd8504cc9c arcv2_irq: Add power management suspend/resume
In order to resume the ARC from deep sleep,
the interrupts need to be restored.

The FIRQ stack needs to be saved and restored
when performing sleep operations.

During early initialization, the sp in the 2nd register bank
is made to refer to _firq_stack.
This allows for the FIRQ handler to use its own stack.
Fast Interrupts cannot be used after sleep if this information
is not restored.

This patch adds the suspend and resume functions.

Jira: ZEP-1223

Change-Id: Ic81980f05aee6c1f7b8c46c743f2648c65b29486
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:31 +00:00
Julien Delayen
2008af30e7 arc: Define _arc_v2_irq_unit device
Move interrupt initialization for the ARC to its own
device. The init function for the arc will be only
doing platform specific operations

Jira: ZEP-1288

Change-Id: Icb04c3622890021c65cd24cecf6cafee6c37caf9
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-15 12:49:30 +00:00
Julien Delayen
60f5d4ef05 arc: Add cc to clobber list for sleep instruction
As flags are modified when entering sleep, add cc to
clobber list.

Jira: ZEP-1408

Change-Id: Ia80bc1c7ddedb9d9963c47108372a90928597c1d
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-12-12 22:06:29 +00:00
Flavio Santes
59c8f32f0f x86/soc: Add ARG_UNUSED macro to avoid compiler warnings
The ARG_UNUSED macro is added to avoid compiler warnings.

Change-Id: If0242548849ee5b258bb3fce9fd727b377411343
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-12 20:02:30 +00:00
Marcus Shawcroft
362fb9e62b arm: Fix irq offload inline asm memory ordering.
Add a "memory" clobber to inline asm SVC call to ensure the compiler
does not reorder the instruction relative to other memory accesses.

Issue found by inspect the source code.  There is no evidence to
suggest that this bug will manifest for any current ARM target using a
current compiler.

Change-Id: I32b1e5ede02a6dbea02bb8f98729fff1cca1ef2a
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-11 11:19:02 +00:00
Marcus Shawcroft
a94437c03c sensor: Add nRF5 temperature driver.
Basic interrupt driven driver for the nRF5 onboard temperature sensor.

Change-Id: Id0ac303293b8e8b8285b19bcda31284ee6617105
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-12-11 11:14:05 +00:00
Maureen Helm
4a1c31a790 k64: Change the default pinmux driver to the ksdk one
Stop using the specific k64 pinmux driver by default and start using the
more generic ksdk pinmux driver instead.

Jira: ZEP-1393
Change-Id: Id65b59518c386e6ba33cfa5c4c5bd541664d2b41
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-12-10 21:14:12 +00:00
Erwan Gouriou
2695efa90a soc: stm32xx: add pwm pinmux support
Following pinmux update for PWM support,
update soc to support this new configuration.

Change-Id: I1126e347ab1ab6b2d830993e548de8f32fa2f8f9
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 10:31:46 -06:00
Vincenzo Frascino
c4e5126519 soc_beetle: Add initial PM configuration
This patch adds the boot time Power Management configuration for Beetle
on Zephyr. In particular it defines the states of the peripherals during
sleep and deep sleep and the allowed wakeup sources.

Jira: ZEP-1300
Change-Id: Iad9c0f851771ea60d94bbe5420b7b3ee0743b77e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
c14867069a stm32l4: add pinconf settings for I2C
Add one pin configuration for I2C1 of the STM32L4 series.

Change-Id: Id05d916f2a1126ca439aebcddd8dc9c91015f6fe
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
d4b69847a8 stm32l4: add pinconf for USARTs
Add the pin configuration of the USARTs.

Change-Id: Idf7a18b6eab95c61870ad4850c9eafb1fdcab03d
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:45 -06:00
Neil Armstrong
3842c60ce3 stm32l4: add clock control driver
Add the clock driver for the STM32L4 series.

Change-Id: Icdf79061f163d8d00187b382d1564422fb875c5b
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-12-06 10:31:41 -06:00
Neil Armstrong
8833e44f6d stm32l4: add initial soc support for stm32l4
Add the initial SoC support for the STM32L4XX family. The code was
tested on STM32L476RG, but should work on any STM32L4XX currently
available.

This implementation was inspired by the stm32f1x implementation.

Change-Id: Id6670bce0c423617284e8467a9c461531f948e0f
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
2fcf3435c1 serial: Provide new numbering scheme for stm32 UART
There was a misalignment between Zephyr UART device numbering and
SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could
be confusing for user.
This commit allows to align "UART_1" to IP USART_1.
Change is propagated to all STM32F103RB/STM32F401RE based boards and
respective pinmux drivers

Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
575207c6ff stm32f4: Update after serial driver rework
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore

Change-Id: Ia9f9b0a2a63280c0221c789a53ff7338bda17dfb
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
293b3e18bd stm32f1: Update after serial driver rework
Due to new serial driver implementation based on STM32Cube we can
remove the USARTX_ADDR defines as they aren't ended anymore

Change-Id: Icd5b7995429025c5b54b1a04ca6abb9649ab31c8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Erwan Gouriou
8c079e91c9 serial: Provide STM32Cube based serial driver on stm32f1, stm32f4
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.

Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-12-06 09:50:11 -06:00
Flavio Santes
91aa33ba11 arch/x86: Remove unused parameter warning
This patch fixes the unused parameter warning found at the
quark_x1000/soc.h file.

Change-Id: I110d7185d8302f95d14efd13060055e7378aea23
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-03 14:49:10 +00:00
Flavio Santes
cf09370d4e arm: Remove unused parameter warning
This patch fixes the unused parameter warning found at the
arch/arm/core/fault.c and arch/arm/soc/st_stm32/stm32f1/soc_gpio.c
files.

Change-Id: I5b3013c1514cff30f4e98feb31169fb28546c534
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-03 14:49:09 +00:00
Ramesh Thomas
3cabbfd081 quark_se_ss: power_mgmt: fix sleep mem ordering bug
Memory access could be reorderd around sleep. Add memory
in clobber list.

Jira: ZEP-1408
Change-Id: I49df2542e0059ba76a262fbda58eb46b86e89bea
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-12-03 13:50:31 +00:00
Chuck Jordan
cd198764ba arc: branch too far when STACK_CHECKING enabled.
A build error was resulting if CONFIG_ARC_STACK_CHECKING is enabled.
There is a breq that was too far. Adding conditional code to
re-arrange the branching so that it can be done.

See ZEP-1116.

Change-Id: Idea85817b2e05617bbaa4450437aa74c5737e213
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-12-02 22:57:14 +00:00
Ramesh Thomas
aae7ac0765 quark_se_ss: power_mgmt: Remove redundant int trigger setting
Zephyr is always setting irqs to be level triggered as
required by the core. It is unnecessary to set it to
level again while entering sleep states.

Change-Id: I10f919d619af2e1ab05dc85a67766929b6ae9402
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-12-02 14:03:06 +00:00
Benjamin Walsh
4e8a54c1e3 arc: move disabling/invalidation of caches earlier
Too much code might run with a stale icache, before _PrepC(), so move
the invalidation/disabling code earlier. The asm code does the exact
same thing disable_icache() and invalidate_dcache() were doing.

Change-Id: If52f4e4a1de546fb82873c91ead95614a44b106d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-30 23:47:46 +00:00
Marcus Shawcroft
64c69d585f Fix Kconfig formatting.
Change-Id: I5720efb9455740a95ea785b0cd205875a215b922
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-11-30 17:01:46 +00:00
Andrew Boie
452fd7a5c2 x86: don't set segment registers if we don't set GDT
We have no idea what's in the GDT if we don't set it ourself.

Change-Id: I3c2e406370e3ea149252c423d66c97aab95bee17
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-29 14:51:57 -08:00
Benjamin Walsh
eba017632a arm/frdm_k64f: fix boot issue with MBED bootloader and INIT_STACKS=y
Initializing the interrupt stack before initializing (turning off) the
watchdog on the FRDM board pushed the initialization of the watchdog too
late, causing it to fire and reset the board. The board would be kept in
a reboot loop.

Move the initialization of the watchdog earlier: this runs on the main
stack now, instead of the interrupt stack, the same stack the interrupt
stack initalization code runs on.

Change-Id: Ic0006f4f4f4090393571d8355a80dc9390c9fbc6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-28 18:33:11 +00:00
Ramesh Thomas
87a2b02189 quark_se_ss: power_mgmt: Fix a bug in call to sleep instruction
When sleep instruction is called with interrupts enabled, the
interrupt priority threshold bits need to be set. Only interrupts
with equal or higher priority will wake the sleep. Currently it
is set to 0 unintentionally and only priority 0 interrupt can
wake the sleep.

Jira: ZEP-1349
Change-Id: I927e259345cc37c5ecc4dfdcde996dd16443e61b
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-28 01:00:35 +00:00
Ramesh Thomas
4a09593714 quark_se: power_mgmt: Fixes a cpu context save bug
The cpu context save function was manipulating stack and
returning to C caller. This can corrupt stack if the calling
function has data saved and it pops before entering deep
sleep. Moved sleep functions into assembly to avoid this.

Jira: ZEP-1345
Change-Id: I8a6d279ec14e42424f764d9ce8cbbef32149fe84
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-28 00:59:51 +00:00
Vinayak Chettimada
a100ada866 drivers: timer: nRF SoC Series RTC system clock implementation
The nRF5x series SoCs do not implement systick, hence we disable
CORTEX_M_SYSTICK.
Instead, use nRF SoC Series NRF_RTC1 for system clock interfaces.
The kernel system clock interface is implemented using the low
power real time counter NRF_RTC1. NRF_RTC0 is used by the BLE
controller.

In addition, cleanup nRF5x series defconfig to be consistent.

Jira: ZEP-742
Jira: ZEP-1308
Jira: ZEP-1315

Change-id: I0f6cc1836fe0820a65f2cbb02cf5ae7e9eb92e1d
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-27 19:39:27 +00:00
Anas Nashif
92c5f91413 arm: systick: Some SoCs do not have systick
Make the systick feature optional that can be selected by the SoC.

Change-Id: I4a405640b84daecc17fc1882743d3cafb78ff861
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-27 19:39:26 +00:00
Benjamin Walsh
8641c9e6a5 arm: fix bug when Zero Latency Interrupts are enabled
An IRQ would always register as a ZIL interrupt.

Change-Id: If82a85f472a60512745652aacc7e8b7dfacaa268
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:19 +00:00
Benjamin Walsh
6741561ae4 arc: fix missing _firq_stack symbol when INIT_STACKS=y and NUM_BANKS=1
There is no FIRQ stack in the system in this case, so do not initialize
it.

Change-Id: I8bc068ce43ac8a39909994d8cc01ba0c6a17f4ae
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:19 +00:00
Benjamin Walsh
b2974a666d kernel/arch: move common thread.flags definitions to common file
Also remove NO_METRIC, which is not referenced anywhere anymore.

Change-Id: Ieaedf075af070a13aa3d975fee9b6b332203bfec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:18 +00:00
Benjamin Walsh
194f45cc66 arm: fix early boot on Cortex-M0 with init stack
The assembler was passed immediate values that are too large for the
limited Cortex-M0 thumb assembly. Load values in registers instead of
using immediate values.

Change-Id: Ib5541c92dea03e0efb1b88ab91eeb408d151a71b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-24 01:45:00 +00:00
Vincenzo Frascino
9f04723439 arm: Enable REBOOT when RUNTIME_NMI is selected
This patch enables REBOOT when RUNTIME_NMI is selected via defconfig
file. This action is required to prevent compilation errors.

Change-Id: I67c18b2860ac34ba8f96e780737b4857a6063ece
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-23 20:13:51 -05:00
Vinayak Chettimada
3bc143962c arm: make _timer_int_handler optional
If CORTEX_M_SYSTICK is not selected, do not reference
_timer_int_handler. SoC will need to define a custom system
clock implementation.

Change-Id: I655f3abf66953e434fef69ed16db2d9c2dcc486e
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-23 20:13:31 -05:00
Vincenzo Frascino
4d8c021820 arm: Fix CONFIG_RUNTIME_NMI behavior
Zephyr kernel is unable to compile when CONFIG_RUNTIME_NMI is enabled in
defconfig on ARM's architectures.

This patch addresses the following issues:
* In nmi.c _DefaultHandler() is referencing a function
(_ScbSystemReset()) not defined in Zephyr. This has now been replaced
with sys_arch_reboot.
* nmi.h is included in ASM files and due to the usage of "extern" the
compilation ends with an error. Added the directive _ASMLANGUAGE to
prevent the problem.

Jira: ZEP-1319
Change-Id: I7623ca97523cde04e4c6db40dc332d93ca801928
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-11-23 00:27:56 +00:00
Benjamin Walsh
069fd3624e kernel: streamline initialization of _thread_base and timeouts
Move _thread_base initialization to _init_thread_base(), remove mention
of "nano" in timeouts init and move timeout init to _init_thread_base().
Initialize all base fields via the _init_thread_base in semaphore groups
code.

Change-Id: I05b70b06261f4776bda6d67f358190428d4a954a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:27:42 +00:00
Benjamin Walsh
50eb51a745 arc: support interrupt/FIRQ stacks with CONFIG_INIT_STACKS
Use the main stack during very early boot so that we can call memset on
the interrupt and FIRQ stacks. Iniitalize the them before one of them is
used for the rest of the pre-kernel initialization.

Change-Id: Ib57856a66273dda9382e08fa91da5a54847b77c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:24:01 +00:00
Benjamin Walsh
0c9268784e arm: support interrupt stack with CONFIG_INIT_STACKS
Use the main stack during very early boot so that we can call memset on
the interrupt stack. Initialize the interrupt stack before it is used
for the rest of the pre-kernel initialization.

Change-Id: I6fcc9a08678afdb82e83465cda1c7a2a8c849c9b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:24:01 +00:00
Benjamin Walsh
83e6df26f9 arc: use one of the interrupt stacks during early init
Same issue as with ARM. ARC can use _Swap() though, because the call to
it is serial, not generating a low-priority exception and interrupts are
locked until the main() thread is context-switched into and the
interrupt stack is released.

Fixes ZEP-1310.

Change-Id: Ie1f27f7ad0502191ca2867b5400d6e0bfb7f0fc6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:23:59 +00:00
Benjamin Walsh
7f4c294e5c arm: use interrupt stack during early init
The ARM Cortex-M early boot was using a custom stack at the end of the
SRAM instead of the interrupt stack. This works as long as no static
data that needs a known initial value occupies that stack space. This
has probably not been an issue because the .noinit section is at the
very end of the image, but it was still wrong to use that region of
memory for that initial stack.

To be able to use the interrupt stack during early boot, the stack has
to be released before an interrupt can happen. Since ARM Cortex-M uses
PendSV as a very low priority exception for context switching, if a
device driver installs and enables an interrupt during the PRE_KERNEL
initialization points, an interrupt could take precedence over PendSV
while the initial dummy thread has not yet been context switched of and
thus released the interrupt stack. To address this, rather than using
_Swap() and thus triggering PendSV, the initialization logic switches to
the main stack and branches to _main() directly instead.

Fixes ZEP-1309

Change-Id: If0b62cc66470b45b601e63826b5b3306e6a25ae9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:23:59 +00:00
Benjamin Walsh
8fcc7f69da kernel/arch: remove unused uk_task_ptr parameter from _new_thread()
Artifact from microkernel, for handling multiple pending tasks on
nanokernel objects.

Change-Id: I3c2959ea2b87f568736384e6534ce8e275f1098f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:23:57 +00:00
Tomasz Bursztyka
6d6c559001 arch: stm32f1: Fixing a typo
PA10 should use *_PA10_UART1_RX

Change-Id: Ifba4d301d049db1d62ea3a63d4d66f75c88a71a6
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-11-22 17:00:45 +00:00
Tomasz Bursztyka
28537c887b arch: stm32f1: Fix 80 char limit issue
Change-Id: I1d83c53d509eecf037efb0cafd7f5b5aefdf855d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-11-22 17:00:44 +00:00
Andrew Boie
2ffa516d89 x86: set accessed bit in ROM-based GDT
Previous configuration was backwards. From the Intel manual:

"If the segment descriptors in the GDT or an LDT are placed in ROM,
the processor can enter an indefinite loop if software or the
processor attempts to update (write to) the ROM-based segment
descriptors. To prevent this problem, set the accessed bits
for all segment descriptors placed in a ROM. Also, remove
operating-system or executive code that attempts to modify
segment descriptors located in ROM."

Only by some miracle has this not been causing problems.

Change-Id: I0bb915962a1069876d2486473760112102feae7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-19 00:57:04 +00:00
Benjamin Walsh
669360d5ec kernel: fix thread prio and stack size types in some APIs
Prio should be an int, since values are small integers, not a fixed-size
int32_t. It aligns with the prio parameters of the other APIs.

Stack size should be size_t.

Change-Id: Id29751b86c4ad7a7c2a7ffe446c2a96ae83c77bf
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-18 23:08:46 +00:00
Sergio Rodriguez
bad9665198 soc: stm32f1: gpio: Fix unnecessary else statement
The bitfield determining the I/O direction already defines the pin
as either input or output, cannot be none or both at the same time

This issue was reported by Coverity

Coverity-CID: 151970

Change-Id: I18d5387139d6834004ba3269c5b54176bdc97ea7
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
2016-11-18 02:03:53 +00:00
Benjamin Walsh
32698293c8 kernel/arm: fix race condition when setting _Swap() return value
There was a possible race condition when setting the return value of a
thread that is pending, from an ISR.

A kernel function causes a thread to pend, with the following series of
steps:

- disable interrupts
- move current thread to wait_q
- call _Swap

Depending if running on M3/4 or M0+, _Swap will either issue a svc #0,
or pend PendSV directly. The same problem exists in both cases.

M3/4:
__svc will:
- enable interrupts
- trigger __pendsv

M0+:
_Swap() will enable interrupts.

__pendsv will:
- save register context including PSP into the thread struct

If an interrupt occurs between interrupts being enabled them and
__pendsv saving PSP, and the ISR sets the pending thread's return value,
this will happen:

- sees the thread in a wait_q
- removes it
- makes it ready
- calls _set_thread_return_value
- _set_thread_return_value looks at the thread's saved PSP to poke
  the value

In this scenario, PSP hasn't yet been updated by __pendsv so it's a
stale value from the previous context switch, resulting in unpredictable
word on the stack getting set to the return value.

There is no way to fix this issue and still have the return value being
delivered directly in the pending thread's exception stack frame, in the
M0+ case. There will always be a window between the unlocking of
interrupts and PendSV being handled. On M3/4, it could be possible with
the mix of SVC and PendSV, since the exception stack frame is created in
the __svc handler. However, because we want to keep the two
implementations as close as possible, and there were talks of moving
M3/4 to using PendSV only, to save an exception, the approach taken
solves both cases.

The approach taken is similar to the ARC and Nios2 ports, where
there is a field in the thread structure that holds the return value.
_Swap() then loads r0/a1 with that value just before returning.

Fixes ZEP-1289.

Change-Id: Iee7e06fe3f8ded84aff918fd43408c7f589344d9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-17 14:46:12 +00:00
Inaky Perez-Gonzalez
11bd718733 fatal error handlers: report which thread croaked
When a thread dies, at least print the pointer to it, so we can debug
better.

Change-Id: Ief6bbc0c221e2d5271c240a4b73df16413aa5e22
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-11-17 14:36:50 +00:00
Allan Stephens
c98da84e69 doc: Various corrections to doxygen info for Kernel APIs
Most kernel APIs are now ready for inclusion in the API guide.
The APIs largely follow a standard template to provide users
of the API guide with a consistent look-and-feel.

Change-Id: Ib682c31f912e19f5f6d8545d74c5f675b1741058
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-16 21:43:16 +00:00
Benjamin Walsh
13f6a0c676 kernel/arm: fix missing interrupt lock around _is_next_thread_current()
This reverts commit

	"kernel/arm: add comment about _is_next_thread_current"

and fixes the interrupt locking issue.

The comment would have been right if only reads were done the ready
queue, but that is not the case. It turns out that the comment was written
ignoring the fact that _is_next_thread_current() updates the next thread
cache when fetching the next thread.

Change-Id: I21c9230f85f4f87a6bbf14fd4a9eb7e19b59f8c5
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-16 00:16:28 +00:00
Gil Pitney
34849b2424 cc3200: Remove CPU_HAS_FPU from cc3200 Kconfig.soc
Though Cortex-M4 could optionally have a floating point unit,
the MCU in the cc3200 in fact does not have an FPU.

Enabling CPU_HAS_FPU caused applications built with CONFIG_FLOAT=y
to crash during an early call to enable_floating_point().

This patch was validated by running microPython, which is one
such application.

Change-Id: I8bfd42c456524e152cbbb983001d9540d93fbe98
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-11-14 20:05:18 -08:00
Benjamin Walsh
dfa7ca4ee5 kernel/arm: add comment about _is_next_thread_current
Normally, _is_next_thread_current() must be called with interrupts
locked, but the ARM interrupt exit code does not have to do that. Add
explanation why.

Change-Id: Id383b47a055fdd6fbd5afffa52772e92febde98f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-15 00:44:15 +00:00
Anas Nashif
2367df8d59 drivers: update ipm driver to use unified kernel
Move away from legacy APIs and use unified kenrel instead.

Change-Id: Icae86beec66df1b041405cbe3455913630fc8ad1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-13 13:53:53 +00:00
Benjamin Walsh
f6ca7de09c kernel/arch: consolidate tTCS and TNANO definitions
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.

Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.

The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.

The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.

Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.

Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-12 07:04:52 -05:00
Allan Stephens
dd07b4779f kernel: Eliminate use of KERNEL_V2 configuration option
The unified kernel is now the only supported kernel, so this
option is unnessary. Eliminating this option also enables
the removal of some legacy code that is no longer required.

Change-Id: Ibfc339d643c8de16a2ed2009c9b468848b8b4972
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-12 12:04:39 +00:00
Jithu Joseph
fca0add22b console : usb: USB UART console output support
Add support for console output via the USB UART.
Note that console input via the USB UART doesnt work.

Adds a simulated poll method for UART interface exposed by USB.

Jira : ZEP-775

Change-Id: I357827ea52c027eb000baed80225f422df1f3358
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-11-12 01:39:30 +00:00
Chuck Jordan
73c5b2861e arc: trap handler should always check IRQ_ACT
Regardless of the number of interrupt priorities
supported, the exit of the trap handler can check
AUX_IRQ_ACT to see if it interrupted a FIRQ or IRQ.

Change-Id: I0b84d8298d3e6e437c934c01db4535fa8fe29458
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-11-11 21:37:18 +00:00
Ramesh Thomas
24f94ca49e quark-se: power_mgmt: Add a optional deep sleep resume handler
Some arduino 101 boards have old boot loader without context
restore boot flow feature. This handler will allow doing deep sleep
in those boards by jumping to the context restore code. This will
be disabled by default and can be optionally enabled by user.

Jira: ZEP-1258
Change-Id: I92e70550fd92c1cac42b3039d667fb0be8cf5bce
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:41:52 +00:00
Ramesh Thomas
a3dc53f2a6 power_mgmt: Do not notify deep sleep if bootloader does context restore
Some bootloaders have power management support to restoer context
upon resume from deep sleep. In such cases, the OS startup code
should call the notification hook. Create Kconfig flags to configure
this option.

Jira: 1257
Change-Id: I9f40c5fa077c2f17dc8e9f11604c3ed17e549ed5
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:40:53 +00:00
Ramesh Thomas
c0cd7acf34 power_mgmt: Simplify _sys_soc_resume notification
_sys_soc_resume hook is over loaded to handle to different
scenarios. It is primarily called to notify exit of kernel idling
after PM operations. It is also used to notify exit from deep sleep.
This is very confusing and also makes the implementation of the
hook function very difficult because of very different conditions
involved in the 2 different use cases. Further, users may not require
either or both use cases depending of their custom boot flow and
power state handling. To simplify, create a separate hook for the
purpose of deep sleep exit notification. Use the existing one to
only notify kernel idling exit after PM operations.

Jira: ZEP-1256
Change-Id: I96350199a0fd37f16590c8ee5302a94a3d71b8ba
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:40:52 +00:00
Vincenzo Frascino
df33a1e185 arm: soc: Add support for ARM Beetle SoC
Add SoC support for ARM Beetle platform.

Beetle is an ARM Cortex-M3 based SoC used on ARM V2M Beetle Boards.

https://www.arm.com/products/tools/development-boards/versatile-express/beetle_iot_evaluation_platform.php

This patch contains:
* The base SoC platform.
* The clock_init functionality.
* The system wide pin definitions.
* The configuarion for the drivers at SoC level (IRQs, PINs and
  Base Addr).

Jira: ZEP-1245
Change-Id: If15675935890711983e5ce37d49732b0462c3ec7
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-11-11 20:39:52 +00:00
Julien Delayen
6e71f1f6a3 power: Fix x86 wake up sequence
When waking up from C2LP state, the timer needs
to be reinitialized as we cannot know the time
that we spent in that state.
In order to reschedule the user application, expire it
as soon as we restart.

Change-Id: Id38a0de71e148ae8d9024a36d3983ab57b1e40d2
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-11 03:29:02 +00:00
Julien Delayen
f540cbc5c5 power: Add ARC power states and update sample
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.

States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled

Jira: ZEP-994

Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-11 03:28:54 +00:00
Anas Nashif
7cac3b9625 arch: arc: arm: sys_thread_self_get -> k_current_get
Change-Id: Iaa01b0d8733d76888524cfd258bacbd9c11142de
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-10 18:52:51 +00:00
Allan Stephens
bce8fbb61e kernel: Clean up of x86 floating point code
Updates x86 floating point support to reflect changes that have
been made in recent months.

* Many, many, many cosmetic changes (mostly revisions to comments).

* Elimination of unnecessary function aliases that were needed
  to support the task and fiber versions of certain APIs.

* Elimination of run-time code to enable a thread's "FP regs"
  option bit if the "SSE regs" option bit was set. The kernel
  now recognizes that the thread is using the FPU as long as
  either option bit is set. (If the thread has both option bits
  enabled this is the same as if only the "SSE regs" bit is set.)

Change-Id: Ic12abc54b6fa78921749b546d8debf23e7ad232d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-09 23:51:30 +00:00
Andrew Boie
56f561e15e arches: use new kernel APIs
Change-Id: I4b6f5264d5295ebf4278991a1f4e2141bef6602f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-09 20:49:40 +00:00
Andrew Boie
0b474eef9c kernel: deprecate old init levels
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.

New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.

Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.

Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-09 17:59:44 +00:00
Benjamin Walsh
3cc2ba9f9c kernel: add __ASSERT() for thread priorities
Verify the thread priorities are within the bounds when starting a new
thread and when changing the priority of a thread.

Change-Id: I007b3b249e4b80235b6439cbee44cad2f31973bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-08 20:27:31 -05:00
Benjamin Walsh
5986ec040b arc: fix race condition when returning from interrupt
A race condition would happend if a FIRQ interrupted a
return-from-interrupt from a RIRQ at the wrong moment: if a decision was
already taken which thread to context switch in and the FIRQ woke up
another thread of higher priority, the ready queue would be corrupted.

The solution is to lock interrupts at the moment the interrupt return
code starts looking at the kernel queues. Interrupts do not need to be
unlocked before exiting: the return-from-interrupt (rtie) instruction
will restore the correct interrupt locking state for the thread being
context switched in.

Change-Id: I777665c2faeca7b1f2a77ddd9ee2a520080bae88
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-08 22:50:14 +00:00
Andrew Boie
9b0ec51098 arc: remove CONFIG_NANOKERNEL code
Change-Id: I1978c067d422aebb52d736ac747443a06bd437c3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-08 22:02:46 +00:00
Andrew Boie
ee95dd22a4 x86: remove CONFIG_NANOKERNEL references
Change-Id: I8c6ca9189dd09133162816675e33332d6e5a34b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-08 22:02:45 +00:00
Iván Briano
f4764fc348 counter qmsi: Enable the driver to work on ARC
Jira: ZEP-1030

Change-Id: I3f5e26f399a163467ec8371802b7472d87416940
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-08 14:37:35 -02:00
Leandro Pereira
0be498db5c quark_se: Correctly wait for ARC_READY flag while initializing ARC
The bitwise AND operator was being applied to the boolean expression
"!shared_data->flags" instead of the whole expression because a
parenthesis was lacking.

This bug has been found using Coccinelle using the following spatch,
after finding a similar bug somewhere else in the code base:

      @@
      expression E1;
      expression E2;
      @@

      - !E1 & E2
      + !(E1 & E2)

No other instance of this defect has been found with this spatch.

Change-Id: I6b9ca092f4015c80ddc83c31ce540a92e67cdb11
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2016-11-07 22:22:00 +00:00
Chuck Jordan
381cb25f63 arc: cache.h support added for em7d and em11d SOC
An implementation to flush multiple d-cache lines has been added
per the top-level cache.h API. ZEP-1153 was opened to express
the need for MORE i-cache and d-cache APIs. For example, the current
cache.h API doesn't provide a means to invalidate d-cache lines
and has nothing for i-cache.

I've also modified some of the i-cache related aux registers to have
better names so that they won't be confused with d-cache.
These changes are for
ZEP-1176.

Change-Id: If4c5410451cc40dcd5618fc871093c8febf7e061
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-11-07 18:53:49 +00:00
Allan Stephens
f48f263665 kernel: Rename USE_FP and USE_SSE symbols
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.

Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-07 18:52:31 +00:00
Jorge Ramirez-Ortiz
27ecd5d8f3 drivers: flash: SoC KSDK
This KSDK flash shim driver supports the device in the FRDM K64F
platform (enabled with this commit).

WARNING: the driver disables the system interrupts for potentially
long periods of time. This is required to avoid Read-While-Write
issues since most platforms run in XIP mode.

For more detailed information see the link below:
http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf

Change-Id: I70f8d09080251033ce2f45be0c2eb95c19fded08
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
2016-11-07 18:43:16 +00:00
Anas Nashif
12ffc58d4b benchmarks: rename _NanoTscRead -> _tsc_read
Change-Id: Id5687f79ac13136f14a14d250e149436a0173f04
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-07 15:39:15 +00:00
Maureen Helm
33ee93d7dd serial/uart_k20: Fix instance source clock frequencies
The uart_k20 serial driver incorrectly assumed that all instances of the
UART peripheral are driven by the system clock, when actually some
instances are driven by the bus clock (which usually runs at half the
system clock). This caused incorrect baud rate calculations for UART
instances driven by the bus clock (UART2-4).

Change-Id: I38041781cdee146912bb5167e7c71d6416b966b5
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-11-04 23:00:04 +00:00
Andrew Boie
3a6bd2a552 arm: remove support for legacy kernels
Change-Id: I93c2dd6bf7286f50cb2702a94cbc85dc3bdee807
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-04 22:56:18 +00:00
Piotr Mienkowski
dccec68e0f arm: add missing atomic operations selection for Cortex-M7 processor
This change is required to support unified kernel.

Change-Id: I47bd644239eb3e624c7a5cb456eedad5aca79e8e
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2016-11-04 17:46:03 -05:00
Andrew Boie
a62d4be68b nios2: remove support for legacy kernels
Change-Id: If16533a478e5cd10f924eb6abe4b25c9902733c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-04 11:45:14 -07:00
Andrew Boie
8871cf0994 arc: remove support for legacy kernels
Change-Id: Id3d8285dc39428752758ee47fb1b826f05b1f3e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-04 11:45:14 -07:00
Andrew Boie
6e172b8abd x86: remove legacy kernel support
Change-Id: I81111a58d1305bd521ea93adc40c66b43f20977c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-04 11:45:13 -07:00
Benjamin Walsh
1bfa7e3d93 unified/arm: fix missing setting of default _Swap() return value
The unified kernel expect the default return value from a _Swap() call
to be set to -EAGAIN by the architecture code. Cortex-M3/M4 does this in
the SVC call handler, and it was missing from the Cortex-M0/M0+ before
pending PendSV.

Change-Id: I3316901186ab409f49043eb4f1972c4b0dd9a4a2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-04 17:51:14 +00:00
Gil Pitney
e8b43cbc81 cc3200: Add a UART driver (polled and interrupt modes)
The pinmux configuration is done during board initialization.

This was validated using the following Zephyr apps:
- samples/hello_world
- samples/philosophers
- samples/drivers/uart
- samples/shell

UARTA0 is currently supported.

Change-Id: I85727c622d4d42183cc9f2f8b43d653e245dd17e
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-11-04 14:53:33 +00:00
Gil Pitney
385c7be8af cc3200: Add support for the TI CC32xx SoC Series
Initial support is for the CC3200 SoC, comprising a network coprocessor
and Cortex-M4 MPU.

This leverages the CC3200 SDK driver peripheral library, installed
separately, or built from ext/hal/.

Jira: ZEP-1109

Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-11-04 09:38:50 +00:00
Maureen Helm
516d1286a6 k64: Move driver instance defconfigs to boards
The k64 SoC has multiple instances of many peripherals, but which
instances can actually be used depends upon the board design and pinmux
configuration.

Move all instance-specific default driver configurations from the SoC to
the boards (frdm_k64f and hexiwear_k64). Default driver selection
remains in the SoC (e.g., enable the KSDK I2C driver when I2C is
enabled).

This paves the way to support different driver defaults for the
frdm_k64f and hexiwear_k64 boards, but it does not yet change any of the
default values; it only changes where the default values get set.

Change-Id: Id9ed898762eb400ecefeac91ae4dce66da05622d
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-11-03 22:10:36 -05:00
Allan Stephens
a3f3de3741 unified: Rename ESSENTIAL to K_ESSENTIAL
Adds standard prefix to symbolic option that flags a thread
as essential to system operation.

Change-Id: Ia904a81ce343fdd1cd44caaaeae641d822777f9b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-04 00:47:08 +00:00
Julien Delayen
fec01af64a power: Update Quark SE PM layer with QMSI 1.3
QMSI 1.3 natively supports restoring the SoC and peripherals
after sleep.

The Zephyr Power Management shim layer is updated
in order to support QMSI functions.

The following functions have been added:
void _sys_soc_set_power_state(enum power_state);
void _sys_soc_power_state_post_ops(void);

In order to fully support deep sleep, the function
_sys_soc_set_power_state now support saving and
restoring CPU context and returns to the application.

_sys_soc_set_power_state function also abstracts
QMSI cpu states and enable the application to choose
between C1/C2 or C2LP states.

The QMSI power states are mapped as follows:
SYS_SOC_POWER_STATE_CPU_LPS -> power_cpu_c2lp
SYS_SOC_POWER_STATE_CPU_LPS_1 -> power_cpu_c2
SYS_SOC_POWER_STATE_CPU_LPS_2 -> power_cpu_c1
SYS_SOC_POWER_STATE_DEEP_SLEEP -> power_soc_deep_sleep
SYS_SOC_POWER_STATE_DEEP_SLEEP_1 -> power_soc_sleep

The following functions have been removed:
void _sys_soc_set_power_policy(uint32_t pm_policy);
int _sys_soc_get_power_policy(void);
FUNC_NORETURN void _sys_soc_put_deep_sleep(void);
void _sys_soc_put_low_power_state(void);
void _sys_soc_deep_sleep_post_ops(void);

Those changes are propagated to the samples.
All calls to QMSI are removed.

Jira: ZEP-1045, ZEP-993, ZEP-1047

Change-Id: I26822727985b63be0a310cc3590a3e71b8e72c8c
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-03 21:31:30 +00:00
Julien Delayen
5e87553079 quark_se: Add restore info shared memory to linker
A new shared memory has been added to the qmsi bootloader
in order to handle the restore flow and jump to
the restore trap where context is restored.

Add the new entry to the QUARK SE C1000 linker file
and new kconfig options:
- CONFIG_BSP_SHARED_RAM_ADDR to set the address of the
  shared memory.
- CONFIG_BSP_SHARED_RAM_SIZE to set the size of the
  shared memory.

This is only enabled with CONFIG_SYS_POWER_DEEP_SLEEP.

Jira: ZEP-1046

Change-Id: I35d924a100c5583025aa36a9741428ab51809c57
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-03 21:31:26 +00:00
Erwan Gouriou
f595df3755 stm32f4: Enable STM32Cube SDK support on stm32f4 family
Enable HAS_CUBE config flag on stm32f4 family soc.h is updated to
include minimum include files from ext/hal/stm23cube

Change-Id: I35a8c33aab777167ee7029edc1b7a4f6d21fccd8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-11-03 20:29:08 +00:00
Erwan Gouriou
dc70dc0977 stm32f1: Enable STM32Cube SDK support on stm32f1 family
Create HAS_CUBE config flag to control activation of STM32Cube support.
Generate fitting compilation options for STM32Cube in
/ext/hal/stm32cube/Makefile soc.h is updated to include minimum include
files from ext/hal/stm23cube

Change-Id: If58ce0a4fdb7fbf5f171dfe5f1f8eb75126a8313
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-11-03 20:29:07 +00:00
Erwan Gouriou
eed678612b clock_control: have FLASH_BASE compatible with ST CMSIS files
In ST CMSIS files, FLASH_BASE does not mean base address of FLASH register
Instead FLASH_R_BASE is used.
stm32f1 clock control driver is updated to be compatible with this naming.

Change-Id: Ic4fb49c60c392e15fd12c69266baf4c686bd343b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-03 20:29:07 +00:00
Erwan Gouriou
39f7adc41d stm32f4: Adapt CONFIG_SOC to STM32Cube values
STM32Cube uses SoC defines made to reflect HW heterogeneity that
should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f401re following define is used:
*STM32F401xE
Which means:
*Same SW could be used on STM32F401RE and STM32F401CE:
    same CONFIG_SOC could be used
*Different SW should be used on STMF401RE and STM32F401RC:
    different CONFIG_SOC should be used
This change focuses on stm32f4xx series.

Change-Id: I56ff4d1815d09747cf722385532eb2dcbdf37b44
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-03 20:29:06 +00:00
Erwan Gouriou
df5a2af34b stm32f1: Adapt CONFIG_SOC to STM32Cube values
STM32Cube uses SoC defines made to reflect HW heterogeneity
that should be taken into account by SW.
Aim of this commit is to adapt values used by Zephyr to the same
diversity. This will help create new SoC values only when justified
by a real hardware difference that should be taken into account
by software.
For instance, for SoC stm32f103rb following define is used:
*STM32F103xB
Which means:
*Same SW could be used on STM32F103RB and STM32F103VB:
    same CONFIG_SOC could be used
*Different SW should be used on STMF103RB and STM32F103R4:
    different CONFIG_SOC should be used
This change focuses on stm32f1xx series.

Change-Id: I5ecfaa52952d04421b27b5e74fb71b4fc108b662
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-03 20:29:06 +00:00
Iván Briano
f028973f43 gpio qmsi: Enable SoC level GPIO to work on ARC too
The GPIO and AON GPIO ports are available to both the x86 and ARC
cores, but the driver always assumed only the x86 at the time of
configuring interrupts.

Use the available macros to set the correct values independently of
which core it's being built for.

Jira: ZEP-1030
Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:56 +00:00
Iván Briano
34cf9773b1 gpio qmsi: Differentiate between the SoC GPIO and SS GPIO
The SoC level peripherals are accesible by both cores, while the SS
ones are only available to the sensor subsystem. Since the ARC core can
make use of both drivers at the same time, we need to be able to
differentiate their configuration values somehow.

Also disable the SoC GPIO for the ARC by default, as it still needs
more changes to be usable.

Jira: ZEP-1030
Change-Id: Ic5415c404ecd32a3e560467b6f5eaa873a515d72
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:52 +00:00
Iván Briano
5b2160b598 watchdog qmsi: Enable the driver to work on ARC
Jira: ZEP-1030
Change-Id: Iab5bb301dae9a18dc2050606f230606ef76bebb5
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:48 +00:00
Iván Briano
244af4a2af aio qmsi: Enable the driver to work on ARC
Jira: ZEP-1030
Change-Id: I614646053974d6a81579bbea9d969a10916f9cac
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:44 +00:00
Iván Briano
cb6cba2c70 dma qmsi: Enable the driver to work on ARC
Jira: ZEP-1030
Change-Id: I29f742762d92ca86361be9c9ed76e8cea21d58b6
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:40 +00:00
Iván Briano
b63e635a18 rtc qmsi: Enable the driver to work on ARC
Jira: ZEP-1030
Change-Id: Ie57b183c9fdf0e0cb70c7d81b92b221d54a32c0f
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:28 +00:00
Iván Briano
beb4f405d8 socs quark: Simplify IRQ configuration
IRQ numbers differ between x86 and ARC, as well as the bits that need to
be touched in the interrupt routing masks. QMSI abstracts some of it and
for the rest we do have the information needed.

Add a macro to select the right IRQ number based on which core we are
building for.

Change-Id: I3e6680d10a0a23c98777d2831efe6819fcb54162
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:27 +00:00
Andrew Boie
4208976bfc build: consolidate some common parts of linker scripts
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.

x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.

Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-10-31 18:00:58 -07:00
Chuck Jordan
8b1958a36a arc: Don't need CONFIG_NUM_REGULAR_IRQ_PRIO_LEVELS
We can derive NUM_REGULAR_IRQ_PRIO_LEVELS by subtracting 1
from CONFIG_IRQ_PRIO_LEVELS if FIRQ is present (which is currently
always the case). If FIRQ is not present, the value will be equal
to CONFIG_IRQ_PRIO_LEVELS since all interrupts will be regular.

Change-Id: Ibefc939e3771bf0adf712127db0d36cb49bf732b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-31 23:56:56 +00:00
Iván Briano
0094ab228d ext qmsi: Update to QMSI 1.3 release
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:

- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.

Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-10-31 13:26:06 +00:00
Amit Kucheria
fdfa958d5f boards: stm32f4: Extract common config options
Move common config options one level up to try to simplify the per-board
defconfig

Change-Id: I3d80fa494050634d0f877af2015b01b85df20d1d
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-28 18:58:06 +00:00
Amit Kucheria
eb0f8ab9fc boards: 96b_carbon: Add support for 96boards Carbon board
Add support for the STM32F401 chip on the board

Change-Id: I96c0799f3658ecea096fa5971bce9faf21919ee1
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-28 18:58:06 +00:00
Ricardo Salveti
1c1bd9a018 pinmux: stm32: add support for STM32F4
STM32F401 allows for upto 16 alternate functions on each pin.

Change-Id: Ib1c14fd31abaa2b05a5ab0f7bd1b4a4748f10f84
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-28 18:58:04 +00:00
Ricardo Salveti
cf59106433 gpio: stm32: add support for STM32F4
Implements MCU-specific GPIO input interrupt integration.  Added
definition of System configuration controller as well as its needed by
the GPIO code.

The SYSCFG controller is used for system-specific configuration such as:
 - remap the type of memory accessible at address 0x00000000
 - manage the external interrupt line connection to GPIOs
 - configure the I/O compensation cell

Change-Id: Id2ebfbd1b21e77be76406d1cd6cd5d4989e9e2fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-28 18:58:03 +00:00
Ricardo Salveti
3580a6bcec clock_control: stm32f4x: introduce driver for STM32F4x RCC
Based on the STM32F10x driver. Removing old code as we need to use the
bus number when dealing with 4 possible peripherals.

Change-Id: Id0263aa008e9b039ff9a00339e5622e289ffdf99
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-28 18:58:03 +00:00
Amit Kucheria
95e7fb6c98 arm: st_stm32: Add support for STM32F4x SoC family
This patch adds support for the STMicroelectronics STM32F4x family in the
STM32 MCU line. Configuration is included for the STM32F401RE MCU.

Acknowledgements to Pawel Wodnicki's earlier submission from February that
was used as a starting point for this port. In the end, we rewrote all of it.

Change-Id: I9797c282ac3c0cc66a63b9d34821de95df537ef6
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-28 18:58:02 +00:00
Dmitriy Korovkin
3c7dda3897 unified/arc: Fix scheduler algorithm bug
Fix the error in thread rescheduling:

Fix Fast IRQ exit routine error when it reschedules threads if
(prio >= 0) || (sched_locked == 0) || (next_thread == _current),
while the correct condition for thread rescheduling is:
(prio >= 0) && (sched_locked == 0) && (next_thread != _current),

Fix regular IRQ error when the regular IRQ exit routine rescheduled
threads when (next_thread == _current) instead of
(next_thread != current).

Increased IDLE_STACK_SIZE for ARC architecture, to hold saved
registers.

Change-Id: I1d87a968e231e13822844b7564567e6ca310cde2
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-10-28 17:46:54 +00:00
Marcus Shawcroft
c49ad10273 soc:mk64f12: Enable RANDOM_KSDK driver by default if RANDOM_GENERATOR enabled.
The mk64f12 provides RNGA hardware. Follow the implementation pattern
used by various other driver classes and enable the RANDOM KSDK shim
driver if the RANDOM driver is enabled.

Change-Id: I46bdf16cf1c48937011fb1b0e4c292615efd4c95
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-28 12:35:18 +00:00
Benjamin Walsh
b452817b67 kernel: merge _IS_IN_ISR() with _is_in_isr()
They were the same, standardize on the lowercase one.

Change-Id: I8bca080e45f3e0970697d4451e468b9081f96f5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-27 21:45:03 +00:00
Amit Kucheria
9cbd41ab13 arm: defconfig: Remove platform-specific options
SOC_TI_LM3S6965 and UART_STELLARIS are platform-specific, remove from
arch/arm/defconfig.

Change-Id: I3b37bc2ddfabb1da4e7538b5ab0e553fb2464584
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
2016-10-27 15:00:47 +00:00
Ricardo Salveti
a9f2061dfb gpio: stm32: introduce alternative function config
STM32F4 requires the alternative function config to be set, so just
initialize that as part of the gpio configure call.

Change-Id: I33a4a8efec59c5ebe7dc3f3580f0dd2bf7ded7f4
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
2016-10-27 14:48:43 +00:00
Allan Stephens
743bdb8143 unified: Enable handling of thread options for static threads
Change-Id: I51d2d9cfa0eeb5f974a6cf1db32406399ef57418
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-27 08:36:14 -05:00
Marcus Shawcroft
abb99c377d soc/stm32f1: Enable IWDG_STM32 dependent on WATCHDOG
The STM32F1 range all have the independent watchdog, enable the driver
by default if CONFIG_WATCHDOG is enabled.

Change-Id: I3869884dc51c56194367b46007c87f6cee699689
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-26 20:51:08 +00:00
Piotr Mienkowski
378fa6598f arch: Add support for Cortex-M7 processor
All M7 features common to M3/M4 are working. New features like Tightly
Coupled Memory (TCM) are not yet supported.

Change-Id: I5f7b292e70843aec415728f24c973bb003014f4b
Jira: ZEP-977
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
2016-10-26 12:58:40 -05:00
Andrew Boie
431607c20a nios2: port to unified kernel
With this patch we introduce unified kernel support for NIOS II.
Not all test cases have been ported, but the following command
currently succeeds with 43/43 passing test cases:

 $ sanitycheck --arch=nios2 -xKERNEL_TYPE=unified \
         --tag=unified_capable

Issue: ZEP-934
Change-Id: Id8effa0369a6a22c4d0a789fa2a8e108af0e0786
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-10-26 17:10:13 +00:00
Allan Stephens
4aef71b9f6 unified: Finish adding thread monitoring support
Existing code wasn't removing a thread from the kernel's list
of active threads if the thread terminated or aborted. (It did
remove it if the delayed starting of a thread was cancelled.)

Change-Id: Icc97917e33765696480d0e9bf31e882ef555d095
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-26 17:03:13 +00:00
Allan Stephens
2220f25f0a kernel: Standardize thread monitoring initialization
Gets rid of unnecessary THREAD_MONITOR_INIT() macro, to be
consistent with the approach taken by _thread_monitor_exit().

Aligns x86 code with the approach used on other architectures.

Revises the associated comments and removes unnecessary
doxygen tags.

Change-Id: Ied1aebcd476afb82f61862b77264efb8a7dc66c9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-26 17:03:12 +00:00
Allan Stephens
92e75040a2 kernel: Revise thread monitoring exit API naming
Renames _thread_exit() to _thread_monitoring_exit() to make
its purpose clearer. Revises the associated comments and
removes unnecessary doxygen tags.

Change-Id: I010a328d35d2d79d2a29b9d0b6c02097bb655989
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-26 17:03:12 +00:00
Carles Cufi
33d17497d2 drivers: uart_nrf5: Use MDK baudrate divisor constants
The baudrate calculation present in set_baudrate() is
causing the UART to emit inital bytes incorrectly, for a
reason currently unknown, but directly related to the fact
that __aeabi_uldivmod is being invoked.
Since the nRF5x Product Specifications do not provide a
standard formula to calculate baudrates and instead list
a predefined set of divisor values, we opt here to use the
official values and remove the attempt at calculating them
manually.

Change-Id: Ic3ff42ea6d065e9a1d26a5350ce5bf5ad661160a
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-10-25 18:40:56 +00:00
Kumar Gala
bbf736cf6e build: refactor kernel hex build to be common
Several platforms utilize a ihex image format.  Rather than
duplicating the build bits in everyones makefile, pull it into the
toplevel makefile so we all share it.

Change-Id: I9097b06e7e386a69ce6ab4d4e4d56cc776adfec2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-24 10:59:22 -05:00
Anas Nashif
641944283d soc: intel_quark: source Kconfig file of SoC
Change-Id: Ibcd8dc5889cc89333a017d2838294e6abf16618a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-22 16:55:54 -04:00
Dmitriy Korovkin
dc76dbf2ef unified: Add tickless idle support for ARC
Change-Id: I89684e7bee379be0a18f64e4f2c39ae132fe7e6d
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-10-22 01:27:01 +00:00
Dmitriy Korovkin
909bfffda9 unified/arc: add unified kernel support for ARC arch
- the interrupt (both regular and fast) now does not do rescheduling
  if the current thread is a coop thread or if the scheduler is not locked

- the _nanokernel.flags cache of _current.flags is not used anymore
  (could be a source of bugs) and is not needed in the scheduling algo

- there is no 'task' field in the _nanokernel anymore: scheduling routines
  call _get_next_ready_thread instead

- the _nanokernel.fiber field is replaced by a more sophisticated
  ready_q, based on the microkernel's priority-bitmap-based one

- thread initialization initializes new fields in the tcs, and does not
  initialize obsolete ones

- nano_private includes nano_internal.h from the unified directory

- The FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
  priority drives the behaviour

- the tcs uses a dlist for queuing in both ready and wait queues instead
  of a custom singly-linked list

- other new fields in the tcs include a schedule-lock count, a
  back-pointer to init data (when the task is static) and a pointer to
  swap data, needed when a thread pending on _Swap() must be passed more
  then just one value (e.g. k_stack_pop() needs an error code and data)

- the 'fiber' and 'task' fields of _nanokernel are replaced with an O(1)
  ready queue (taken from the microkernel)

- fiberRtnValueSet() is aliased to _set_thread_return_value since it
  also operates on preempt threads now

- _set_thread_return_value_with_data() sets the swap_data field in
  addition to a return value from _Swap()

- convenience aliases are created for shorter names:

  - _current is defined as _nanokernel.current
  - _ready_q is defined as _nanokernel.ready_q

- _Swap() sets the threads's return code to -EAGAIN before swapping out
  to prevent timeouts to have to set it (solves hard issues in some
  kernel objects).

Change-Id: Ib9690173cbc36c36a9ec67e65590b40d758673de
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-10-22 01:27:00 +00:00
Dmitriy Korovkin
05d4b23f22 arc: Fix RGF_NUM_BANKS==1 and NUM_IRQ_PRIO_LEVELS>1 problem
Define _firq_scratch_restore, needed when CONFIG_RGF_NUM_BANKS==1
outside of CONFIG_NUM_IRQ_PRIO_LEVELS > 1 clause.

Change-Id: I82eef11a005a35f38a064ce3ce1d6521d6428958
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-10-22 01:27:00 +00:00
Ricardo Salveti
1dd18c3f92 arm: Add initial support for Nordic Semiconductor nRF51 series
Still missing a working timer driver, as SysTick is not really available
in this SoC series (enabled to avoid build issues, but not used).

Jira: ZEP-784

Change-Id: Ie1c8e6c5e8955ee7f260ce013f4451f9215f3457
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-22 01:25:55 +00:00
Ricardo Salveti
69b9451af1 arm/nordic: use a common header for the nrf51/nrf52 SoC families
Integrating the IRQ definitions for both nRF51 and nRF52, and defining
the set of IRQ values that are common to both.

Also switch the controller, uart and clock drivers to use the common
header definitions.

Change-Id: Id6816d7a97720896cfe4df83656fb8b1f8fb01fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-22 01:25:54 +00:00
Ricardo Salveti
ffacae20d0 arch/arm: add initial support for Cortex-M0/M0+
Not disabling SysTick as it is optional by the spec.

SVC not used as there is no priority-based interrupt masking (only
PendSV is used).

Largely based on a previous work done by Euan Mutch <euan@abelon.com>.

Jira: ZEP-783

Change-Id: I38e29bfcf0624c1aea5f9fd7a74230faa1b59e8b
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-22 01:25:53 +00:00
Chuck Jordan
13900b7046 arc: remove some NSIM conditionals
EM7D was recently merged, and one change suggested there was
to remove conditional checks for NSIM. It is OK to have the simulator
use the exact same memory addresses and sizes as would be found on the
board. This submission fixes EM9D and EM11D to be the same -- i.e.
to not have NSIM conditionals.
See ZEP-966.

Change-Id: Ia990ff7bb4b7ff5071af83723ed3d1420fdff012
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-21 11:53:37 -07:00
Chuck Jordan
a9442ab761 arc: em_starterkit board can now support SOC=EM7D
The EM7D SOC is similar to EM11D, except it has different sized
iccm and dccm memories, and also has FIRQ with RGF_NUM_BANK==1.
To select this SOC on the board, all dip switches are in the up position.
See ZEP-966.

Change-Id: I864ffe0efdf367de0a8cd58e9c46efd7e401c671
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-21 18:10:04 +00:00
Chuck Jordan
ff303948d5 arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.

Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966

Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-18 20:26:29 +00:00
Anas Nashif
debf5bfe63 pinmux: k64f: remove unused Kconfig section
Those options are not being used anywhere, so remove them and avoid some
confusion.

Change-Id: Ia3767dbd2432851dfae4b1e996f02ed1b2450505
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-18 20:14:52 +00:00
Vinayak Chettimada
5732ae1ae0 arm: nordic_nrf5: Select clock control for BLE controller
Bluetooth controller implementation requires the low power
oscillator for radio time space scheduling and as sleep
clock; the high frequency oscillator as the active clock.

For Nordic Semiconductor's nRF5 Series SoC's select the
NRF Clock peripheral when BLUETOOTH_CONTROLLER is selected
in Kconfig build.

Jira: ZEP-897

Change-id: I6f99e90b3485e757be61e91c749e485dd0cfdaba
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
2016-10-18 13:03:42 +00:00
Anas Nashif
dc8f7b1573 quark d2000: remove bluetooth configuration from SoC
Bluetooth is not an SoC feature of the D2000.

Change-Id: Ibc8a8e6986a7da227fc42cb833fe8508696b104a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-17 09:51:39 +00:00
Marcus Shawcroft
87077727bf eth: Add KSDK ENET driver.
Provide a network driver wrapped around the KSDK ENET and PHY
drivers.

The driver performs one shot PHY setup.  There is no support for PHY
disconnect, reconnect or configuration change.  The PHY setup,
implement via KSDK contains polled code that can block the
initialization thread for a few seconds.

There is no statistics collection for either normal operation or error
behaviour.

Origin: Original

Change-Id: Ia0f2e89a61348ed949976070353e823c178fcb24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-16 09:57:35 +00:00
Marcus Shawcroft
14aa67cbd1 board: Enable ETH_DW for quark_x1000 if ETHERNET is enabled.
There is a convention in the soc implementation for other
(non-ethernet) classes of driver that enabling a generic driver has the
effect of enabling the specific flavour of driver required for the
board.  Extend this convention such that when ETHERNET is enabled, the
quark_x1000 enables the DW ethernet driver.

Change-Id: I525471d259c9582024cd44d6cc4557260abe6451
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-15 16:44:06 +00:00
Marcus Shawcroft
c5248a9d26 quark_se: Make ipm console config structure static.
Change-Id: Id8c4c94a76c5a5f7d2a1bcef2059511033f65ee8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-15 12:29:24 +00:00
Marcus Shawcroft
8ea6287c0b quark: ipm: Make driver config structures static.
Change-Id: I2d4977aaea9df969fd8edb4b07310e472e6c6917
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-15 12:29:18 +00:00
Benjamin Walsh
b4b108de4d unified: rename sched.h to ksched.h
Build breaks when enabling CONFIG_NEWLIB_LIBC because it has its own
sched.h file.

This is a bad symptom of a greater issue: the build system passes many
'-I<path>' options to the compiler, and that allows including header
files by simply specifying their names (when located somewhere else than
<zephyr>/include/) and can cause clashes when several files in different
locations have the same name, like in this case.

Fixes ZEP-1062.

Change-Id: I81d1d69ee6669a609cd0c420b1b8f870d17dcb67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-14 20:49:36 +00:00
Ricardo Salveti
b0e0c51b47 arm: move atomic operations selection to the Cortex-M Kconfig
Builtin might not be available for ARMv6 (Cortex-M0/M0+) depending on
the toolchain used (not available by Zephyr's SDK GCC), so move the
atomic operations selection to the Cortex-M family Kconfig file.

Change-Id: I20a5a0c5fdd2bcff2d304139f5a7e8502fdb1cb3
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-11 20:47:49 +00:00
Benjamin Walsh
35497d6c5e unified: cache the next thread to run
When adding a thread to the ready queue, it is often known at that time
if the thread added will be the next one to run or not. So, instead of
simply updating the ready queues and the bitmask, also cache what that
thread is, so that when the scheduler is invoked, it can simply fetch it
from there. This is only done if there is a thread in the cache, since
the way the cache is updated is by comparing the priorities of the
thread being added and the cached thread.

When a thread is removed from the ready queue, if it is currently the
cached thread, it is also removed from the cache. The cache is not
updated at this time, since this would be a preemptive fetching that
could be overriden before the newly cached thread would even be
scheduled in.

Finally, when a thread is scheduled in, it now becomes the cached thread
since the fact that it is running means that by definition it was the
next one to run.

Doing this can speed up considerably some context switch times,
especially when a thread is preempted by an interrupt and the same
thread is scheduled when the interrupt exits.

Change-Id: I6dc8391cfca566699bb9b217eafe6bc6a063c8bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-10 21:27:31 +00:00
Anas Nashif
5e5981234f quark_se: x86 core does not support ADC
ADC is available on the sensor subsystem only.

Change-Id: I3242108eb1f39a9509e30cc7ff440e02811ba4e6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-10 21:26:31 +00:00
Anas Nashif
e05fa64f4c frdm_k64: spi: fixed wrong kconfig used in driver
Change-Id: I43f31562cdfa0b722907e5c6018e3e56d141ed4f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-10 21:26:30 +00:00
Anas Nashif
37d2fdce13 quark: dma: enable qmsi driver if DMA is selected
Change-Id: I413dc28da562a7899c5271a36eca9a6d8d84221a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-10 21:26:29 +00:00
Benjamin Walsh
fc59e5b584 unified/arm: fix saving of registers in __pendsv()
The unified kernel calls a function (_get_next_ready_thread) to fetch
the next thread to run: it thus must save caller-saved registers that
are expected to hold a value before calling such function.

The callee-saved registers are available after saving them in the
outgoing thread's stack, so use some of those instead to reduce the
number of registers to save before calling _get_next_ready_thread. Also,
save caller-saved registers in callee-saved registers instead of on the
stack to reduce memory accesses.

This issue did not show up previously, probably because
_get_next_ready_thread did not use the regsiters that had to be saved,
but an upcoming optimization to that function stomps on them.

Change-Id: I27dcededace846e623c3870d907f0d4c464173bf
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-07 22:51:11 +00:00
Chuck Jordan
df4c0acd2d arc: Fix comment about IRQ call stack
The code density registers are NOT saved on the stack.
This is controlled by bit 13 in AUX_IRQ_CTRL, which didn't even have a symbol
defined for it. I've also added _ARC_V2_AUX_IRQ_CTRL_LP for bit 13.

Change-Id: Ie80853b72bed4e60a5cf1cf0a8c905a3d86180d9
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-07 20:50:26 +00:00
Chuck Jordan
ed569f525d arc: RGF_NUM_BANKS is another configurable option for ARCs
In order to add the EM7D SOC, I will be implementing a version of the FIRQ
interrupt handler that saves and restores registers on the stack when
RGF_NUM_BANKS==1. All other ARC SOCs at this time have RGF_NUM_BANKS==2,
allowing for a faster handler that can use the registers in the 2nd register bank.
But EM7D doesn't have this 2nd bank, hence the need for this new configurable choice.
(See ZEP-966)

Change-Id: Ie089f1f079902552cf279c2cda23ee0805b01eed
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-07 20:50:25 +00:00
Anas Nashif
84c9db39e7 gpio: reduce Kconfigs and use consistent name for GPIOs
Using AON for GPIO kconfigs is very specifc to quark se, there
is no need to make this special for this platform. Use the
existing scheme instead.

Change-Id: I946431490380dc0f537d6056277a94c9c9c80fed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-07 16:15:07 +00:00
Ricardo Salveti
1450f7bae4 arm: remove exc_wrapper.S
Not used anymore as the support for dynamic IRQs was removed by
commit 844e212.

Change-Id: I624bbd777b2dbcbf905cedc61e63cef21e8a0bce
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-10-07 14:40:17 +00:00
Fabien Parent
f52baa15fb stm32: make SRAM/FLASH base address generic to soc
Move SRAM_BASE_ADDRESS and FLASH_BASE_ADDRESS to Kconfig.soc since
it will most likely be the same values for all STM32 socs.

Change-Id: I682dc441e34155a19a4f90757707008ef299e9d4
Signed-off-by: Fabien Parent <fparent@baylibre.com>
2016-10-05 18:33:21 +02:00
Qiu Peiyang
76549c1b79 I2C: remove obsolete i2c_quark_se_ss driver
i2c_quark_se_ss driver is deprecated and replaced
by i2c_qmsi_ss. So remove i2c_quark_se_ss definition.

Change-Id: Idcc6a7f01ffae626ae7d5f9966eac67be78599af
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
2016-10-05 10:07:30 +00:00
Ramesh Thomas
c4c0ed414b power_mgmt: Reduce complexity in handling of power hooks
Simplified some documentation, removing inconsistencies and making
it easier to understand by separating PM infrastructure areas and
soc specific components that implement the hooks.

Removed the DEVICE_SUSPEND_ONLY policy as it is redundant and
causes high complexity in the flow. It is also not practical
to use it because it was meant to be used without doing CPU or SOC
low power state operations. This means it would do device PM
operations in the ISR of the system timer used by the scheduler.
This can disrupt the scheduler time.

Added a check of a flag around the notification sent from the ISR
of the wake event and created APIs to set/clear it. This will
allow disabling the notification when not needed from
_sys_soc_suspend().

Jira: ZEP-972
Change-Id: Id7aa7d2683384eabed518d4efac446ecc84c3498
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-10-05 10:05:42 +00:00
Andrew Boie
26b1651f0c intstub.S: fix argument to _sys_power_save_idle_exit on IAMCU
Change-Id: I5aa1abe464ba2b8f9c36be78a95705ffcf993c7d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:27 +00:00
Andrew Boie
70d8a32740 x86: interrupts: consolidate duplicated code in idle path
Change-Id: I16b80f363fef17d3ea99fec0ced4f49238f8e6c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:07 +00:00
Andrew Boie
e56f61f5aa x86: exceptions: simplify exception stubs
Exception stubs now just push the handler and in some cases a dummy
error code before jumping to the exception handling code, never to
return.

Change-Id: I6a79d9243deb3fc7ccdae003dd0917364c0aa304
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:07 +00:00
Andrew Boie
edeb1f1c52 x86: interrupts: optimize and simplify IRQ stubs
Interrupt stubs now just push the ISR and parameter onto the stack
and jump to the common interrupt code, never to return.

Change-Id: I82543d8148b5c7dfe116c43f41791f852614bb28
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:06 +00:00
Andrew Boie
2d7490c7ce x86: don't unconditionally run ISRs with interrupts enabled
Re-enabling interrupts before running the ISR must only be done
when CONFIG_NESTED_INTERRUPTS is turned on.

Change-Id: I2c04f2ce08d41cfef5553ee8554a90d1be0e86a3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-26 17:53:45 +00:00
Qiu Peiyang
2a2291d430 remove unused whitespace in arch/arc/core/fault_s.S
commit  e57b21c78c ("irq: Use lowest priority not a
hard-coded priority 2") introduce a wrong whitespace,
not complying with coding style. Remove it.

Change-Id: Ie7e48843e5da6cb3417773ef8a57cf9a166c70d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
2016-09-25 20:35:09 -04:00
Chuck Jordan
e57b21c78c irq: Use lowest priority not a hard-coded priority 2
In this file was found an assumption about how many
priorities are being used. This is configurable with
CONFIG_NUM_IRQ_PRIO_LEVELS, however, so it should be using that
instead. This line of code changes:
or r3,r3,(1<<(CONFIG_NUM_IRQ_PRIO_LEVELS-1))
so as to use the correct bit to OR.

Change-Id: I8c6297e98b5163aa27460a68b203e8a27d1e2506
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-09-24 23:22:03 +00:00
Chuck Jordan
8e5c813a24 irq: _ARC_V2_DEF_IRQ_LEVEL should be set to last legal priority
Set _ARC_V2_DEF_IRQ_LEVEL to the last legal priority value, and not 15.
The last legal value is: (CONFIG_NUM_IRQ_PRIO_LEVELS-1).
This is safer because we don't want priorites not configured to be 
enabled.

Change-Id: I1689cc00aa7e707a204d16ec17d7f396566e8638
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-09-24 23:22:03 +00:00
Peter Mitsis
b27249486a unified: Remove references to obsolete task_timeout
Change-Id: I7c3b1b8418809914d3daf9d68ed8e4c3b99dd0b1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-23 19:53:20 +00:00
Andrew Boie
325cae5c94 kernel: remove lingering irq_connect_dynamic() references
This API no longer exists.

Change-Id: I724bee8c0ebfbbe2d47c00c7645977d817bbcd36
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-23 15:36:51 +00:00
Anas Nashif
58002193e9 drivers: gpio: reuse gpio Kconfigs for sensor subsystem
No need to create new Kconfig that do exactly the same, just
reuse those from the main QMSI driver.

Change-Id: I965055f36845ac0464e4a383b0d05c3ae35c0015
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-22 01:00:46 +00:00
Andrew Boie
99368c7435 x86: optimize GDT space
The CPU manual indicates that 8-byte alignment is sufficient,
not sure why gdt_rom was aligned on a 16-byte boundary.

The null descriptor in the GDT is never looked at by the CPU,
save a few bytes by putting the 6-byte pseudo descriptor there.

Change-Id: I73f26cdeb30a91f8258c88ef960a45812a11d959
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-20 20:47:15 +00:00
Andrew Boie
757dae5b7d x86: introduce new segmentation.h header
This header has a bunch of data structure definitions and macros useful
for manipulating segment descriptors on X86. The old IDT_ENTRY defintion
is removed in favor of the new 'struct segment_descriptor' which can be
used for all segment descriptor types and not just IRQ gates.

We also add some inline helper functions for examining segment registers,
descriptor tables, and doing far jumps/calls.

Change-Id: I640879073afa9765d2a214c3fb3c3305fef94b5e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-20 20:46:45 +00:00
Vinayak Chettimada
79cdf33579 ARM: irq: Add _arch_irq_is_enabled external interrupt API
Add _arch_irq_is_enabled external interrupt API to find out
if an IRQ is enabled.

Change-id: I8ccbaa6d4640c1ab8369d2d35c01a2cfbb02f6cd
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
2016-09-20 19:45:31 +00:00
Vinayak Chettimada
bbeb7030a4 ARM: irq: Do not clear pending IRQ when enabling them.
Do not clear pending IRQ when enabling an IRQ on ARM
architectures. Peripherals and S/W ISRs may be required to
be deferred until they are enabled later and the pended
IRQ should be retained for the ISR to be vectored to when
enabled.

Change-id: I808183018d8a2cc58390a1de3b4797b2bb7c6ec9
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
2016-09-20 19:44:59 +00:00
Peter Mitsis
3ffe5bfb8c unified: Include _timeout structure in tcs_base
The '_timeout' structure is needed by dummy threads so that they can
handle timeouts.

Change-Id: Iefabd6ad93c8e176e95ce4262f5f3544dc90b7d5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-20 11:43:40 -04:00
Peter Mitsis
68d1f4b562 unified: Add timeslice support
Change-Id: I5b6c1ef5c015d1ddaea21b1c5447336b1b04db39
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-20 15:28:54 +00:00
Anas Nashif
442987f542 intel_quark: move X86_IAMCU to defconfig
Do not force selection of X86_IAMCU

Jira: ZEP-867
Change-Id: I2ca0bcd73502321e9e6f5a4638c309393da54e43
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-17 11:14:12 +00:00
Daniel Thompson
de2be17fee arm/nrf52: Set CPU_HAS_FPU
Quoting the product specification this device contains an "ARM
Cortex-M4 processor with floating-point unit" or, as this would
more normally be expressed an ARM Cortex-M4F.

Update Kconfig accordingly.

Change-Id: I5bd6f17724d0d4aa9aaab9961f12d4e8502c38a5
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
2016-09-16 12:33:24 +01:00
Anas Nashif
99abf49fce quark_x1000: move the X1000 into the intel_quark family
Change-Id: I9d7f1bc56293458d1410b40b7e103974718cb681
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:33 +00:00
Anas Nashif
211e0e14d7 soc: intel_quark: move quark d2000 to intel_quark family
Change-Id: I4eeb25ee3ee94d59e6425163aad3c393593b7e02
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:32 +00:00
Anas Nashif
0be112fbcb intel_quark: Group Quark SoCs under intel_quark/
Change-Id: If0120aff88310871438562234abf51b26675ff28
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:32 +00:00
Anas Nashif
5363d14a9e boards: rename Quark SE Devboard to Quark SE C1000
This board now has an official name and will be available soon:

http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/se-soc/overview.html

Jira: ZEP-758
Change-Id: Ia16d33722308cf81471321c3063bdc75055a4d50
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:31 +00:00
Anas Nashif
5e4b62c35c boards: rename Quark SE Devboard to Quark SE C1000 (Sensor Subsystem)
Jira: ZEP-758
Change-Id: I8ee5a2f9e4a6ecbd15214e59321bf27a502ef6ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:30 +00:00
Benjamin Walsh
b32d0ff71e unified/x86: fix IAMCU build
Unified kernel does not provide the _thread_arg_t type, but instead uses
void * directly for its thread entry parameters. _thread_entry_t is
typedefed from void * anyway, and only obfuscates the type. So, define
_thread_entry_t to be a function pointer to a function with three void *
parameters, and when the unified kernel becomes the only kernel, all the
_thread_arg_t types will go away.

With this change, IAMCU runs all the tests sysV x86 is able to run as a
unified kernel.

Change-Id: I53c8754629a5a0a114a16a775ff1efc1884496ff
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-15 09:42:24 -04:00
Marcus Shawcroft
1bea527da6 ksdk: Add KSDK RNGA driver.
Provide a random driver wrapped around the KSDK RNGA driver.

Origin: Original

Change-Id: I43feeb37d8d5173c7b95af8e80434fb7dc77a83e
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-09-14 12:35:30 +00:00
Benjamin Walsh
983cbe398c unified/x86: add unified kernel support for x86 arch
The x86 architecture port is fitted with support for the unified kernel,
namely:

- the interrupt exit code now calls _Swap() if the current
  thread is not a coop thread and if the scheduler is not locked

- there is no 'task' fields in the _nanokernel anymore: _Swap()
  now calls _get_next_ready_thread instead

- the _nanokernel.fiber field is replaced by a more sophisticated
  ready_q, based on the microkernel's priority-bitmap-based one

- nano_private includes nano_internal.h from the unified directory

- the FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
  priority drives the behaviour

- the tcs uses a dlist for queuing in both ready and wait queues instead
  of a custom singly-linked list

- other new fields in the tcs include a schedule-lock count, a
  back-pointer to init data (when the task is static) and a pointer to
  swap data, needed when a thread pending on _Swap() must be passed more
  then just one value (e.g. k_stack_pop() needs an error code and data)

- fiberRtnValueSet() is aliased to _set_thread_return_value since it
  also operates on preempt threads now

- _set_thread_return_value_with_data() sets the swap_data field in
  addition to a return value from _Swap()

- convenience aliases are created for shorter names:

  - _current is defined as _nanokernel.current
  - _ready_q is defined as _nanokernel.ready_q

- _Swap() sets the threads's return code to -EAGAIN before swapping out
  to prevent timeouts to have to set it (solves hard issues in some
  kernel objects).

- Floating point support.

Note that, in _Swap(), the register holding the thread to be swapped in has
been changed from %ecx to %eax in both the legacy kernel and the unified kernel
to take advantage of the fact that the return value of _get_next_ready_thread()
is stored in %eax, and this avoids moving it to %ecx.

Work by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
         Allan Stephens <allan.stephens@windriver.com>
	 Benjamin Walsh <benjamin.walsh@windriver.com>

Change-Id: I4ce2bd47bcdc62034c669b5e889fc0f29480c43b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-13 17:12:55 -04:00
Benjamin Walsh
b9a0d90a5f x86: load _nanokernel in %edi in _Swap()
Loading the _nanokernel address in %edi rather than in %eax allows
calling funtions in _Swap() without having to restore it, since %eax is
used for the return value. %edi is a callee-saved register and does not
have to be restored.

Change-Id: I338086d8e15857e835d5d7487de975791926f869
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-13 17:12:55 -04:00
Benjamin Walsh
3cf3778d31 unified/arm: add unified kernel support for ARM arch
The ARM architecture port is fitted with support for the unified kernel,
namely:

- the interrupt/exception exit code now pends PendSV if the current
  thread is not a coop thread and if the scheduler is not locked

- fiber_abort is replaced by k_thread_abort(), which takes a thread ID
  as a parameter (i.e. does not only operate on the current thread)

- the _nanokernel.flags cache of _current.flags is not used anymore
  (could be a source of bugs) and is not needed in the scheduling algo

- there is no 'task' field in the _nanokernel anymore: PendSV not calls
  _get_next_ready_thread instead

- the _nanokernel.fiber field is replaced by a more sophisticated
  ready_q, based on the microkernel's priority-bitmap-based one

- thread initialization initializes new fields in the tcs, and does not
  initialize obsolete ones

- nano_private includes nano_internal.h from the unified directory

- The FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
  priority drives the behaviour

- the tcs uses a dlist for queuing in both ready and wait queues instead
  of a custom singly-linked list

- other new fields in the tcs include a schedule-lock count, a
  back-pointer to init data (when the task is static) and a pointer to
  swap data, needed when a thread pending on _Swap() must be passed more
  then just one value (e.g. k_stack_pop() needs an error code and data)

- the 'fiber' and 'task' fields of _nanokernel are replaced with an O(1)
  ready queue (taken from the microkernel)

- fiberRtnValueSet() is aliased to _set_thread_return_value since it
  also operates on preempt threads now

- _set_thread_return_value_with_data() sets the swap_data field in
  addition to a return value from _Swap()

- convenience aliases are created for shorter names:

  - _current is defined as _nanokernel.current
  - _ready_q is defined as _nanokernel.ready_q

- _Swap() sets the threads's return code to -EAGAIN before swapping out
  to prevent timeouts to have to set it (solves hard issues in some
  kernel objects).

Change-Id: I36c03c362bc2908dae064ec67e6b8469fc573983
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-13 17:12:55 -04:00
Benjamin Walsh
a8a830b5db arm: only compile gdb stubs when CONFIG_GDB_INFO=y
They use data that is unavailable to the unified kernel, and are not
used anymore really. For now, only compile them when CONFIG_GDB_INFO=y,
and never enable CONFIG_GDB_INFO when building the unified kernel.

These files should go away when the unified kernel is made the only
kernel type.

Change-Id: I0a2a917dd453ecaae729125008756e0f676df16d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-13 17:12:55 -04:00
Benjamin Walsh
781561c855 arm: add __ASSERT() for stack alignment
Change-Id: Id5c23f502a17ad3e889a0de7c7ad18085b123078
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-09-13 17:12:55 -04:00
Dmitriy Korovkin
59f198d86d arm atmel sam3: Disable watchdog timer
Watchdog timer is enabled after the board reset. It is not used by Zephyr OS,
and having it enabled causes system resets during CPU-intensive operations.

Change-Id: If5583dbd2d2fb2206274467c523d6b5d147f1fbe
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-09-12 02:00:34 +00:00
Dmitriy Korovkin
8409242d6d arm atmel sam3: Add constants and structures for watchdog registers
Define symbolic constants for watchdog timer registers.
Provides the necessary interface to configure or disable
the watchdog timer.

Change-Id: I80002a843361569fdd78b725fc3f68e65195d02e
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-09-12 02:00:33 +00:00
Andy Ross
55dd1cc918 quark_se_ss: Fix console default
The ARC side should use the same console UART as x86 by default if we
want identical behavior.

Change-Id: I067860581cfd93d97ffad3d8f0bc5591f555e3ce
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-09-09 21:37:56 +00:00
Ricardo Salveti
b96cfc5191 arm/nrf52: fix default number of IRQs
There is a total of 39 IRQs defined at nrf52/soc_irq.h.

Change-Id: Id478fb15a07cfdecaa6cc136730d20017b8752c5
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-09-09 14:32:43 +00:00
Andre Guedes
a7f70af0db quark_d2000/se: Don't setup GDT during initialization
Quark D2000 and SE based boards (but Arduino 101) use QMSI bootloader
by default. QMSI bootloader sets up GDT in the so-called 'basic flat
model' just like Zephyr does by default.

This patch changes Quark D2000 and SE boards default configuration
so they rely on QMSI bootloader and we don't sets up GDT twice.

Change-Id: Ic6e520148b732bd48c00657c6c8138a8d865faef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-09-09 11:21:39 +00:00
Anas Nashif
5c7a26536d quark_se: sensor: enable QMSI ADC driver
If ADC is enabled, configure QMSI driver.

Change-Id: I73f23d0b2fa788f605e5a440ed0bcb3d5e5f011c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-08 20:45:35 -04:00
Ricardo Salveti
30e76dfb7b arm/irq_manage: change assert to allow sharing prio with PendSV
Zephyr uses the last priority level for the PendSV exception, but
sharing prio can still be useful on systems with a reduced set of
priorities, like Cortex-M0/M0+.

Change-Id: I767527419dcd8f67c2b406756b9208afd3b96de0
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
2016-09-08 21:43:21 +00:00
Andrew Boie
e931410756 x86: fatal: don't report bogus interrupt vectors
_irq_controller_isr_vector_get() now returns -1 if it couldn't
determine which vector was activated.

Issue: ZEP-602
Change-Id: Ib0f5dbc3b68cc5e2c3a23121530e178aede20d06
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-08 12:48:20 -07:00
Baohong Liu
20d85fefe9 i2c: qmsi_shim: change some i2c config parameters to SoC specific
Change the signal ramp up/down config parameters in i2c driver
module to SoC specific.

Jira: ZEP-753

Change-Id: Ie01f1d890a7133d30ea53eee07f60354734a8571
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-09-08 11:57:41 +00:00
Anas Nashif
ce52e3988f Merge "Merge bluetooth branch to master" 2016-09-08 02:26:59 +00:00
Maureen Helm
e4067638b7 i2c: ksdk: Add shim driver
Add a shim layer around the ksdk I2C driver to adapt it to the Zephyr
I2C interface. Currently only supports master mode.

Jira: ZEP-717
Change-Id: I704b8c38e22e456bb9fa4325682b2a354a27a7ba
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-09-07 14:40:20 +00:00
Vinayak Chettimada
ad0e041e3d soc: Use nrf.h instead of nrf52.h and nrf52_bitfields.h
Since nrf.h abstracts the differences between the nRF51 and nRF52
architectures and chooses the right headers to include, it is
safer to use that instead of directly including the soc-specific
headers.

Jira: ZEP-702

Change-Id: I0e1758ede48f3422a41d226b0eab008e4ba2c77c
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-09-07 08:17:26 +03:00
Andrew Boie
844e21269c arm: remove dynamic IRQs and exceptions
Change-Id: I8fea235aff6b7cb7da07b491ba39ea383709b57f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 23:47:21 +00:00
Andrew Boie
1cda7554ca arm: exc_manage: fix printk format code usage
Change-Id: I1e3f313f9c653dc2eec2ea02f16437f6c60ef304
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 23:47:14 +00:00
Andrew Boie
3a1cf9af2c arc: remove deprecated dynamic interrupt implementation
Change-Id: I7a81123f72458f43d3e8e1ca04a921ae6c5f1f6e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 22:26:11 +00:00
Andrew Boie
e98ac235e6 x86: declare internal API for interrupt controllers
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.

Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.

Contents of the API:

- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.

- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags

- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced

- In assembly language domain, _irq_controller_eoi implements
EOI handling.

- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.

Specific changes made:

- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.

- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.

- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.

- Unused APIs removed, or folded into calling code when used just once.

- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway

Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 18:35:47 +00:00
Andrew Boie
c545e19a00 x86: remove dynamic interrupts and exceptions
Change-Id: I7e9756e9a0735a7d8257ee2142d5759e883e12cc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-06 18:35:24 +00:00
Anas Nashif
62289e6de7 quark_se: disable IPM and enable UART0 on the sensor subsystem
Treat the sensor subsystem as an independent board that can send
messages to UART and disable IPM and the messaging interface. IPM
can be enabled by applications that require such interface.

Fix all samples that are affected by this change to make sanitycheck
pass.

Jira: ZEP-451
Change-Id: I3df6af16adefaefec02b97778d6c68ffc920ac35
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-08-31 16:31:04 +00:00
Maureen Helm
de2a471138 nxp_kinetis: Refactor K64F init to use ksdk clock driver
The ksdk provides a clock driver, fsl_clock.c, for the K64F and an
example usage of that driver, clock_config.c, for the Freedom board.

See ext/hal/ksdk/devices/MK64F12/

Leverage parts of clock_config.c to configure the clocks (specifically,
the sequence in BOARD_BootClockRUN()), but use the new Kconfig options
to set up the configuration structure. This will allow support for new
boards that may have a different external oscillator frequency or type.

Jira: ZEP-715
Change-Id: I3f0c75e6236f57600cd8b7f06f4482b13026fc10
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-08-30 22:06:49 +00:00
Maureen Helm
67132c8689 nxp_kinetis: Add Kconfig options to configure clocks
Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose
Clock Generator (MCG) module to configure clocks. Adding options to
configure these modules for PLL operation with different external
oscillator frequencies, which can vary across boards. More options may
be added later to support other clocking modes such as FLL.

Jira: ZEP-715
Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-08-30 19:39:09 +00:00
Andy Ross
9f628943a8 toolchain: Remove vestigial COFF assembler symbol mangling support
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.

We aren't.  Zephyr is an ELF platform.  None of our toolchains do
this.  Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard.  Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.

(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)

Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2016-08-30 19:01:11 +00:00
Andrew Boie
0827d6c775 x86: fix incorrect printk() usage
Change-Id: I346a62f6a4611c7aaaae8b50dab17913faf4033f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-28 07:47:28 -04:00
Andrew Boie
c3825f2fed arc: fix incorrect printk() usage
Change-Id: Ib7fea912642dd72304d5d9fbd1309ab060a7e833
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-28 07:47:28 -04:00
Andrew Boie
1925d853cf nios2: fix incorrect printk() usage
Change-Id: Ib5102a8f0bc9dd8c6a43f94b3dfb3bc7cd16879b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-28 07:47:28 -04:00
Andrew Boie
b63d4928d8 arm: fix incorrect printk() usage
Change-Id: I56f980659513e66a414cc7ca9b64ecde61e903f9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-28 07:47:28 -04:00
Andrew Boie
4c22a95425 arc: unify copied linker script
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)

Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-27 11:28:42 +00:00
Benjamin Walsh
36ece00163 arc/soc: remove unused CONFIG_TIMER0_CLOCK_FREQ
Defined in all SoCs, but never referenced anywhere. That definition has
been replaced by CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.

Change-Id: I1801f72a03925717ded6fbfdef22b1993f843461
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-08-27 10:49:01 +00:00
David B. Kinder
d748577706 doc: Fix terminology in Kconfig files for 'platform'
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen.  References to 'platform' are change to 'board'

Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2016-08-18 21:17:29 +00:00
Andrew Boie
533c2ee30d arc: fix management of IRQ priority levels
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.

Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.

IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.

Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-17 20:51:05 +00:00
Andrew Boie
317a28bff3 arc: em11d: em9d: set SPI_DW_IRQ_FLAGS
0 should be fine; no need to make this an FIRQ or non-maskable

Change-Id: Ifdf89a72e4864a2c2bbd83752cd814e2cb9aa16e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-12 22:57:56 +00:00
Andrew Boie
8d320db7c6 em9d: em11d: fix broken build
The GPIO and UART drivers were failing to build due to some
missing soc.h defines.

Change-Id: I6811e3699449da0a61ccc8376a8e11b96ad7a4e5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-12 09:36:29 -07:00
Kumar Gala
79606bccf0 arm: Add support for both floating point ABIs
Add a Kconfig option to select between the Hard and Soft Float ABIs.  We
also default to the Hard Float ABI as this is what older SDK versions
supported.

JIRA: ZEP-555
Change-Id: I2180c98cd7556ab49f5ca9b46b31add2c11bd07b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-08-11 17:37:12 +00:00
Ramesh Thomas
e2dbb8059f power_mgmt: PM should use GPS1 instead of GPS0
QMSI boot loader uses GPS0. power.c should use GPS1 for its
purpose because GPS1 is reserved for PM use. Switched to
use GPS1 instead.

Jira: ZEP-647
Change-Id: I653450cd0b42aa80bef21c8a42f4aa39cdaef2ed
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-08-05 23:14:47 +00:00
Maureen Helm
dc631750fa nxp_kinetis: Refactor K64F init to use CMSIS register accesses
The K64F SoC initialization previously used macros and structs
custom-defined in Zephyr in order to access peripheral registers.
Refactored it to use CMSIS-style register accesses from the ksdk
instead.

Change-Id: I80975c62de07ec95cf830e99cd5b0abb9623acd0
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-08-02 05:27:35 +00:00
Genaro Saucedo Tejada
e7f42e52c9 sys_log: replace old debug macros at SSS boot
The boot initialization and boot process of the sensor sub systems
is now using the new system log macros and updated the Kconfig
variable to be a level rather than a bool.

Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
2016-07-31 18:16:02 +00:00
Andrew Boie
86bc75e4ab qemu_nios2: increase RAM size
Reflects RAM increase that we get with SDK 0.8.2.

Change-Id: I5d7157834e29bb56864e81fedfb9766d5e4a24f8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-29 20:47:11 +00:00
Andrew Boie
17c0b372a2 x86: improve exception APIs
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:

 _EXCEPTION_CONNECT_CODE(handler, vector)
 _EXCEPTION_CONNECT_NOCODE(handler, vector)

For x86 exceptions that do and do not push error codes onto
the stack respectively.

In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c

Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.

CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.

Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-28 18:13:24 +00:00
Kumar Gala
453b177435 arc: Remove nonexistant Kconfig sybmol from defconfig
CONFIG_SOC_GENERIC_ARC doesn't exist so remove it.

Change-Id: Idecfd27684b5fd83b7b296daa46a1a21a0ae4d95
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-07-27 17:14:54 +00:00
Andrew Boie
96cadd1a9a arc: move special-purpose irq priorities to flags
We have already done this on x86 and ARM. The policy is as follows:

* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.

Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-26 15:06:28 +00:00
Ramesh Thomas
2ce3a59555 power_mgmt: Create arch/soc specific helper functions
Created set of functions that was designed in the original RFC to
contain arch and soc specific code.  This makes the interface to
the OS PM infrastructure cleaner and makes it easier to understand
the flow in the sample app. Also it makes code reuse easier across
soc/arch implementations.  These are open to change in future if
other means to achieve the same goals are in place.

Jira: ZEP-227 ZEP-225
Change-Id: Ief57871c370341c55009ad4f456b7f71f2c2a3c6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-07-21 11:25:31 -07:00
Andrew Boie
eb53ebb885 x86: fix CONFIG_INIT_STACKS
The interrupt stack wasn't being initialized at boot.

Change-Id: Iec3e770d385643415641e15906c3a53f7c74a2e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-21 15:04:55 +00:00
Andrew Boie
3adcc45970 arm: assume irq stack and size are aligned
This is done in nano_init.c.

Change-Id: I86e170ecb51f0291a79f65847bb6043aa28731eb
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-21 15:04:41 +00:00
Andrew Boie
7a6272f846 nios2: assume IRQ stack pointer and size already aligned
This is now done in nano_init.c.

Change-Id: I6a55df8c33e23a0899fb4186696a6601e3f01aa3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-21 15:04:05 +00:00
Andrew Boie
0a86fcbb2a x86: assume irq stack pointer and size already aligned
This is now done in nano_init.c

Change-Id: I2717ca54fd5e16b18c2dc506bc3972caf23f26d8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-21 14:26:30 +00:00
Kumar Gala
1c0bcc8cc5 toolchain.gccarmemb: Simplify setting of libgcc include path
Utilize the gcc -print-libgcc-file-name to determine the path to
libgcc.a.  Using this also resolve issues if we are building with
floating point and the various ABIs to pickup the right lib.

We can also simply a few Makefiles and remove the need to export
_CROSS_COMPILE_arm_isa.

Change-Id: I293394c921c18fa4984173ba51825d6f9a333697
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-07-21 02:42:56 +00:00
Andrew Boie
fda08b0e43 x86: close EOI race condition when nested IRQs enabled
Until now, EOI had always been sent out to the APIC with interrupts
unlocked. Depending on timing, there is a race where the next interrupt
on the same line could arrive before _IntExit disables interrupts
and pops context. If this happens consecutively enough times, the
interrupt stack will overflow.

Now we disable interrupts at the beginning of _IntExitWithEoi and they
remain that way until 'iret'.

Change-Id: Ibb28e0db902ff483d7a885389f231ac2d1864657
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-20 21:48:00 +00:00
Andrew Boie
6a1474e75b nanokernel: support GCC compiler atomic builtins
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.

At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.

Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-18 23:20:52 +00:00
Andrew Boie
2eb86db529 nios2: optionally print cause code reason
This is at the expense of code size. The QEMU and MAX10
targets have plenty of space so enable it for these boards,
but leave off by default for others.

Change-Id: I93fdb7db14232727e9953b22490d8869ff3b60e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-18 19:26:37 +00:00
Peter Mitsis
cac70df72b nanokernel, cosmetic: Standardize [INT|EXC]_ACTIVE comments
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.

Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-07-18 12:26:33 -04:00
Andre Guedes
ebded004b9 x86: crt0: Remove 'je copyDataDone' from CONFIG_XIP block
When CONFIG_SYS_POWER_DEEP_SLEEP is enabled, the _sys_soc_resume
function is called and the 'ZF' bit from EFLAGS register may be set
to 1. In that case, we end up wrongly jumping into 'copyDataDone'
label and no data is copied from ROM to RAM.

It seems this 'je' instruction is used without any previous comparison
operation which properly sets the ZF flag. Since 'ZF' initial value is
0, we never jump into 'copyDataDone' label. Also, this 'je' instruction
doesn't seem to be really required since, if %ecx is zero, no data will
be copied anyway.

That being said, this patch removes the 'je' instruction since it fixes
the bug described in the first paragraph and it doesn't affect the rest
of the crt0 execution.

Also, removes outdated information about section size and alignment.

Change-Id: Ia062b78247c4059009193a53f879aa1ebe80881d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-07-15 23:59:11 +00:00
Andrew Boie
afaba4a98b altera_max10: enable and use 16550 UART
The 16550 will now be the default console device.

Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-15 19:31:44 +00:00
Andrew Boie
ff948335be nios2: remove nios2e-zephyr
We are not using this core build any more. Users should be using
the provided F core instead.

Change-Id: I2b5266273030c1bd355aafa78733b4077848d115
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-14 22:40:45 +00:00
Andrei Emeltchenko
1aa71161c0 quark_se: Correct UART_IRQ_FLAGS to IOAPIC_LEVEL
This patch basically reverts patch "QMSI/uart: Use IOAPIC_EDGE instead
of IOAPIC_LEVEL". The issue with lost UART interrupts is fixed with
following patch: "_loapic_isr_vector_get: fix implementation" which is
a proper way.

Change-Id: I07aa168335827b09db7fcb2486b01585648ff5d6
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-07-14 22:40:24 +00:00
Andrew Boie
af085b8edf quark_se: make EOI operations atomic
Some issues have been noted with nested interrupts on quark SE.
In particular, the wrong vector # being sent to the IOAPIC EOI
register. Now when doing EOI, we lock interrupts so that the act
of reading the current vector being serviced, and sending EOI
to both controllers happens atomically.

Change-Id: Id9ad992740e197bb9d4638764952b04a27c4af61
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-13 22:41:33 +00:00
Andre Guedes
813923e63c x86: crt0: Fix '_sys_soc_resume' type declaration
The '_sys_soc_resume' symbol is function-type not data-type as declared
in crt0.S. This patch fixes this by using GTEXT macro instead.

Change-Id: Ibe8bcf92ab045bfe908fd2048d046083e773894f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-07-13 17:59:25 +00:00
Andrew Boie
448334c2eb nios2: _Swap(): fix C calling issue
The code expected r10 to be preserved across the call to the
event logger, which wasn't reasonable given that it is caller-
saved.

Change-Id: I694357ea7ee9b410b93b5a0894e8c38c53127363
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-13 17:58:42 +00:00
Andrew Boie
8c524a291e x86: merge IAMCU and SYS V core arch code
Having two parallel implementations is a maintenance issue, especially
when some strategically placed #ifdefs will suffice.

We prefer the ASM versions for SYS V, as we need complete control of
the emitted assembly for interrupt handling and context switching.
The SYS V code is far more mature. IAMCU C code has known issues with
-fomit-frame-pointer.

The only difference between the two calling conventions is that the
first three function arguments are provided in eax, edx, ecx instead
of on the stack.

Issue: ZEP-49
Change-Id: I9245e4b0ffbeb6d890a4f08bc8a3a49faa6d8e7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-13 17:56:39 +00:00
Andrei Emeltchenko
8be61102da quark_d2000: Update UART_IRQ_FLAGS for the board
Since we started to use UART_IRQ_FLAGS define them also for
quark_d2000 board. Note that we use IOAPIC_LEVEL since this is right
thing to do and the issue with lost interrupts is fixed in
_loapic_isr_vector_get().

Change-Id: Iaed0283bcc01290e420b42ff5d40ce9d99bfc677
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-07-13 14:44:43 +00:00
Andrei Emeltchenko
bdb62b8934 QMSI/uart: Use IOAPIC_EDGE instead of IOAPIC_LEVEL
Use IOAPIC_EDGE instead of IOAPIC_LEVEL to fix missing interrupts.
During tests it was found that using IOAPIC_LEVEL interrupts for UART at
some points are lost.
Proposed by Calando, Antoine <antoine.calando@intel.com>

Change-Id: I18b20217c4d73fdeaa424bf59d00f6be1ec6ef1b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-07-12 19:30:31 +00:00
Andrew Boie
4eee43d4d4 nios2-qemu: correct system.h
The emulator supports all the integer math instructions and has
the necessary registers for exception debugging.

Change-Id: I55938d9e3a4b9d219f6fee06fe070e860ca71d4b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-12 18:09:55 +00:00
Andrew Boie
0b6c4febf1 nios2: get CPU features from ALT_CPU_* namespace
NIOS2_* namespace is deprecated.

Change-Id: I5a9b07ee33b20aa18509e9d789837f48199ab25d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-12 18:09:53 +00:00
Andrew Boie
80826decfc nios2: enable XIP by default
Change-Id: I930cbb61cf72de7c68b9a4289554004b4b2f8e21
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-12 18:09:49 +00:00
Andrew Boie
251317c1bf nios2f-zephyr: commit additional source files
These are necessary to edit the CPU design in QSYS.
These originate from the F core archive supplied by Altera.

Change-Id: Ic03bd8738ae58dc154b5eaef91154fadaa61c491
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-08 21:20:26 +00:00
Andrew Boie
76be6c89a7 nios2f-zephyr: update CPU build
This build has support for hardware break/watch points.

Change-Id: Icf8a0d4abc82640eedd8c43322ebecf0ef069974
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-08 21:20:22 +00:00
Andrew Boie
9557f0306c gen_idt: don't force 32-bit build
We no longer assume pointer sizes are the same between host and
target, and use stdint defintions to size things.

Change-Id: Ie4dc41c60d62931fdb3d1764ade01c16a64d0b54
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-08 20:31:02 +00:00
Andrew Boie
5b9378ab7e nanokernel: move dataCopy() and bssZero() to common code
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.

Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.

The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.

Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-08 18:23:11 +00:00
Andrew Boie
ef29812d51 nios2: support more global pointer scenarios
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.

For systems where all RAM is less than 64K, the 'data' option may be
appropriate.

Some fixes had to be made to the system in order to get around some
issues:

* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.

* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.

* same situation with extern references to k_pipe_t (fixed pipe_priv
test)

For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.

Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-06 18:14:31 +00:00
Andrew Boie
fca3591bce nios2: enable use of global pointer indirect addressing
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.

Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-06 16:33:32 +00:00
Peter Mitsis
005925e2dd arm float: Add Kconfig options
Adds Kconfig options CPU_HAS_FPU, FLOAT and FP_SHARING for the arm
architecture.

NOTE: All SOCs in the MK64F12 family have an FPU so that makes it a
convenient location to enable the hidden CPU_HAS_FPU option.

Change-Id: I71771d24f20f52079314bb8db9bf8a0aa827ab41
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-07-01 19:44:15 +00:00
Peter Mitsis
1f47a0dbce arm float: Update compiler options
Apply the correct compiler options when building for a Cortex-M4
processor that has floating point enabled. Using 'softfp' allows
floating point to be used with existing libraries supplied by the
Zephyr SDK. The 'hard' option would require new libraries to be
shipped with the SDK.

Change-Id: I141c20f54c2241134510888688637930c7b560a2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-07-01 19:44:15 +00:00
Andrew Boie
231e617593 nios2: enable instruction/data caches
The caches get initialized on boot and flushed after XIP copy
takes place.

Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-07-01 00:34:47 +00:00
Andrew Boie
c613715322 nios2-qemu: use all available RAM
Use all available ram, cut in half for simulated RAM/ROM
regions. Some larger test cases did not fit in 64K for
non-XIP case.

Change-Id: I12296286ca7efa5bcc1ceef30486c3fe8976811c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-30 20:56:16 +00:00
Andrew Boie
f33b8d32a1 nios2: implement kernel_event_logger
Interrupts and context switches are logged. Since this CPU does not
have a power-saving instruction, it never enters a sleep state so
we do not call _sys_k_event_logger_enter_sleep() from anywhere.

Change-Id: Idcef388e93ffea373446997a0f87e93a4db44331
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-30 12:10:43 -07:00
Andrew Boie
eab9123589 nios2: fix nano_cpu_idle()
Interrupts must always be unlocked when coming out of this function
or execution will never leave _power_save() once entered.

Change-Id: Idda9d9be7cfc576a1072afec38000f63ae262a10
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-30 18:52:10 +00:00
Adrian Bradianu
ff712114ef usb: dw: Add Quark SE USB device controller driver
Quark SE USB device (Designware IP) controller driver implements
the low level control routines to deal directly with the hardware.
Only FIFO mode supported.

Change-Id: I086186df017734579f0363ed79effc1481ff32c2
Signed-off-by: Adrian Bradianu <adrian.bradianu@windriver.com>
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-06-30 00:21:39 +00:00
Peter Mitsis
c632271879 arm float: Enable floating point
Enable floating point in the Cortex-M4 processor.

Change-Id: Ibadae12b9197d6486fd5c6a3d4e177fa9e1c71bc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-06-29 20:34:42 +00:00
Peter Mitsis
fc8b2a2064 arm float: Save and load FP registers
Saves and loads the non-volatile FP registers (s16-s31) when switching
between threads.

Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-06-29 20:34:20 +00:00
Peter Mitsis
65f1c0c10a arm float: Add preemptive FP regs
Adds the preemptive floating point registers to the ARM's thread
control structure.

Change-Id: I65fbee6303091ce0658bbc442c4707d306b68e92
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-06-29 19:49:34 +00:00
Peter Mitsis
d5709b6c92 arm float: Update exception stack frame structure
Updates the exception stack frame structure to include floating point
registers.

Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-06-29 19:47:59 +00:00
Dmitriy Korovkin
2e8e3088e8 atmel_sam3: Do not switch off CPU clock if debugging is planned
at91sam3 supposed to go to Sleep mode and stop the CPU clock
(HCLK). It leads to JTAG problems. In order to be able to use
JTAG, we need to keep CPU clock on. This is achieved by
switching to Wait mode and keeping external main clock.
Since Wait mode switches off automatically Fast RC Oscillator,
but keeps external clock untouched.

Change-Id: Ife37a7691c3cbdf434e560725a71d419adafe054
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-06-29 05:36:48 +00:00
Andrew Boie
31196d78aa nios2: add config option to include reset vector
Change-Id: I0e6257f30eb2ca778c094c0faa3721dc62e18d86
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:56 +00:00
Andrew Boie
7511a4f606 nios2: exceptions: remove remaining muldiv references
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.

Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:55 +00:00
Andrew Boie
e7041e98f8 nios2: exceptions: use computed offsets
Before we were hard-coding them in the assembly file. Makes it
easier to alter the layout of the struct.

Change-Id: I619dc67c68ff87fe60de429a69b2f604292d270c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:55 +00:00
Andrew Boie
c2ca9e609c nios2: fix debugging output
The faulting instruction was off by 4 bytes and we weren't printing
the exception cause code properly.

Change-Id: I86f4320c7be43dca96940186def56aa5e47bc49f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:55 +00:00
Andrew Boie
2de74a93ea nios2: properly set NANO_ESF pointer for _Fault()
We want to pass along the stack pointer, not dereference it.

Change-Id: I554eff316bffe50654942746e7960b561abb413b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:54 +00:00
Andrew Boie
a0464b802b nios2: implement thread monitor
Pulled from the ARC implementation. Tested via
test_obj_tracing.

Change-Id: I858e89cc9187f99539b362ade8098b3606d31464
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 05:23:54 +00:00
Andrew Boie
8616dad7eb nios2: fix QEMU arguments
The extra and redundant -serial was casuing issues, remove.
Pass -nographic to work around issues with the experimental QEMU
builds.

Change-Id: I3102fe026a56781d5c4fb20acaa519af368f8a41
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:22 +00:00
Andrew Boie
96a9ae3a41 nios2: thread.c: don't include timeout_q.h
Unnecessary and generates build errors for microkernel.

Change-Id: I678f44aa2b68c8f8954c78e7828e534f0c1f4215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:17 +00:00
Andrew Boie
543aa77392 nios2-qemu: fix CONFIG_XIP
It's all RAM, but we pretend the range 0x410000 - 0x420000
is the "ROM" region, and stuff gets copied into RAM starting
at 0x400000.

Change-Id: Idf6bd603e2552593f588cf6130ee4da946bcf5a3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:15 +00:00
Andrew Boie
a7b54980bd nios2: set appropriate compiler flags for math support
Nios II CPUs vary in configuration on whether they support
'mul', 'mulx', and 'div' family of instructions. The compiler
can be told to use GCC integer library routines instead if
needed.

Ideally we would just pull the configuration out of system.h,
but pulling include file #defines into the Make environment
will involve some build system work that is best left to a
later improvement.

We've decided to take this build-time approach rather than
handle unimplemented instruction exceptions, so remove the
hook in exception.S

Change-Id: I05be0d5ed4c1a49b23dca1550ee66fd5891044d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:14 +00:00
Andrew Boie
fda3bc1c8c nios2: _Swap(): optimize irq unlock
If the CPU lacks certain features the only writable bit in the
status register is the PIE bit, so just write the saved value back.

Change-Id: I91537ff640aa9977d19587c4b0ae414028752341
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:11 +00:00
Andrew Boie
69abfbdc9b nios2: remove stub build workaround
No longer necessary as all the stubs which didn't use their
parameters have now been implemented.

Change-Id: I0ab3f024431426fbdac6d17de21e9c7338879f6e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:09 +00:00
Andrew Boie
8a8a2928e5 nios2: implement fiberRtnValueSet()
The return value of _Swap() is often treated as a "don't care" value and thus
often ignored. However, there are cases when it is desirable to have a
meaningful return value. This meaningful value can be assigned via
fiberRtnValueSet(). To that end, a new field has been added to the coop
register struct to store this value for when _Swap() needs to return that
meaningful value.

Change-Id: Ic4967fa7d602850c09ebde18e8bfd4c97cda9ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:07 +00:00
Andrew Boie
885e9084a8 nios2: _IntLibInit(): fix comment
Change-Id: I9cfee87ed3ba5fadba60c197a44b38a0dc75720f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-29 00:08:06 +00:00
Andrew Boie
d4a209d484 nios2: implement irq_offload()
For this implementation, the presence of a value in global
_offload_routine signifies to the exception code that we should
enter the IRQ handling code even if there are no bits enabled
in ipending. The 'trap' instruction gets us into the exception
handling code.

Change-Id: Iac96adba0eaf24b54ac28678a31c26517867a4d2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-28 15:56:05 -07:00
Andrew Boie
99b2866ed2 nios2: implement _IS_IN_ISR()
We check to see if the stack pointer is somwhere on the
interrupt stack.

Change-Id: Ic9d21e9f03476b9c8955c44cbfa2e61dd1daed22
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-28 15:56:05 -07:00
Andrew Boie
5a92526a7d nios2: add start_task_arch.h
Required by microkernel, currently does nothing.

Change-Id: I256886e3a52817d9216599bbf5691bc27c1d0ad8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-23 05:37:32 +00:00
Andrew Boie
84f06303d1 nios2f-zephyr: check in CPU and configuration
Per Altera these files for the /F core are freely distributable.
README included with instructions and links to necessary software.

Origin: Altera
Change-Id: I58c0dbcb5a2b11f0845d4e390e6aa0020d8b3ed5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-23 00:15:53 +00:00
Andrew Boie
b8d7b0dfe7 nios2: properly set SYS_CLOCK_HW_CYCLES_PER_SEC
This is a workaround until we can modify the kernel to pull this
value out of system.h instead of Kconfig.

Change-Id: Iaafa9003d2bbcb5b38a050c371466a206f716ae7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:21 +00:00
Andrew Boie
738dec483e nios2: add static interrupt handling code
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.

Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:21 +00:00
Andrew Boie
e2ff2fdd91 nios2: add base exception handling code
Change-Id: I56b0ec1a3576a77ca7bd6f2c0217de8053406927
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:20 +00:00
Andrew Boie
1487c6d66e nios2: implement _Swap() and _new_thread()
With this code we can successfully boot and context switch into
the main thread. Nanokernel hello_world has the expected
"Hello World!" string in the RAM console.

Change-Id: I56335d992f5a7cbb12d9e4c02d1cc23ea28ae6ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:18 +00:00
Andrew Boie
3574aec5e1 nios2: don't enable XIP by default
If XIP is turned on, only hardware breakpoints may be used, and
code cannot be loaded onto the device with nios2-download
or GDB 'load' command. RAM-constrained applications are free to
enable this if they need to.

Change-Id: Iee2d41f71f7ca2bc599801cf3cf0fac680273e51
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:13 +00:00
Andrew Boie
5846018d0d nios2: crt0: fix GDB debugging
When an image is sent over the wire with the GDB 'load' command,
it tries to start execution from the __start symbol, which needs to
be in RAM. Since the reset vector is in ROM, name it something else.

Change-Id: Id0bbfa76db9a8a81bd7ff20be3f2baec81eae15e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:12 +00:00
Andrew Boie
0d9b755bb1 nios2: ensure stack pointer is properly aligned
Kconfig doesn't enforce any kind of alignment when specifying the
ISR stack size. Perform the assembly equivalent of STACK_ROUND_DOWN.

Change-Id: Ib7fb72ff7db8a3aa20ec6d0c59a03aa8227f6671
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:11 +00:00
Andrew Boie
b5177d7d2d nios2: Makefile: optionally include SOC Makefile
It may not necessarily exist.

Change-Id: I5c79d7538edef78e38f7e05b004e69e0259dd079
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:10 +00:00
Andrew Boie
464676510b nios2: crt0: init interrupt stack as well
CONFIG_INIT_STACKS should initialize all stack regions
with 0xaa. Make sure the initial interrupt stack gets this
as well. Take care not to exceed the bounds of the array
if it is not 4-byte aligned.

Change-Id: Ib23329ac84a5a8515272be2944f948e8faba65b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:10 +00:00
Andrew Boie
6524bae242 nios2-qemu: experimental QEMU target for Nios II
Change-Id: I4c2413000166b4a8c221fab81f3d8da98a88806b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:09 +00:00
Andrew Boie
4fabf216fd nios2f-zephyr: add Nios II/f core
This core has extra debugging features useful for this bring-up
exercise.

Change-Id: I619bc8768acb1d9be8699a6e238168f47e605f3d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 01:31:09 +00:00
Javier B Perez
587e5a5198 doc: fix blank line and unindent error in FAULT_DUMP option
Change-Id: I5fe38a03c0c16f89e5f456a62eb38d058380d00c
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
2016-06-21 20:04:13 +00:00
Maureen Helm
2bf391797b ksdk: Add Kconfig support for the ksdk
Add hidden configuration HAS_KSDK for SoCs to select if they have
support in the ksdk.

Change-Id: Ia4cd11901bc26d21a3bdfad6236d66656bb292cb
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2016-06-17 19:15:29 +00:00
Kumar Gala
b757c1ccba nios2: remove empty files from nios2e-zephyr
Use a kbuild trick to force built-in.o to get built even if there isn't
any code so we can link properly.  This is cleaner than keeping around
empty files that don't do anything.

Change-Id: I4214d21104fe5f49613fa5697c8116b0e8c8aa50
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-06-17 17:28:31 +00:00
Inaky Perez-Gonzalez
60f5c97dd0 doc|config: Nordic RF5 fix references to SOC_NRF5
There was a reference to SOC_FAMILY_NRF5 which was not use by anyone
else and it seemes like it was a typo, where the right reference was
to symbol SOC_NRF5. However, the right fix is to move both sites to
use SOC_FAMILY_NRF5 *and* fix the SOC_SERIES to be only nrf52,
otherwise it causes path duplication and the build fails.

This was also causing documentation warnings that are thus killed.

Change-Id: I92e74a6158f02df43e6e857df8f1e67bcfdd9551
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-06-16 19:51:40 +00:00
Baohong Liu
263b3cdbba quarkd2000: correct LOAPIC timer IRQ number
Change the LOAPIC timer IRQ number to 10. It should not
be 0.

Change-Id: I156286d0e3b903cca07cc3f87804b145aacaf117
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-06-15 02:13:15 +00:00
Inaky Perez-Gonzalez
66999d04d8 doc: add empty lines in enumeration for ReST to be happy
The ReST parser dislikes enumerations with no empty lines in
between. Whatever.

Change-Id: I480c08fe5b69f0d0f3ebfacdc64fc9e3ec94da21
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-06-15 01:44:55 +00:00
Inaky Perez-Gonzalez
68685dd301 doc: removed unused/defined CONFIG_EOI_HANDLER_SUPPORTED config option
No code uses it and it being undefined anywhere generates a
documentation warning.

Change-Id: I09de2e58edf82e7fb9780a5dea98a282502436b6
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-06-14 20:00:52 +00:00
Maureen Helm
2815687186 nxp_kinetis: Add Kconfig options to select the SoC part number
The KSDK device header files require a preprocessor macro that defines
the part number string (e.g., MK64FN1M0VMD12). Create a hidden Kconfig
option to hold the part number string, and hidden Kconfig options that
the board Kconfig will use to select the specific part number.

Change-Id: I612e785026261e425b47b5b7fae0c65b4f94b30b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-06-10 12:17:57 -05:00
Andrew Boie
00365c188c nios2: Kconfig: remove some unused config options
We get these out of system.h instead. A clause in libc-hooks.c
for newlib added since we don't get RAM size from
CONFIG_SRAM_BASE_ADDRESS.

Change-Id: Ic35113395b951f625e8e29658afe19c525037964
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:42 +00:00
Andrew Boie
3b9302158c nios2: set up common linker script for XIP and non-XIP
We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.

To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.

Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:41 +00:00
Andrew Boie
dca76617f0 nios2: implement irq_enable() and irq_disable()
Change-Id: I98fee2df9cb8a7aa9769863238980d043903d436
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:41 +00:00
Andrew Boie
45cff183a2 nios2: implement nano_cpu_idle and nano_cpu_atomic_idle
Nios II does not have a power saving instruction, so there is nothing
to really do here other than ensure that interrupts are in the correct
state when leaving nano_cpu_atomic_idle().

Change-Id: I664c7542dc2fc1795a453d35e183a737dcb20c38
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:41 +00:00
Andrew Boie
9280e71ea4 nios2: add flashing/debug scripts
For the moment, NIOS2_CPU_SOF must be set with the path to the
CPU configuration. We are checking with Altera on whether we
can directly check in the binary to the source tree.

These scripts depend on tools provided by the Altera Quartus
Prime Lite Edition. This is available for free but requires
registration on Altera's website to obtain.

Change-Id: Ia6cb6c9e43c3e141807a887cb25c47b370a7d8e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:40 +00:00
Andrew Boie
fe6f178a3b nios2: generate kernel image in Intel HEX format
Altera tools for creating .pof files for flashing onto their
FPGAs require UFM data to be in this special format. Extend
the current 'all' and 'zephyr' targets to additionally create
this .hex file using objcopy, with the same exclusions as the
existing rule for .bin files.

Change-Id: I75293fba47536545359f817a1f2c1ae905b9d25c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:40 +00:00
Andrew Boie
31e8030c05 nios2: set initial stack pointer to the interrupt stack
Change-Id: I5a71215dde9e7fdc7d5d9de5297f5f493de40ca8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:39 +00:00
Andrew Boie
191f1df574 nios2: crt0: split into __start and __text_start
__start is the CPU's reset vector. In a typical Nios II configuration,
the exception vector is 0x20 bytes after the reset vector, severely
constraining the amount of code that can go in here.

Split this into __start and __text_start. The only thing that __start
really need to do is init the instruction cache and jump into
__text_start.

JIRA IDs placed in comments for missing items.

Change-Id: I3c6b8ed65e8fcf6b6a735b80cf007d0180599230
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:39 +00:00
Andrew Boie
e57f3446ac nios2: add arch/nios2/soc/<soc>/include to linker include path
Linker scripts for Nios II will also need these headers as it
specifies the device's physical layout and various important
vector addresses.

Change-Id: Ie9efaf19e53d2493eed7b9783052393d7ea9dd0f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:39 +00:00
Carles Cufi
a155617858 nrf52: Use nrf.h instead of *nrf*.h
Include nrf.h instead of directly using the specific header
required. This will be useful in the future when additional
Nordic ICs are supported.

JIRA: ZEP-377
Change-Id: I7a7257b0aaa5fa0a0d202322c366efbdd1d84458
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-06-03 04:41:26 -07:00
Carles Cufi
7da47626fb nrf52: Provide Nordic MDK compatible macro based on SoC series
Translate CONFIG_SOC_SERIES_NRF52X to NRF52, which is the macro
expected by the Nordic MDK headers.

JIRA: ZEP-377
Change-Id: Ic846e4cddf8146ae9d96bc98d4b12311552dc4f6
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-06-03 04:41:26 -07:00
Kumar Gala
556b66f468 More cleanup whitespace in Kconfig files
Some additional whitespace converted to TABs

Change-Id: I945383f70960ad97e9cbc11ea96b099bcc558404
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-06-01 22:39:54 +00:00
Chuck Jordan
6c86ed85fe arc: fix stack corruption caused by firq handling
There are a few problems with the code being repaired here.
1. A seti was used to re-enable all interrupts, even though the
thread being switched to may have had certain interrupt priorities masked.
2. saved status32 already has SC bit if thats wanted, so its ok to just
restore status32 as-is w/o needing to and off anything.
3. the code is difficult to write using kflag and seti because as you
restore registers, there aren't any to use. But we can exploit a
trick where we pretend an interrupt has occured by setting a bit in
AUX_IRQ_ACT, and then use RTIE instruction to restore status32
atomically with branching to return address. Something about the way
this code was written was causing stack corruptings and crashes in an
application that uses a high rate of both FIRQ and Regular interrupts.

Change-Id: Ia7166d51f0e750c07832ab115b7151ce37ee0278
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-06-01 14:25:01 +00:00
Chuck Jordan
5f14d8fb01 arc: improved saving of lp_<count,start,end> using GPRs
Since firq utilizes a 2nd register bank, and since all of those
many GPRs can be used, the strategy here is to save extra registers,
such as lp_count, lp_start, lp_end into callee saved registers.
These registers are safe to use because the C-ABI followed by the
compiler will cause these to be spilled to the stack if a C function
wants to use them. By selecting upper GPRs, r23-r25, it is very unlikely
the compiler will spill them. This improvement, therefore, can avoid a
d-cache miss since we are avoding memory altogether when saving these.
The struct firq_regs is no longer needed.

Change-Id: I7c0d061908a90376da7a0101b62e804647a20443
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-29 22:23:13 +00:00
Carles Cufi
ddcc350a8b nrf52: Auto generate Intel Hex kernel image
Generate kernel image in Intel Hex format when building for the nRF52.
Remove the additional step from the board doc file.

Change-Id: I619496f64037c2a0ac459ae05e549e01458e0f71
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-05-29 03:27:27 -07:00
Chuck Jordan
0ca24cedda arc: trap handler, used by irq_offload, now handles thread switch
It was found that the test latency_measure, when compiled
for microkernel, would fail on the ARC. This because the
trap handler, used by irq_offload, wasn't supporting thread switching.
This submission adds the code to do that, and the code size is
bigger only when CONFIG_MICROKERNEL is defined.

To keep code a bit smaller, there is a trick exploited here where
the AE bit is cleared in the STATUS32 register and in AUX_IRQ_ACT,
bit 1 is set, to make it appear as if the machine has interrupted
at priority 1 level. It then can jump into some common interrupt
exit code for regular interrupts and perform an RTIE instruction
to switch into the new thread.

test/latency_measure/microkernel now passes.

Change-Id: I1872a80bb09a259814540567f51721203201679a
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-27 21:11:24 +00:00
Kumar Gala
bbe222cad0 soc: arm: Unify setting of Cortex-M specifc compiler flags
Moved setting of specific Cortex-M compiler flags in each SoC directory
unify setting them in the arch/arm/soc Makefile.

Add flags for Cortex M0, M0+, M1, M3, M4, and M7.  However only
CONFIG_CPU_CORTEX_M3 and CONFIG_CPU_CORTEX_M4 are supported at this time

As part of this change converted Kbuild files for some SoCs into
Makefiles as the Makefiles would be empty otherwise.

Change-Id: Ie4e0178b141ca761ec482a610ae50e94fe58070f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-27 10:45:48 -05:00
Kumar Gala
6102427e5d build: Introduce concept of SoC specific build flags
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.

Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-27 10:04:29 -05:00
Carles Cufi
893fbd5460 arm: Add support for Nordic Semiconductor's nRF52 series of ICs
Add SoC support for the Nordic Semiconductor nRF52 series.

JIRA: ZEP-377
Change-Id: Idb476f43d7ca35f87c73910dd9bd1c50032ccdbe
Signed-off-by: Glenn Ruben Bakke <glenn.ruben.bakke@nordicsemi.no>
Signed-off-by: Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Håkon Alseth <haakon.alseth@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2016-05-27 01:38:20 +00:00
Andrew Boie
81f61bb1be x86: make GDT setup optional
For some security scenarios the GDT may already be setup and locked,
in which case the kernel trying to set it again could lead to problems.

Change-Id: I727c1d213479f46a4bb6f0c04a9096131e10b3e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-26 19:32:03 +00:00
Chuck Jordan
80f0de8604 arc: Uses of .nd on various branches not wanted
The .nd on a branch is WRONG if its an unconditional branch. Not needed.
On conditional branches its a compiler feature that is not yet functional
with ARC targets. Typical code for this compiler can use .d to put
something in the delay slot of an instruction, but using .nd is probably
never wanted.

Change-Id: If1017c468e6e7af269ea73daeb4bc223dcc0059f
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-26 10:45:53 +00:00
Anas Nashif
de8bc78a5e arc: support microkernel on ARC
Microkernel on ARC works fine, was missing some declarations in the
linker file.
Also enable testing of microkernel with ARC and disable tests where
ARC is not supported yet.

Jira: ZEP-396
Change-Id: I2ac7b8dc0bea22f5d2e24832d9e3afad8df9f580
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-25 22:14:18 -04:00
Kumar Gala
9ec2f3be80 Cleanup whitespace in Kconfig files
Convert leading whitespace into tabs in Kconfig files.  Also replaced
double spaces between config and <prompt>.

Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 13:28:07 -05:00
Kumar Gala
8870a72e0d quark_se_ss: Remove duplicate QMSI Kconfig symbols
config QMSI & QMSI_BUILTIN got duplicated in Kconfig.defconfig.
Remove the duplicates.

Change-Id: I5b318ab73fa7e3dbc4943534e42d283e0382ff92
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 12:45:38 +00:00
Kumar Gala
7584a1273f ext: plumb out Kconfig support for external source code
Add missing Kconfig files and connections to expose Kconfig options
in ext/ directories.  Fixup QMSI to only be exposed on platforms that
utilize it.

Change-Id: I6c6c5011b2bf2966f65aa8279dc594a244821956
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 11:28:34 +00:00
Chuck Jordan
bc04903bdd arc: disable i-cache in early init because ARC CPUs start with it on
The ARC CPU comes up from reset with i-cache enabled.
It can have garbage in it from a previous run.
The fix is to check the build register for the i-cache, and if its
present, invalidate it fully, and then disable it.
_icache_setup() is called later to turn it on.

Change-Id: I26fae915153841c61e9530d5af2ddb9d0553275b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-24 00:02:17 +00:00
Chuck Jordan
95dd06737f arc: Adding EM11D SOC
EM11D is a ARC CPU configuration that can be selected for the
ARC EM Starter Kit. The board support for this board will be
submitted separately to expidite review.

Change-Id: Ifc4d48e1f5e01d44d1706e6426bd3b2d77ebe2f8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-23 23:48:00 +00:00
Chuck Jordan
7bfe11b3e1 arc: Adding EM9D SOC
EM9D is a ARC CPU configuration that can be selected for the
ARC EM Starter Kit. The board support for this board will be
submitted separately to expidite review.

Change-Id: I2c85bdab6ea7bfb257e94e4c72b11b4568dbac19
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-23 23:18:36 +00:00
Anas Nashif
59b34a37d8 uart: use qmsi driver for quark_se sensor subsystem
Move away from native driver and use the UART driver provided
by QMSI.

All peripherals on Quark MCUs will use QMSI drivers developed
specifically for Quark and optimized for this MCU line.

Change-Id: If4e27f38736849ea3e12c269886e2a03d957b671
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-23 21:32:20 +00:00
Anas Nashif
9739d11125 quark_se: i2c: use qmsi i2c driver
Now that we have QMSI sensor subsystem drivers, lets use them.

Change-Id: Icd301b6c044280b5b25d719b6dcc16d556a2ea8d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-23 21:31:41 +00:00
Anas Nashif
862cff1eab quark_se: gpio: use qmsi gpio driver
Now that we have QMSI sensor subsystem drivers, lets use them.

Change-Id: I1340ba8930fc8676f7b706540a105250ce3e51b9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-23 21:31:16 +00:00
Anas Nashif
1619e264dd quark_se: spi: use qmsi spi driver on sensor sub-system
Now that we have QMSI sensor subsystem drivers, lets use them.

Change-Id: I1776178ad6fb984d6e293dbfa8bb1d718e4c2566
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-23 21:30:53 +00:00
Anas Nashif
f7c5820f28 quark se: build sensor subsystem files
Change-Id: I4490823450dd5fab0c04bece9e61481958ab3843
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-23 21:30:25 +00:00
Chuck Jordan
9ae5d7671f arc: adding "all rights reserved" to banner
My boss is asking me to add "all rights reserved" to synopsys banners.

Change-Id: Id74bf3cd0be6bc3159a8b687a37eb11fa3a49f3e
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-20 20:55:21 -07:00
Peter Mitsis
1b3f8d1a95 x86 exceptions: Fix _ExcEntSetupDone
Fixes a bug in _ExcEntSetupDone wherein the return address to the
exception stub was accidentally changed to point to the TCS of the
interrupted thread.

Jira: ZEP-378
Change-Id: I0e502649c49c35ba8b2457016ede4a6b586da3fb
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-05-20 00:09:16 +00:00
Chuck Jordan
7f637af2bd spi: For spi_dw, added SPI_DW_FIFO_DEPTH as configurable paramter
When using the Synopsys DesignWare Synchronous Serial Interface (SSI),
the FIFO depth can vary from 2-256, depending upon how this module is built.
For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be
32. Adding this now as a configurable option. A larger FIFO really helps
reduce SPI interrupts.

Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 01:24:57 +00:00
Chuck Jordan
d32edfd220 arc: fix spelling error in comment of fault_s.S
In fault_s.S, changing the word "save" to "safe".

Change-Id: Ia997082a62bf287f09a72b7f0a00d506bd982770
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-15 10:54:35 -07:00
Chuck Jordan
c3ad7615ff arc: Add linker command file for Harvard architecture
Some ARC CPUs can be built with separate instruction bus
and data bus (i.e. Harvard Architecture). Such systems
have only ICCM and DCCM memories. When CONFIG_HARVARD
is defined, the initial stack pointer is set to the
TOP of the DCCM memory. Currently there is no SOC that
existing in Zephyr tree that sets CONFIG_HARVARD, but
this will be coming soon.

Change-Id: I2016d1f472fbdad683a964aa0b65c5263ecfb6cf
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-15 01:48:41 +00:00
Anas Nashif
059d97839e add a new option for debugging quark se
We had wrong logic and confusing config options for debugging
Quark SE sensor subsystem. The new option will be used for GDB
debugging. The existing DEBUG option will be used for printing
additional messages on the screen while booting the sensor
sub-system.

Change-Id: Ia54d22e872edafe531ccde271e7504fe9c48a73a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:52 +00:00
Anas Nashif
fbe7d90ead spi: consalidate and simplify
Use the same Kconfig infrastructure and options for all SPI drivers.

Jira: ZEP-294
Change-Id: I7097bf3d2e1040fcec166761a9342bff707de4dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:26 +00:00
Anas Nashif
a2b9b4b71a spi: remove kconfig variables that can be define in headers
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.

Jira: ZEP-294
Change-Id: I962ce36b7e2361ea77ae4178bb7c86c19a241c4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:26 +00:00
Anas Nashif
9096daa53f spi: intel: move soc specific values to header file
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.

Jira: ZEP-294
Change-Id: I7688ca523915e3fa8a1d28dea7a1d84a66b39d56
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:25 +00:00
Anas Nashif
d0c4b30679 adc: unify kconfig variables and make them consistent
Change-Id: Icf102cf845f0917263d4286fec7a85112c7f8ffc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:25 +00:00
Anas Nashif
1d547699a5 aio: unify kconfig variables and make them consistent
Change-Id: Ic3e4f1142a3d4dcde5947586bb4ad86372b3f70b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:24 +00:00
Anas Nashif
1ee7175de9 rtc: unify kconfig variable names
Change-Id: I2adc0b21944fc0af85d40c09deac14bdbf134178
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:24 +00:00
Anas Nashif
72bf29eb03 watchdog: unify kconfig variables
Use consistent naming for watchdog drivers.

Change-Id: Idcec987253ce1b6230ccdf29cd8149d0bd705052
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:24 +00:00
Anas Nashif
82c969c8ae gpio: use consistent names for IRQ priority variables
Change-Id: I35ca4a13bb9dc0fd86298fa4fb17158b275dc9cc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:23 +00:00
Anas Nashif
e1fea59671 gpio: GPIO_DW_BOTHEDGES_SUPPORT unused
Change-Id: I57adb395d308f01e469a2a88e0ad658169ffff72
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:22 +00:00
Anas Nashif
0140da310b i2c: unify kconfig options and share them across drivers
Reduces Kconfig variables by ~20

Change-Id: If39f7d49482d62417c621f98bc8c0c78df0d4139
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-12 10:57:22 +00:00
Chuck Jordan
4ad41d8d7f arc: early init should invalidate d-cache and set vector table
Some ARC targets can have a data-cache. Although there is no special
instruction to clear exceptions during early init, it is necessary to
invalidate the d-cache BEFORE any data is fetched. The ARC on arduino 101
doesn't have d-cache, and will thus skip this d-cache invalidate.

Also, it is important to set the vector table base register to point to
the interrupt vector table EARLY, so that if an exception is encountered,
the correct vector table is found. Set this base only if it is found to be
different from the one compiled in to the code.
These initialization steps assure that proper exception handling
is in place during early init.

Change-Id: Ie8b5928e5813e104680a6d6510c85d32dc8ed8f3
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-11 11:10:52 +00:00
Chuck Jordan
bd012c92b3 arc: initialize the i-cache ONLY if it is present
The aux register named _ARC_V2_I_CACHE_BUILD can be read
to determine if the ARC has an i-cache. If it does not,
don't attempt to initialize it because this would cause an exception.

Change-Id: I3ff519befcc5ebb7745b58401f12cf3015a9e2e9
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-11 11:10:52 +00:00
Chuck Jordan
f1874fabdd arc: do lr and sr instructions together, avoid instruction pipeline bubble
The lr and sr instructions cause a pipeline bubble. There is an efficiency
to be gained if pairs of lr or sr instructions are done right next to
each other. This can avoid some stall cycles.
Also, r14 and r15 can be used with isa-16 instructions.

Change-Id: I4165365b49da910db31e0699a1a6e47114962942
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-09 20:56:52 +00:00
Chuck Jordan
a364a628b0 arc: Add CONFIG_HARVARD since some ARC CPU Architectures are Harvard.
Some ARC SOC implementations will need CONFIG_HARVARD so as to
select a different initial stack pointer (one at the top of DCCM memory),
and also to select a different linker command file that uses
ICCM and DCCM. Quark_se_ss will have HARVARD equal to n.

Change-Id: Idb7c4126866c9604e1924200ad5fdd2bc9d28269
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-09 20:56:51 +00:00
Chuck Jordan
ac6f97893b arc: more improvements to use isa-16 instructions
By using isa-16 instructions, a bit of code-size can be saved,
and code can be a little faster.

Change-Id: I0567d8274372748f579610e2bd4236ce52c5d6c8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-09 20:56:50 +00:00
Andrew Boie
e91f7101c6 nios2: update _new_thread prototype to latest changes
Now matches kernel/nanokernel/include/nano_internal.h.

Change-Id: I4dbbf50aa05c55de42100a6896fe0fa3b26955ec
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:28 +00:00
Andrew Boie
8564875a98 nios2: provide and include soc-specific headers
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.

Include these files from <arch/cpu.h>.

Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:28 +00:00
Andrew Boie
7f7337a0fe nios2: fatal: add _SysFatalErrorHandler and _Fault stub
ZEP-252 will handle implementation of the code here.

Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:27 +00:00
Andrew Boie
2d5645e57a nios2: add minimal crt0.S
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.

vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.

Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:26 +00:00
Andrew Boie
ff872dc349 build: rename non-generated linker scripts to .ld extension
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.

Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:26 +00:00
Juan Manuel Cruz
8c1c45cfad event_logger: add arc support for sleep event
Jira: ZEP-53
Change-Id: I54e1a677a3d0cd5f08efefe45058115e79c062f9
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-05-06 18:52:45 +00:00
Anas Nashif
301572949a qemu: disable vga and avoid annoying warning message
supress warning message about missing rom file

qemu-system-i386: pci_add_option_rom: \
       failed to find romfile "vgabios-cirrus.bin"

Change-Id: I335369cf40b0891cbc96b4ff4d9e5e2f4740ee96
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-05-06 15:13:49 +00:00
Chuck Jordan
02c7eaa173 arc: improve code-density by using ld_s and st_s with r0-r3
Code size can be reduced by replacing ld and st
with ld_s and st_s (if target registers are r0-r3).

Change-Id: Ia70f0aff07fe41a0cfeff2d59dcdadf7c88e1ae8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-06 11:18:27 +00:00
Chuck Jordan
3545672e57 arc: can use small-variant instructions to load/store %r13
code-size optimization to use small-variant loads/stores with %r13w

Change-Id: Ic9b2b7744f7d465bccb1e59f64e621985ae7d04d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-06 11:18:27 +00:00
Chuck Jordan
77286b3143 arc: Set __start entry point to be same as __reset
There is a BUG here in that the alias for __start was
aliased to the start of the vector table. Yet, on ARC CPUs,
the vector table CANNOT be the entry point, because there
is no code in a vector table. Only addresses appear in each vector.
Thus, the reset vector, at offset 0 in this table, is a raw address.
The top Makefile in zephyr sets the lable __start to be the entry point
like this: -e __start. Debuggers, for example, use this entry point
to know where the first line of code is.

Also, in KConfig, there were duplicate NSIM blocks. One has been
removed.

Change-Id: I480be7d338a8b45b8ea6ef3f55ac2e6c43829452
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-05 22:12:56 +00:00
Peter Mitsis
b58878bb89 kernel: Init back pointer to microkernel task
Fibers initialize this back pointer to NULL as they are (by definition)
not microkernel tasks.  Microkernel tasks initialize it to their
corresponding 'ktask_t'.

However for nanokernel systems, the back pointer is always NULL. This
is because there is only one task in a nanokernel system (the background
task) and it can not pend on a nanokernel object--it must poll.

Change-Id: I9840fecc44224bef63d09d587d703720cf33ad57
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-05-04 22:51:33 +00:00
Peter Mitsis
8a33d98811 nanokernel: Add back pointer to microkernel task
Adds a back pointer to the microkernel task to the TCS when
configured for a microkernel. This is a necessary prerequisite
to support microkernel tasks pending on nanokernel objects.

Change-Id: Ia62f9cf482ca20b008772dad80cbfd6acb6f5b7a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-05-04 22:51:32 +00:00
Andrew Boie
68b3b6135e errno: implement _get_errno() in common code
We really should have more faith in the compiler, it generates
code to implement this exactly like the arch-specific assembly
versions, and on ARM is actually 4 bytes shorter.

FUNC_NO_FP used to disable the usual C preamble to update the
frame/stack pointers, which is how the sizes are still the same
or less. It's debatable how useful the occasional use of
FUNC_NO_FP is in practice since it hinders debugging and in a
production build frame pointers should be globally disabled, but
we can address that later.

Change-Id: I6c4b64ab3e3a9b6f91d52fa8c92e6e79a986fc77
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-04 17:04:14 +00:00
Chuck Jordan
6fd732f780 arch/arc/include: start_task_arch.h needed so ARC can build microkernel apps
Change-Id: Ibf23fb3545f98a4d5ade7640abde4819b95d0b8e
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-04 14:55:33 +00:00
Chuck Jordan
822b19ef74 arch/arc: add ICCM_BASE_ADDRESS and ICCM_SIZE
I am working on porting Zephyr to ARC EM Starterkit. This board has ARC 
CPUs with ICCM memories. On quark_se_ss ICCM is missing and ignored.

Change-Id: Ic49fc8ef3e6ad879ffc673b8baf34dd467f76c04
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-04 14:54:54 +00:00
Iván Briano
5e92acf9cf quark_x1000: The Quark X1000 does have an FPU
Change-Id: I2e23e7a950a055f31f01ccb871d476a9b9d8018b
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-05-04 10:24:30 +00:00
Andrew Boie
f6cf65d57c nios2: add prep_c to zero BSS and copy XIP data
Copied verbatim from arch/arc/core

Change-Id: I00c920064f75455010806951ad052289d0290654
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:46 +00:00
Andrew Boie
d380e555c6 nios2: turn on function and data sections
Change-Id: I5bd841873207d1106a82b3e05187ee401b6c5478
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:46 +00:00
Andrew Boie
f00671ab16 nios2: move cflags hacks to main Nios2 Makefile
These are for any Nios II at this stage of bring-up.

Change-Id: Ie4d0c80df164f81f6615ac35d3f42235b04870f1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:46 +00:00
Andrew Boie
9433895954 nios2: basic build, non-functional
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.

This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.

Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:45 +00:00
Geoff Thorpe
ded3070c1c nanokernel: tighten _is_thread_essential()
Of the 3 related functions;
  _thread_essential_set()
  _thread_essential_clear()
  _is_thread_essential()

The first two are parameter-less and always operate on
"_nanokernel.current". The last one takes a 'thread' parameter but will
operate on _nanokernel.current if the parameter is NULL. All calls to
_is_thread_essential() pass NULL!

This change makes the 3 functions consistent by removing the parameter
to the 3rd function. This should also be marginally more efficient,
though consistency was the motivation. This change corrects the doc
preamble to all 3 functions.

(These functions would probably be better as inlines. Also, the choice
of when to use wrappers seems a bit arbitrary. E.g. there's nothing
for setting/testing the "FIBER" flag.)

Change-Id: Ie3589f8a28b227c6d7a3a31b664d3b3e6e9c6d17
Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
2016-05-03 17:42:54 +00:00
Daniel Leung
8f0ab3038c arm/nxp_kinetis/k6x: simplify uart init
The UART console init should be done after UART init. So it can be
folded into general UART init, thus one fewer SYS_INIT().

Change-Id: Ifb18c5308dfef790325e6bff5bc7b5976fcd421e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-05-03 12:43:31 +00:00
Daniel Leung
ad6ed299b7 arm/nxp_kinetis/k6x: always inline clock init function
The clkInit() is always called so this can be inlined.
This saves 32 bytes of ROM space compared to non-inlined version.

Change-Id: I2cb6d02c0996acad16029be243f6059183938089
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-05-03 12:43:31 +00:00
Daniel Leung
b6f56d478a arm/atmel_sam3: always inline clock init function
The clock_init() is always called so this can be inlined.
This saves 32 bytes of ROM space compared to non-inlined version.

Change-Id: I1b95142da4c22f4b7fc7f7f6210503d90cf65cc9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-05-03 12:43:31 +00:00
Juan Manuel Cruz
2170ca79ff build: support icx llvm compiler
Change-Id: I0bcc1f2e0ea93830e61fb3eaf8b523b7c4e1c301
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-05-03 00:02:40 +00:00
Anas Nashif
79ba6c5d47 gpio: unify kernel configuration for all architectueres
This also enables GPIO on ATMEL SAM3 when GPIO is set.

Change-Id: I4125af4910d57bed98b0ee4967fb696e3f345e67
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-30 13:43:26 -04:00
Anas Nashif
ea54982e99 quark_se: remove hardcoded reset vector for ARC
Change-Id: Iba4d46b50990167aa9e21635a6a8e6c1dd90c5e3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-30 11:00:35 +00:00
Andrew Boie
7327c9ee1f nanokernel: move C atomic operations to centralized code
These C variants of atomic operations can work on any arch,
have platforms select them if they don't have ASM equivalents.

Change-Id: I38eb03bb58beff865681ee56ef7bc0fcded1e906
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 21:40:19 +00:00
Andrew Boie
97dcf63a5a arch/Makefile: simplify
The arch names and the directories are the same, make it so we
don't have to keep appending stuff to this file as new arches
are defined.

Change-Id: I640526f5cb83fe34f5af14b62e5d06295a4912b0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-27 21:40:19 +00:00
Andre Guedes
981caded95 arch: st_stm32: Include errno.h
The files soc_config.c and soc_gpio.c use errno code so they should
include errno.h.

Change-Id: I94237aa294701cc71ed17ea42eca9d8073d4ae47
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-04-26 22:49:49 +00:00
Anas Nashif
04e6243aa5 gpio: rename device name for AON GPIO
Change-Id: Iccd3790d3e7adbe790fe78755d297aad0ae97834
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-25 19:17:05 +00:00
Anas Nashif
1a1f7fd916 arc: make SRAM/DCCM values configurable
Remove hardcoding and make the values configurable. Also make the
Kconfig variables consistent with other architectures.

Change-Id: I69334002303d4d8abaf7363d9134fd5f46ce4eeb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-25 19:17:03 +00:00
Anas Nashif
9d8c332b21 i2c: use I2C_X nameing instead of I2CX
Other IOs use this format, so lets be consistent and use

I2C_0 instead of I2C0 and I2C_1 an instead of I2C1.

Change-Id: I591ab08e14bd533ef0fac38e596559da783863b8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-25 17:01:48 +00:00
Anas Nashif
ce836e2c69 toolchain: move iamcu output format/arch to SoC
Instead of defining the output format in the toolchain environment
setup, define this per SoC that supports the ABI.

This will allow us to directly referencing an installed toolchain
without the need for declaring ZEPHYR_GCC_VARIANT

Change-Id: Icd1a7a21acbf075a51854fb2ebb3ef06788ce9b5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-25 17:01:48 +00:00
Anas Nashif
e8bc8af602 quark_d2000: remove unused code
For Quark D2000 we use QMSI drivers, so the initialisation code is no
longer needed.

Change-Id: I22aaa35288e230c455a19b9e67dc6cfb7dc0ff12
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
b0c0040894 quark_se: quark_d2000: remove all defines that now come from qmsi
QMSI defines all the registers of the SoC and other values in
qm_soc_regs.h, so cleanup soc.h and rely on the data from the BSP
contained in qm_soc_regs.h.

Change-Id: I672925cf1c0144a9ed64073ea289c691285a8082
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
a6915c070d qmsi: spi: use built-in qmsi driver
Change-Id: Ic7e86e015d4beb11a01d75aa50bc50f95c784e5e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
1797c8f108 qmsi: uart: use built-in qmsi driver
Change-Id: Ie19aee8dad8ba082891f92a2d42dc71f4ac34dbe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
b3e02b406a qmsi: adc: use built-in qmsi driver
Fix naming and use a global driver name for instance.

Change-Id: I30a54cb9c20773e1b6fdc57b934aa564612a6c45
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
85b3c2c62a qmsi: gpio: use built-in qmsi driver
Change-Id: I11444bcc146dbc477bb605f6b405bee559716f2a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:55:36 -04:00
Anas Nashif
f4feacf8b2 qmsi: aon_counters: use built-in qmsi driver
Change-Id: I5df98e9eacf429f017a094c861dcf54ab61566c1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:29 -04:00
Anas Nashif
b512681f8c qmsi: aio: use built-in qmsi driver
Change-Id: I24b227d9367a4f0144cb9fa968a51827f8c2dfc5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:29 -04:00
Anas Nashif
940d539834 qmsi: pwm: use built-in qmsi driver
Change-Id: I154840f704b9cfec269addaf3cbd7e71bb6310af
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:29 -04:00
Anas Nashif
a7d3329694 qmsi: i2c: use built-in qmsi driver
Change-Id: I2e650198117128cec79a64abcd2cc065b5f9804c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:29 -04:00
Anas Nashif
98c09140f1 qmsi: watchdog: use built-in qmsi driver
Change-Id: I0cff75181bb2a51c91e6589f9624f0891db0b6e9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:29 -04:00
Anas Nashif
80e9d63dec qmsi: rtc: use built-in qmsi driver
Change-Id: If8e70c946f73abf03a695fecaeff30a9881f6e94
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:28 -04:00
Anas Nashif
987016b954 drivers: add qmsi files for Quark MCUs
This is from QMSI porject at https://github.com/01org/qmsi

The version included in this change is 1.0.1:

https://github.com/01org/qmsi/releases/tag/v1.0.1

commit: c902bc5143546b76a3708ddb465ea9b7a8bd314a

Origin: https://github.com/01org/qmsi
Change-Id: I983deb2cffe2f84b7b7f2dd381367863eab7c6d1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 20:46:28 -04:00
Anas Nashif
7c27d8ab3a soc: arm: add Makefiles one level up
It was not possible to add directories under an SoC family
because of the direct call to Makefile in the SoC series from the
architecture level.

While we have SoC still using the old structure, add a conditional
to still support old structure and allow Makefiles directly under
an SoC family directory. 

This is useful for adding drivers and BSP files common to one family.

Change-Id: I85dc8341523b41949de91d78675153ce0baa5aac
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-22 21:33:26 +00:00
Johan Hedberg
264c207f4f Bluetooth: Add custom "monitor" protocol logging over UART
With most boards there's no simple way to get access to the HCI
traffic. Simultaneously these boards only have one external UART for
the console. This patch introduces a protocol which combines both
normal logs and HCI logs over a single binary protocol sent over the
console UART.

The protocol is modeled based on the btsnoop/monitor protocols used by
BlueZ, and the first tool that's able to decode this is btmon from
BlueZ ("btmon --tty <tty>").

For platforms with two or more external UARTs it is still possible to
use CONFIG_UART_CONSOLE as long as the UART devices used are
different, however on platforms with a single external UART
UART_CONSOLE should be disabled if BLUETOOTH_DEBUG_MONITOR is enabled
(in this case printk/printf get encoded to the monitor protocol).

Origin: Original
Change-Id: I9d3997c7a06fe48e7decb212b2ac9bd8b8f9b74c
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-04-22 18:49:11 +03:00
Juan Manuel Cruz
b17258b536 debug: interrupt event logger support for arc
Jira: ZEP-53
Change-Id: Id6ee505a7e89122a47fc22162b4c257ac2126d09
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-04-22 12:39:22 +00:00
Anas Nashif
d2f1c76686 new SoC naming convention
Use SOC_FAMILY and SOC_SERIES to identify soc families and series
and to point to the correct linker files and files related to a
specific SoC.

Change-Id: I8b1a7339f37d6ea4161d03073d36557a40c0b4a6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:59 +00:00
Anas Nashif
a02c34ef0b soc: introduce SoC families and series
Add additional layers when defining SoCs to allow reuse among SoCs
of the same family and architecture.

The Board is the first location where we search for a linker.cmd file,
if not found we look for the linker file in
arch/<arch>/soc/<family>/<series>

Change-Id: I51d5e9a056220d0bd2ae0fa31474ffe63568e698
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:59 +00:00
Anas Nashif
b85ffc8104 stm32: reorganise soc directory and use family/series
Use SoC family/series and reoganise the structure to follow new
hierarchy.

Change-Id: I8637f1487a8287a6614ce6636cd018cf342fec95
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:59 +00:00
Anas Nashif
65c06afa58 kinetis: reorganise soc directory using soc family
Add Kinetis SoC family and rename fsl_frdm_k64f to mk64f12.
This will allow adding new SoCs of the same family and the reuse of code
among SoCs of the family and series.

Change-Id: Iea1a663aef7ce0487f147bdd36f668bebe80deb5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:58 +00:00
Anas Nashif
4b411b34a1 stm32: rename SOC_STM32F1X -> SOC_SERIES_STM32F1X
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.

Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:58 +00:00
Anas Nashif
9bf2da7ef4 stm32: rename CONFIG_SOC_STM32 -> CONFIG_SOC_FAMILY_STM32
Use CONFIG_SOC_FAMILY for the top level SoC family. A family
will have different SoCs or different SoC series with multiple
SoCs.
Adding the Family string to the config variable to avoid confusion
between actual SoCs and families and to prevent name collisions.

Change-Id: Ic99a2c1df7850dee3a45641027af82464dd6fadb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-04-18 21:24:58 +00:00
Benjamin Walsh
43592b1127 x86/debug: GDB server needs to handle some exceptions
GDB server needs ownership of some exceptions to display information when
taking a fatal exception (DIVIDE_ERROR, PAGE_FAULT).

Introduce a Kconfig option that can work for any debugger.

Change-Id: I39aef22a820543a7fe9ac333b487592946abc0f3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-04-16 05:29:22 +00:00
Benjamin Walsh
f703f7d0f6 debug: add target GDB server
The GDB server implements a set of GDB commands, such as read/write
memory, read/write registers, connect/detach, breakpoints, single-step,
continue. It is not OS-aware, and thus provides a 'system-level'
debugging environment, where the system stops when debugging (such as
handling a breakpoint or single-stepping).

It currently only works over a serial line, taking over the
uart_console. If target code prints over the console, the GDB server
intecepts them and does not send the characters directly over the serial
line, but rather wraps them in a packet handled by the GDB client.

Change-Id: Ic4b82e81b5a575831c01af7b476767234fbf74f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-04-16 05:29:22 +00:00
Benjamin Walsh
270d602efd debug/x86: add runtime info needed by target debuggers
Introduce an x86 interrupt stack frame that contains more information
than the non-debug one, namely the caller-saved GPRs, as well as an API
to retrieve it. Able to handle nested interrupts stack frames.

Change-Id: If182aaa2f34e4714b16ca65ff79da63b72d962f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-04-16 05:29:22 +00:00
Benjamin Walsh
e83ddd1471 x86: add debug hook in _NanoFatalErrorHandler()
Allow a debug server such a GDB to take control when a fatal error
occurs. The debug server simply has to define a _debug_fatal_hook()
function that will override the weak function installed by default.

Change-Id: Ib9dca5755868f747b697fa3178e09109f1eedb07
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-04-16 05:29:21 +00:00
Baohong Liu
d45eab2a7c drivers: Quark flash support
Quark flash sub-driver. It is based on the QMSI driver.

In order to enable this driver, the following options
must be set.

CONFIG_QMSI_DRIVERS
CONFIG_QMSI_INSTALL_PATH
CONFIG_FLASH
CONFIG_SOC_FLASH_QMSI

Origin: Original

Change-Id: Iffbea3b17624c755e367677b76d7216c2fba2ca1
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-04-16 02:01:25 +00:00
Daniel Leung
0c9876cc8d ipm: convert to use DEVICE_AND_API_INIT()
Change-Id: I2c81bc0d232473c76c0a4ffbf13faf4eabedda85
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-04-15 22:06:16 +00:00
Vlad Dogaru
b2419abfbc gpio: dw: Activate by default on D2000
Change-Id: I4b5a72ee086fae7c3d29311cd138af28d329f635
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
2016-04-12 09:58:00 +00:00
Vlad Dogaru
9e563c8769 gpio: dw: add support for D2000 board
The D2000 CRB is similar to the Arduino 101 (at least as GPIO is
concerned).  Add support for using the GPIO controller without QMSI
libraries.

Change-Id: I001da05c9a9d5771b2ec678a9d4a91c44db05289
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
2016-04-08 17:55:44 +00:00
Daniel Leung
ba4099430b ethernet/dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ib483419be5199b52cf281b4b106cd8a3be95b7be
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-04-07 00:58:57 +00:00
Andrei Emeltchenko
f7da2220d7 quark_se_devboard: Remove UART default name from soc config
Remove UART default configuration to make it default UART_0. This
makes default working fine with Nordic BLE chip using H:4 driver.

Change-Id: Icb6d9f068b586bbf04694bc77ed968211de94c8a
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-04-06 14:00:56 +03:00
Andrei Emeltchenko
36748b9f33 ia32: Allow to connect Nordic chip to qemu
Allow to connect Nordic Devkit or dongle to qemu. Simple
configuration for the current NBLE firmware is following:

Connect Nordic board to PC, ttyACMX gets created.
$ socat -x /dev/ttyACMX,raw,b1000000 unix-listen:/tmp/bt-server-bredr
Build app with prj_nble.conf and run with make qemu

Change-Id: I354644b465ad09ab0ca62fbd97f15d9bb3c87d6a
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-04-05 11:18:53 +03:00
Daniel Leung
8425568a8a gpio/dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ib7e0b81b2df1a0225fc244fea3035416d0a4f282
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-04-02 23:11:07 +00:00
Daniel Leung
8a05b46325 rtc/dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

This also separates IRQ_PRI into one for DW and one
for QMSI, to follow the convention of every other
drivers.

Change-Id: I338f819f71c18fa9e17015e8a588a3d0207350c6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 23:17:25 +00:00
Daniel Leung
f1ead35cc6 watchdog/wdt_dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ic73783189db57059d2b7f3727e4802e1b2e27931
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 23:17:24 +00:00
Daniel Leung
2d1ed03a8f pwm/k64_ftm: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ifd65097a65f80539cac073f95aadc2d8e42efb9f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 23:17:24 +00:00
Daniel Leung
17b3a85308 pwm/dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ifdbb5e3a997795ef577350d88f8cb06877eb6463
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 23:17:24 +00:00
Daniel Leung
5e886b2748 gpio/sch: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.

Change-Id: Ib8158f00a6c6616360ddbcf63981f1a85911c1b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 23:17:23 +00:00
Dmitriy Korovkin
8d76b7b083 arm: Disable unaligned access traps
GCC enables unaligned memory access for ARMv6 and above.
Once unaligned memory access is allowed, there's no need
for the unaligned memory access trap.

The change prevents the situation when the compiler
generates code that uses unaligned memory access, but
the CPU generates an exception when this code runs.

Change-Id: Id33f2264c631772e5c561e76fb579d8b7bc26e1e
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-31 21:28:23 +00:00
Andre Guedes
6e71586c37 i2c: qmsi: Add support for default configuration
This patch extends the i2c shim driver so it supports the 'default
configuration' infrastructure which enables the user to specify a
default configuration for the I2C device. The default configuration
is set during driver initialization.

This patch also changes Quark SE and D2000 Kconfig.defconfig files so
the i2c default configuration is set to '0x12' which means standard
bus speed, 7-bit addressing and master mode. This is the same value
used when DW driver is selected, by the way.

Change-Id: I06e0dc3c29e8da2f3317db5bef285177f2e92c9a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-31 13:18:26 +00:00
Daniel Leung
cb83db8c74 i2c/dw: remove kconfigs that are SoC specific
Remove those kconfig options that are SoC specific, and should not be
configurable via kconfig.

Change-Id: Ia62888838877da4627419bd36c261d5254761acd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-31 01:11:23 +00:00
Andrew Boie
c73a42bccc x86: irq: fix _get_dynamic_stub() calculation
It wasn't correct to add the size of the long jump instruction
as it *replaces* a short jump instead of just being after it.
So redefine this to be the difference in size between these
two instructions.

Change-Id: I65be2afab19d9cd8b096551acde0156f0503df87
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-30 22:24:16 +00:00
Baohong Liu
3d7ef48a95 drivers: AON counters: Move interrupt setting to SOC Kconfig
These interrupt settings are SOC specific. So, move them to the
SOC level of Kconfig.

As IRQ priority is fixed in D2000, changed the value to 0 to
make it consistent with what other shim drivers are using.

Change-Id: Id20bed46c478a7555ae976e3a3063ba2cb099788
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
2016-03-30 16:18:05 +00:00
Daniel Leung
8563a5178d aio_comparator/dw: base address to be defined by SoC
This is hardware design so there is no need for it to be
configurable in kconfig.

Change-Id: Iff162f330aae8ef9a7139b6e7ed9bfa87f26189a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-30 13:39:04 +00:00
Daniel Leung
32c6d97922 console/uart: remove duplicate default value for parent UART dev
There is no need to re-define CONFIG_UART_CONSOLE_ON_DEV_NAME to be
"UART_0" all over the place as its default is "UART_0" already.
So remove those duplicate defaults.

Change-Id: Ia86e26b8f90540fdbd7dcb3358d6dac352648b21
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-30 13:38:58 +00:00
Daniel Leung
8f6068e9d8 serial/ns16550: make IRQ triggering condition a SoC decision
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.

The default is to be triggered on rising edge, just as the same
old kconfig did.

Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-30 13:38:34 +00:00
Daniel Leung
26b474c987 serial/ns16550: reduce number of kconfig options
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.

Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-30 13:38:34 +00:00
Alexandre d'Alton
eac563ef27 arc: remove unecessary instruction and doc
lp_count register can be store directly to memory, it is actualy done,
and the instruction that precedes it has no effect.

Change-Id: I8b8fee6abd6f08eea38dd1ab5bbe61c25a2a1f7d
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
2016-03-29 01:25:49 +00:00
Alexandre d'Alton
f91e55b798 arc: implement stack checking
ARC CPU has stack checking feature that allows to trigger an exception
whenever the stack is incorrectly accessed.
This patch implements the stack_top and stack_base register updates on
context switches, and activates the Stack Checking bit of STATUS32
register when the CPU is in the context of a fiber or task.
As GCC accesses the non-yet allocated stack with frame pointer enabled,
this patch also add the omit-frame-pointer gcc flag in order to work
properly.

Change-Id: Ia9e224085a03bd29d682fb8f51f8e712f2ccb556
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
2016-03-29 01:25:49 +00:00
Daniel Leung
c65821718f i2c/quark_se_ss: Remove base address kconfig options
The base addresses are SoC specific so there is no need to make
configurable via kconfig.

Change-Id: Iaf8444f77513255d5f0112af6710243aae09f066
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 16:09:15 -07:00
Daniel Leung
72c83d8740 arc/quark_se_ss: clean up soc.h
Most of the #ifdef are not really needed, so clean up the file
for readability.

Change-Id: I4d15f3cb7ef4db9113d4cdadbd3309da6587c64e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 16:05:23 -07:00
Daniel Leung
3f408ee20a i2c/qmsi: rename *_INT_PRIORITY to *_IRQ_PRI
This is to standardize the kconfig for specifying IRQ priority.

Change-Id: Iab10655c6fc6f17c0c6dd49cb7a4e74fabcf852c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 15:59:04 -07:00
Daniel Leung
36678521c3 i2c/dw: rename *_INT_PRIORITY to *_IRQ_PRI
This is to standardize the kconfig for specifying IRQ priority.

Change-Id: I3a51b35e633dc7b1b841e9fa504bf0cfc0d4d575
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 15:59:04 -07:00
Daniel Leung
546b8ade37 refactor common driver initialization priorities
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.

The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.

This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.

Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.

Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 15:58:29 -07:00
Daniel Leung
cecc4b0fb5 pinmux: remove base address and number of pins from kconfig
The pinmux base address and number of pins are now defined in SoC or board
header files instead of specifying them in kconfig. This is because
the pinmux ties directly to the SoC (or board expanders) so the base
address and number of pins do not need to be configurable in kconfig.

Change-Id: Ib6090d7d022b491f3fe8f522858281504c6302bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-28 15:58:29 -07:00
Daniel Leung
a2ba5d1ba3 spi/k64: remove SoC specific SPI constants from kconfig
The base address, IRQ line, chip select numbers, and clock
gating constants are static per SoC, so there is no need to
make them configurable in Kconfig.

Change-Id: I9f87ca29c28c38c42d4e4f1a3a41fa231f63ef03
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Daniel Leung
9c62a4a01f frdm_k64f: gpio: pinmux: remove base addr and irq from kconfig
The base address and IRQ line are static per SoC, so there is no need
to make them configurable in Kconfig.

Change-Id: Ib78401ff136c29642356f5bda9d6cd3e5c98bece
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Daniel Leung
7f6d4e37ee serial/stellaris: remove base addr, irq and clk freq from kconfig
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.

Change-Id: Ia252958d205e0100d1b92e2a12d4c22411bc94b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Daniel Leung
2a29e22c2f serial/k20: remove base addr, irq and clk freq from kconfig
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.

Change-Id: I79b142414143bc5ef585d3136a00375233de1723
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Daniel Leung
c215ef7213 kconfig: add conditions to device init priority defaults
This adds conditions to the default values for device init priorities,
and make them follow the dependencies on the config options. This cleans
up the resulting .config a bit, making it easier to read.

Change-Id: Ib05806ac6108d465ffe245142ecca7a51be6df22
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Daniel Leung
8df10d4584 kconfig: untangle ordering and dependencies
There are two major issues with the kconfig:

() Some of the config options have incorrect dependencies inside help
   under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.

() Since the SoC and board specific kconfig files are parsed first,
   the help screen would say, for example, CONFIG_SPI is defined at
   arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
   the actual config is defined in drivers/spi/Kconfig.

These cause great confusion to users of menuconfig/xconfig.

To fix these, the SoC and board defaults are now to be parsed last.

Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.

And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.

Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-26 20:36:32 -04:00
Ramesh Thomas
bb19e6f82f power_mgmt: Make names consistent with new RFC
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.

Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-26 14:35:11 -04:00
Dmitriy Korovkin
9b2452047d kernel: Combine nano_timers and nano_timeouts
To avoid code duplication nano_timers use nano_timeout
mechanism.

Change-Id: I916bffd2b86e29ee7b7ff7bbb009cd4c844e2a44
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-26 09:20:10 +00:00
Vinicius Costa Gomes
d872bb173c pinmux: Move STM32 boards to the pinmux model
This moves the STM32 based boards (Nucleo F103RB and STM32 Mini A15) to
the "new" pinmux model.

Change-Id: I190df271a6b83fafeec0b281cd4ee7cf13d7e7db
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-03-25 06:17:33 -04:00
Vinicius Costa Gomes
a12a25ad00 pinmux: Move the Freescale FRDM K64F board to the pinmux model
Change-Id: I50cf5fcf00481a3ebac07ced3aa6f7783765934f
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-03-25 06:17:33 -04:00
Vinicius Costa Gomes
649253c8a8 k64f: Fix mixing GPIO and pinmux concepts
Setting the direction of a GPIO pin is not the responsibility of the
pinmux "board" initialisation. This should be left for the GPIO
utilising application.

Some macros that were only used when setting the pin direction are
removed.

Change-Id: I5b63d52446a27fe539c89f0639a8dcadf5ea9f80
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-03-25 10:17:01 +00:00
Andre Guedes
db2e46319f arch: Convert returning codes to errno.h
This patch replaces all occurrences of DEV_* codes by errno.h codes at
the arch layer.

Change-Id: I1a1ab6d0481f3660ad032e2690d2577245fe1f34
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-23 15:49:40 +00:00
Daniel Leung
5b8c5fcc48 arm/fsl_frdm_k64f: remove kconfig default "n" for PWM
CONFIG_PWM is set to "no" by default, so there is no need
to do it in the SoC kconfig file. Also, setting CONFIG_PWM
there causes kconfig to think that CONFIG_PWM depends on
CONFIG_SOC_FSL_FRDM_K64F and gives warnings about
unmet dependencies if the certain combinations of CONFIG
are set.

Change-Id: I0028accfc4b585dcfa87e0d5733b789691a598e3
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-23 15:43:22 +00:00
Vinicius Costa Gomes
7f68afe382 k64f: Move pinmux specific code to pinmux.c
This makes this board more consistent with the rest of the code base.

Change-Id: I5641c6358e638a3585d2154e67d3536b11436e01
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-03-22 15:17:13 +00:00
Maciek Borzecki
f607954dbc arm: access svc instruction using halfword load in svc_handler
Use of `ldr` triggers unaligned memory access when loading SVC
instruction to r0. This is caused by the fact that SVC is a 16-bit
instruction, hence with a 2 byte offset, we are performing an non-word
aligned access. Prevent this by using `ldrh` to load a halfwords rather
than full words.

Change-Id: Ieae60c2ce86c6cfe15c89627d3a450797ce7e714
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-21 16:36:13 +00:00
Maciek Borzecki
61c0363257 clock_control/stm32f1: HSE support and PLL configuration cleanup
Add support for use of HSE (incorrectly named PREDIV1)as input of PLL,
along with HSE bypass for stabilized external clock, and XTPRE
prescaler. Update PLL handling so that we do not unnecessarily enable
PLL clocks, instead enabling only the clocks sources that are required
as per user's configuration.

This change allows higher SYSCLK clock values, up to 72MHz.

Change-Id: Ia7c2be3ce11ac0de2efa664b20e7ab5fddd57a51
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-21 16:36:13 +00:00
Maciek Borzecki
7205070402 soc/stm32f1: add embedded flash registers mapping
Add mapping of registers for embedded flash controller.

Change-Id: I81f891551124e9f124ff59dfe0b3c737ec5b3b63
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-21 16:36:12 +00:00
Vinicius Costa Gomes
facfc59464 pinmux: Convert return codes to errno.h
Before moving pinmux related code to 'drivers/pinmux' fix their return
codes to be consistent with the rest of the API.

Change-Id: Ie84f64e93745d44bef8b9d2119f6a05cdc8cb8c4
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-03-19 10:44:38 +00:00
Andre Guedes
ace49af6b0 uart: Enable QMSI driver for Quark D2000
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.

Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.

Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-18 23:33:06 +00:00
Maciek Borzecki
624c9e339a watchdog/iwdg_stm32: add driver for STM32 Independent Watchdog (IWDG)
Add a driver for Independent Watchdog (IWDG) commonly found in STM32
MCUs. The driver has been tested on STM32F1 family MCU.

Change-Id: Idc6ac35990e46901a206b4af0ce3767eb4875de9
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 20:57:26 +00:00
Maciek Borzecki
7c5cb7b85e soc/stm32f1/gpio: implement MCU specific GPIO input interrupt integration
Add necessary integration for supporting interrupts on GPIO input pins
for STM32F1 line of MCUs.

Change-Id: I0526a85cc3fdb96891c93ba4840ef27d613ab31b
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 20:57:16 +00:00
Maciek Borzecki
dd583518ee soc/stm32f1: AFIO registers mapping
Add mapping of Alternate Function I/O (AFIO) registers for STM32F1 MCU.

Change-Id: Id3e12290d6869c1f0506549f21407b3cd80d0a64
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 20:55:36 +00:00
Maciek Borzecki
33907674dd interupt_controller/stm32_exti: driver for STM32 EXTI controller
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.

Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 20:53:06 +00:00
Maciek Borzecki
e8d16b2985 soc/stm32f1: add IRQ numbers listing
Add a list of symbolic constants for IRQ lines available on
STM32F1 line of MCUs.

Change-Id: Iebf1847719c0db31cf852529fe5876e3cabbfe52
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 20:49:33 +00:00
Maciek Borzecki
a8700114b3 soc/stm32f1/pinmux: implement STM32 pinmux integration
Add necessary integration code enabling use of common STM32 pinmux
driver.

The alternate function listing currently consists of USART1 pins
only. The listing should be updated when support for more devices is
added.

Change-Id: Ic65aeea9df9aaea7636ecdd6996f56e6ef59dc2f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 16:27:04 +01:00
Maciek Borzecki
3642f9d6a3 soc/stm32f1/gpio: implement GPIO support
Add functions required for integration with common STM32 GPIO driver.

Change-Id: Ic6637e991f5c0cf659f3b927ed47ef482b13b64f
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-18 16:27:04 +01:00
Daniel Leung
e143d6dd59 clock_control/quark_se: fix default kconfig dependencies
() Moves the Quark SE clock control into its submenu.
() Fixes the dependencies in the SoC default Kconfig
   so the options are not displayed out of place in
   menuconfig.

Change-Id: Ifdf06242be8ceed03c2c657c942875a5a7f2750e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-18 11:27:09 +00:00
Anas Nashif
98ff441e53 kconfig: reorg ARM options and make things consistent
Make kconfig look the same for all architectures.

JIRA: ZEP-107
Change-Id: Ia8100194ec333fc07a1dff4f6f90364ce8bef4d3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-17 13:00:21 +00:00
Maciek Borzecki
3f5af00529 clock_control/stm32f10x: introduce driver for STM32F10x RCC
The patch adds a driver for STM32F10x series RCC (Reset and Clock
Control) subsystem.

The module is primarily responsible for setting up of MCU's clock
tree. In particular the driver sets up SYSCLK, PLL (with source
configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this
functionality, the subsystem can enable/disable clock signal for
particular peripherals, thus reducing the power consumption of the MCU.

The driver implements clock control driver API. However, subsystem IDs
being HW specific are exposed in driver public header that must be
included by callers. The driver registers a single device using a common
name STM32_CLOCK_CONTROL_NAME. The device is initialized at
the PRIMARY level with priority 1. This allows the initialization to
take place right after SoC initialization routine.

The driver depends on selection of SOC_STM32F1X config option and is MCU
specific.

Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-16 18:11:18 +00:00
Maciek Borzecki
1c78f3d39b st_stm32/stm32f1: introduce STM32F1x SoC family
The patch introduces a new family of SoCs based on STMicroelectronics'
STM32 MCU line. The patch introduces a basic arch/arm/soc layout along
with configuration of 2 MCUs from STM32F1 series: STM32F103VE and
STM32F103RB.

The patch assumes that other MCUs from STM32 family will be included
under arch/arm/soc/st_stm32 tree, to achieve the following layout:

arch/
  arm/
    soc/
      st_stm32/
        stm32f0/
        stm32f1/
        stm32f2/
        ...
        stm32l0/

Most of the configuration within a single MCU family (ex. STM32F1) is
shared, however individual MCUs differ with respect to SRAM size, flash
size or the number of available peripherals. The patch assumes that per
MCU line Kconfig.soc.family file should introduce basic setup for given
series. This can be further tuned by per MCU files, with
Kconfig.soc.stm32f103rb and Kconfig.soc.stm32f103ve as examples.

Each family defines a configuration option, ex. CONFIG_STM32F10X, while
individual MCUs define a corresponding per MCU config options,
ex. CONFIG_STM32F103VE.

From the menuconfig perspective, the user is presented with a family
selection under General Platform Configuration/SoC Selection.  A
specific MCU model can be selected by accessing General Platform
Configuration/STM32F1x MCU Selection, with the default entry being
selected by the board configuration.

Change-Id: I22e4defd4a08ed1b2e2cad0e214b34f565e08831
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-16 18:03:13 +00:00
Daniel Leung
52caf8cfc8 arm/fsl_frdm_k64f: fix kconfig hierarchy
This makes sure the CONFIG_GPIO_K64F_* kconfig options have correct
dependencies. Or else CONFIG_GPIO_K64F can be disabled, but all
the CONFIG_GPIO_K64F_{A,B,C,D,E} are enabled.

Same goes for SPI, FTM and pinmux.

Change-Id: I8d225dea714081b14b19006d61b8f3f6afafa5ee
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-15 21:39:15 -04:00
Daniel Leung
ef83c14c4a arch: move kconfig SoC selection to top level
The SoC selections for each architecture are moved to the top level
in menuconfig and xconfig. This makes it more intuitive to select
architecture -> SoC -> then board, avoiding an additional trip to
go into the architecture menu to select SoC.

Change-Id: I57a78a09adfc4bb12423915b6ad14ceb74381a2b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-15 21:39:14 -04:00
Daniel Leung
25459c137c arch/x86: limit floating point kconfig options to supported CPUs
It makes no sense to allow enabling support for floating point
registers when the CPU has no FPU.

Change-Id: If51187033fc84957721d87fa6e79ef31124f4b14
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-15 21:39:14 -04:00
Daniel Leung
1eddc97b74 arch/x86: hide CPU family Kconfig options
These options should be selected by individual SoC automatically,
and should not be visible options. Or else it would be possible to
select Quark SoCs and telling Kconfig it is from Atom family (which
is incorrect).

Change-Id: I17a6cf713378333e0e7942aa49b381b5eb9526b5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-16 01:38:07 +00:00
Anas Nashif
e65df2562d ia32: compile with soft-float when using IAMCU ABI
When building with IAMCU, make sure we set the soft-float, otherwise
build would fail with unsupported instruction errors.

JIRA: ZEP-103

Change-Id: I7a5f107a2df50799a7f6dd4aba36c1a977c1461d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-14 20:54:08 +00:00
Anas Nashif
64b8a3868e kconfig: move IAMCU option under processor capabilities
Change-Id: Ieaba79e0750ed10f5d4b7204146dbc47775695bf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-14 16:50:51 -04:00
Anas Nashif
84a5557eb3 kconfig: move ARM bootloader options to bootloader menu
Change-Id: Ia3612413f68691d9e9364f278aada6b9c3296fb5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-03-14 16:50:50 -04:00
Dan Kalowsky
983ec93bd4 arch: arm: move nmi to common location
The nmi_on_reset.S functions are used by all ARM platforms.  It
makes no sense to repeat the same code for all platforms.  Moving
the code from each SOC implementation to arch/arm/core.

The same treatment for the NMI_INIT() macro.  Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.

Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-03-12 03:20:36 +00:00
Sergio Rodriguez
07da8afd4d aio: QMSI analog comparator driver
This creates the QMSI comparator driver which is simply a shim driver
based on the comparator driver provided by QMSI BSP.

In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_AIO_COMPARATOR=y
CONFIG_AIO_QMSI_COMPARATOR=y

Origin of the file: Original

Change-Id: Iad01cb80f7bb1eff1710cd76cd0afeb70c311e04
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
2016-03-12 03:17:59 +00:00
Andre Guedes
7633279d4a uart: qmsi: Add support for IRQ APIs
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.

Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.

Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.

Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:55:13 +00:00
Andre Guedes
d95d6c63a1 uart: Introduce QMSI shim driver
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.

This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.

In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y

This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.

Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 23:54:59 +00:00
Juan Manuel Cruz
d151776e59 debug: thread monitor allow to access more thread information
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.

Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.

By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.

It also allows a task to access its kernel task structure
through the first parameter of the thread.

This allows a debugger application to access the information directly
from the thread context structures list.

Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
2016-03-11 22:11:39 +00:00
Andre Guedes
8337953197 Remove unused macro UART_IOAPIC_FLAGS
This patch removes the macro UART_IOAPIC_FLAGS from Quark SE and D2000
soc.h since it is not used anywhere in the code.

Change-Id: I0fd42fac2f02e8617bd92c73c1a0354ef2d7a71a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-03-11 00:15:49 +00:00
Andrew Boie
97594df321 iamcu: fix -fstack-protector
One of the tricks that GCC's stack protector does is to stick a
sentinel value on the stack at the beginning of the function, and
check if it is still there when the function is about to return.
However, since this function switches stacks that fails and we get
a stack protector exception before main() even starts.

Change-Id: I2acba8b8c822d7447d8e371bb72603f36e87f54b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-10 23:28:28 +00:00
Benjamin Walsh
7708710229 Revert "arch: arm: set the architecture via Kconfig"
This reverts commit 3f6884902b.

This commit does not work as intended: the part in arch/arm/Makefile
gets ignored and -mcpu=cortex-m3/4 does not get passed to gcc. It seems
that the zephyr toolchain does not care, but the vxworks assembler
chokes if it is missing, and thinks the CPU does not support thumb ISA

Change-Id: I14d11d3e22dac4952bdab3eb9e2d1c36b1a686c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-03-10 16:31:26 -05:00
Jeff Blais
995a9ba72a arm: K64 SPI module driver
Support for Freescale/NXP K64 SPI modules, limited to:

- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats

Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).

Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:50:16 +00:00
Jeff Blais
f428d511f3 arm: config settings for frdm_k64f internal clock dividers
Internal K64 SoC clock dividers were hard-coded. They've been replaced
with config options.

Change-Id: I583307f2e3341525f4445e9ceb89d36634b12802
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:50:01 +00:00
Jeff Blais
1f90470a27 arm: K64F Pulse Width Modulation (PWM) support
PWM support using the Freescale K64 FlexTimer Module (FTM)

Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 15:49:44 +00:00
Jeff Blais
52b499fd1f arm: Freescale K64/FRDM-K64F Pinmux support
K64 pinmux support is created as a normal driver.

As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific.  Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.

Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface.  Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.

The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO.  This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.

This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.

The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):

warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]

Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 11:58:02 +00:00
Jeff Blais
0fd7af2a52 arm: Freescale K64 GPIO driver
Basic driver support for the Freescale K64 GPIO module.

Note that only pin direction, read and write are supported.

Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
2016-03-09 06:39:16 +00:00
Andrew Boie
4a4e82b0c5 arc: remove CONFIG_SW_ISR_TABLE_BSP
It is semantically identical to CONFIG_SW_ISR_TABLE.

Change-Id: Iff0c47166ee6fb1fd8a0991a67bc863d45c32559
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
d9df4758e4 arc: remove SW_ISR_TABLE_STATIC_CUSTOM
This scenario is no longer supported in code; the Kconfig
didn't actually do anything.

Change-Id: Ic48bffb5180c4f72bc9c5d85cf18b1072432b951
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
e2283a2c58 arc: move vector and sw isr table to core code
Change-Id: Iea7ce4248ff3aaba2a5736c5e50f17c7b8b344af
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
6d972a33cf arm: don't build sw_isr_table if disabled
This table was still being added to ROM even if
CONFIG_SW_ISR_TABLE=n.

Change-Id: Ia0de1349960af1c62e88344b3d5b6655b638219b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
bd7d71efdc arm: remove SW_ISR_TABLE_STATIC_CUSTOM
This config option is no longer implemented and doesn't actually
do anything.

Change-Id: I57ab7ba688f57da21f8a58f62ea37dc6b8daaf18
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Andrew Boie
5415d945f8 arm: move irq_vector_table to common location
We don't support hard-coding vectors in this table anymore.
If someone really wants to do this, they can set
IRQ_VECTOR_TABLE_CUSTOM and define their own.

Change-Id: I45f49782ba5fefb0a02eab02ec96efd0019bc6d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-03-08 09:58:20 -08:00
Dmitriy Korovkin
41e55f13ad Kconfig: CPU_MIGHT_SUPPORT_CLFLUSH removal.
Remove CPU_MIGHT_SUPPORT_CLFLUSH as excessive.

Removal the flag requires adding per-SoC cnfiguration,
as some Quark models support clflush instruction, but
some do not, even on compiler level.

Change-Id: I655cba00c629db55d1813c199a2fe08b2d60ef4f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-07 20:25:22 +00:00
Dmitriy Korovkin
287d16d83f x86: Fix cache flush code dependencies
Rearrange the source code in order to place functions
depending on clflush support detection into the proper
section.

Removed dependency between CACHE_LINE_SIZE_DETECT and
CLFLUSH_INSTRUCTION_SUPPORTED or CONFIG_CLFLUSH_DETECT.

Change-Id: I62ba5199763ed16c71f1d2fa372f6cc99b303e6a
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-03-07 20:25:22 +00:00
Daniel Leung
e643cede3a uart: add ISR callback mechanism for UART drivers
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.

Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.

This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.

Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.

This also addresses the following issues:

() UART driver for Atmel SAM3 currently does not support interrupts.
   So remove the code from vector table. This will be updated when
   there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.

This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).

Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-03-05 13:37:57 +00:00
Dan Kalowsky
3f6884902b arch: arm: set the architecture via Kconfig
Currently the build system has hardcoded values for the -march/-mcpu
which identify what architecture should be used when compiling ARM code.
For processors such as the STM32 this will need to be defined by a per
SOC process.

Change-Id: Ia8158cd687d8d0432ea420e204bb2bc67d33a054
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-03-04 15:08:40 +00:00
Yannis Damigos
baddeadda1 arch: & kernel: Updated Kconfigs to remove errors in html generation
This patch updates some help sections to remove the "ERROR:
Unexpected indentation" messages during hmtl documentation
generation.

Change-Id: Idcdc17727b921b6145f9eb28d85975ceca273ce2
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-03-04 13:26:15 +00:00
Anas Nashif
2ed89a49ee rtc: enable clock-gating for RTC on Quark SE
Clockgating was disabled for RTC and disabling RTC had no
effect on Quark SE boards.

Change-Id: I67448d5582a206fc7a68d763d504e9f743043b53
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-29 16:53:36 +00:00
Ido Yariv
744f4fba3d QEMU: Fix the pin2irq translation function
ia32/soc.h is only used by QEMU, but QEMU's INTx routing does not follow
the "standard design consideration".
Instead, the pins are swizzled based on the PCI slot. They are then
routed to IRQs based on the PIIX PIRQ configuration.

For simplicity use hard-coded values for the PIIX PIRQ configuration,
though it may be desirable in the future to determine these dynamically.

Also change the number of PCI buses to 1 and remove irrelevant comments.

Change-Id: I1592009a43dd8a9c5a7c54788fba52f14687ba35
Signed-off-by: Ido Yariv <ido@wizery.com>
2016-02-26 17:05:30 +00:00
Andrew Boie
e444825ee3 irq: formalize external zephyr interrupt API
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.

Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.

Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-26 15:53:22 +00:00
Daniel Leung
1d88a8618d arc: remove defaults for IRQ priority levels
The deleted defaults cannot be overriden by defaults defined
in SoC's Kconfig file. The number of IRQ priority level was
always one, and this caused some code to be dropped within
the fast IRQ handling code. When the electrons aligned in
certain way, undesired effects were observed (e.g. exception,
faults, etc.) when regular IRQs were mixed with fast IRQs.

Moreover, ARC cores are high configurable on hardware level.
So let the SoC config define these values instead.

Change-Id: I2a338d2efc814c46b0f68ab100fc0f66ae0fb60c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-26 15:20:10 +00:00
Benjamin Walsh
fd1aa8575b x86: move reboot via RST_CNT from galileo to generic x86
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.

Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-25 16:52:27 +00:00
Andre Guedes
536d6ec396 i2c: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/i2c/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: If3c260b9a2fa095de47a99eb7fa5b947efefe9b1
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 14:34:24 -03:00
Andre Guedes
1eaaa6434b spi: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/spi/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 14:26:23 -03:00
Andre Guedes
55e93f203c gpio: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/gpio/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.

It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.

Change-Id: Id00f7907fa55025011dabce6e282a9623be23831
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-24 17:05:52 +00:00
Tomasz Bursztyka
16cbf0ea97 quark_se_ss: Add default SPI configuration values
Base address registers and IRQs are set in Kconfig.
Set proper SPI default to various quark_se_ss based boards.

Change-Id: Iadaae551f441457bef334f94f68cafa7c3e499d0
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-20 15:39:16 +00:00
Tomasz Bursztyka
ec678375a3 spi: dw: Quark SE Sensor Sub-System support
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.

Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
 - centralize common macros and definitions into spi_dw.h
 - have a specific spi_dw_quark_se_ss_reg.h for register map, clock
   gating and register helpers dedicated to Quark SE SS.
 - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.

GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.

Adding proper interrupt masks to quark_se_ss soc.h file as well.

One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.

Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.

Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
  handler, but it does not harm doing it anyway and because Quark SE SS
  requires to clear up interrupt as soon as they have been handled,
  introducing a clear_interrupts() function called at the and of the ISR
  handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
  might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
  masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.

Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-20 15:39:16 +00:00
Andre Guedes
424cd841e2 spi: Enable QMSI driver for Quark D2000
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.

Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.

Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:57:45 +00:00
Andre Guedes
2a1871f405 watchdog: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/watchdog/Kconfig because 1) most
of the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).

For Quark D2000, the IRQ priority options (WDT_DW_IRQ_PRI and WDT_QMSI_
IRQ_PRI) values are set to '0' since the priority information is ignored
by the interrupt registering system (the interrupt vectors are fixed in
this SoC).

Change-Id: I8f36c0f0e56211cdee3f2c6fc90c7dcac0a1b5aa
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:20:33 +00:00
Andre Guedes
055d775be6 rtc: Remove default value from platform-specific options
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/rtc/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).

For Quark D2000, the RTC_IRQ_PRI default value is set to '0' since the
priority information is ignored by the interrupt registering system
(the interrupt vectors are fixed in this SoC).

Change-Id: I70de889cfd22e65f0e7acf7e57ddc6439f028394
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 14:20:32 +00:00
Vinicius Costa Gomes
0e60f325f8 gpio: qmsi: Fix overwriting name set by the driver's Kconfig
The name already set by the driver's Kconfig is correct, so overriding
it only causes confusion.

Change-Id: Ia6405786fdfdf103c922517c8140a07a9de387e0
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-20 14:18:36 +00:00
Andre Guedes
2b608b1e59 gpio: Enable QMSI driver for Quark D2000
This patch fixes the GPIO QMSI shim driver so we are able to use it in
Quark D2000 based platforms. To enable this driver we have to add a few
 #if guards because some macros and functions (e.g. QM_AON_GPIO_0 and
qm_aon_gpio_isr_0) are not defined in QMSI headers from Quark D2000
(this SoC doesn't support the Always-On GPIO controller).

This patch also adds the QMSI driver default options to arch/x86/soc/
quark_d2000/Kconfig.

Change-Id: Ia16a345e1de3008f167ed66f891834607c05f4a2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 13:04:34 +00:00
Vinicius Costa Gomes
821212c3df drivers: gpio: Add support for AON GPIO to QMSI driver
This adds support to the AON GPIO controller using the QMSI driver.

In order to enable it, the following configuration options must be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH TO LIBQMSI"
CONFIG_GPIO_QMSI=y
CONFIG_GPIO_QMSI_AON=y

Change-Id: I5a1a232d97741ad7fdbf40d8aea5a835e5b4e724
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-20 13:02:49 +00:00
Daniel Leung
fb84242956 x86/quark_se: don't start ARC if reset vector is NULL
This adds a NULL check against the reset vector for ARC.
If the reset vector is null, do not start the ARC core
as there is nothing to execute, and will probably cause
the whole SoC to stall.

Change-Id: I78d77b3e5940a205e05c13369f889cf9c5955487
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-20 12:59:07 +00:00
Andre Guedes
6b23dc40d1 watchdog: Set DW driver as default for Quark SE and D2000
This patch changes both Quark SE and D2000 Kconfig files to enable the
WDT_DW driver by default if the WATCHDOG is enabled. This way, we keep
it consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).

Change-Id: I9d8b81c0e659b1408137deb71e33dacf6d4108c2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:52:35 +00:00
Andre Guedes
a4cf537d65 rtc: Set DW driver as default for Quark SE and D2000
This patch changes both Quark SE and D2000 Kconfig files to enable the
RTC_DW driver by default if the RTC is enabled. This way, we keep it
consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).

Change-Id: I4910e501c105b6218d046080c47b1e7a42eced92
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:52:00 +00:00
Andre Guedes
ec7c6a80fc i2c: Enable QMSI driver for Quark D2000
This patch fixes the QMSI I2C shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in i2c_qmsi_init() because the macro QM_I2C_1
is not defined in QMSI headers from Quark D2000.

Since this drivers is now properly tested with Quark D2000, this patch
sets the QMSI driver default options in arch/x86/soc/quark_d2000/Kconfig.
It also adds the wiring information required to test the i2c_lsm9ds0
sample app in the Quark D2000 CRB.

Change-Id: I4be03c09304da5a66ac663e48b1d72225eb5651d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:51:49 +00:00
Andre Guedes
fa1e56520b qmsi: Enable both I2C controllers by default
In case the I2C_QMSI driver is selected by the user, enable both I2C
contollers by default. This is the default behavior for I2C_DW driver
as well.

Change-Id: If3dc8eb0a266fde7f598f7b12370e5be903aafed
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-20 02:51:19 +00:00
Benjamin Walsh
74cd948ed3 x1000/pci: fix coding standards
Always use braces, even on one-line code blocks.

Change-Id: Ic9e60db7f851d2fbee5bfd79cd810df23c0c5db0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-17 21:51:57 +00:00
Ramesh Thomas
3888735e0d adv_power:Advanced Power Management APIs
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.

Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 11:20:32 -08:00
Ramesh Thomas
72e248b11b adv_power:Rename PM functions according to coding convention
Renamed functions and labels used in power management code
according to coding convention.  Only doing this to relevant
functions and not touching functions that will be removed in
future patches.

The stack used during resume would be necessary so
renamed that too.

Change-Id: I2f09a349b0f0fd6520c11b4cd73f4c8e1a13f100
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 10:57:51 -08:00
Ramesh Thomas
c1a2523445 adv_power:Fix build error when ADVANCED_IDLE flag is enabled
GlobalTss is not defined anywhere. This was originally designed
to be used by power management code to switch thread context to
kernel resume location. An alternative to this method would be
implemented.

Change-Id: I9ae14ba14f9573d8bd8579869cdee9cf85a5684a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-02-12 10:57:51 -08:00
Sergio Rodriguez
4dee326306 tickless idle x86: Tickless idle support on nanokernel for x86
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture

Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
2016-02-11 19:10:24 +00:00
Andrew Boie
f21ff23310 x86: add debug function to dump IDT
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.

Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-10 16:02:17 +00:00
Andrew Boie
313ed31253 x86: fix IDT entry definition
It was, in a nutshell, wrong. Fortunately, the incorrectly
specified fields weren't being used by anything.

Change-Id: I0fa63fa16a267502744a7a2c82865c7de8b5446e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-10 16:01:26 +00:00
Andrew Boie
4455ee6d87 ARM: rebase available priority levels to 0
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.

Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-08 21:47:35 -05:00
Andrew Boie
b052bd282a x86: intconnect: convert some DEBUG to __ASSERT
DEBUG isn't tied to any config option. Just use assertions.
Most of the time return values aren't being checked anyway.

Change-Id: I7457dcf00e18505bd6bcd98d46288545c03b5fbc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-08 21:45:07 -05:00
Andrew Boie
9fc3afc339 x86: rebase priority levels
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.

Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.

It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.

In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
  generate_interrupt_vector_bitmap() also ensures that there are
  sufficient free vectors within a priority level.

Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-08 21:45:07 -05:00
Andrew Boie
6e83effea8 iamcu: fix dynamic exceptions
The argument to _common_dynamic_exc_handler() in the C domain
was still being set up the Sys V way. Arguments are popped off the
stack in reverse order, so _ExcEnt pushes *pEsf for arg 2, and then
the stub pushes the stub_num for Arg 1.

For IAMCU case, *pEsf is placed in EAX which is where argument 1
lives; static exception handlers take just one argument. However
since we're calling _common_dynamic_exc_handler we also need to
supply the stub_id, which we put in EDX (where arg 2 goes).

Rather than swapping things around at runtime the prototype for
_common_dynamic_exc_handler() is adjusted to fit the calling
convention in use.

Change-Id: Id43cbc3b86d90f941cea771678b2796ae5f1358d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-08 21:45:07 -05:00
Daniel Leung
8d48828b3c i2c: adds driver for Atmel SAM3
Adds the driver to utilize the I2C/TWI interface on Atmel SAM3
family processors for I2C communication.

Note that this currently only supports master mode. Limited
testing has been done using the Fujitsu FRAM sample app.

Change-Id: Ibdb8277e47dd9450b49a66a95421eb1ffb1c4eb4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-08 21:45:07 -05:00
Daniel Leung
dc8ddfcd1d arm/atmel_sam3: add PDC register struct
Adds the struct to describe PDC (Peripheral DMA Controller).
The PDC is being used by peripherals to initiate DMA
transfers.

Change-Id: Ida2a20810c4f2ef972e9669c45e22da07c1576ab
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-08 21:45:07 -05:00
Juan Manuel Cruz
908cb87978 logger: support for iamcu abi core
Adds logger support to iamcu core for the following features:
- context switch logger
- interrupt logger
- sleep logger

Change-Id: Icfbd5fa787633045ba2895e8c28b652c55575b86
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:25:30 -05:00
Andrew Boie
5cc61d5406 iamcu: interrupts: fix comment
Was only true for SYSV version.

Change-Id: I2a73c027b4a68c879c66338713f2d50a400d6c26
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:29 -05:00
Andrew Boie
fb0f918cb1 iamcu: fix dynamic IRQs
The common stub code didn't prefix the arg to 'mov' with a
'$', causing the assembler to generate code which tries to
dereference the argument before sticking it in EAX.

Change-Id: I0e201f799565d9709e3969b82ae2eb3f93a78b3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:29 -05:00
Andrew Boie
0b1d68af27 iamcu: fix irq_offload()
The ASM stub invoked by irq_offload() wasn't switching to the
interrupt stack.

Change-Id: I0c52092a50396aa892e71f0501bbda38395d7554
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:29 -05:00
Andrei Emeltchenko
28198fcca5 quark_se: Remove pipe config defaults
Making pipe driver configuration for quark_se makes no sense for the
board. First it simply wrong since IRQs for serial are 5 and 6 and
when using PIPE care should be taken to allocate right way serial and
Bluetooth for the given UARTs.

Change-Id: I4cb3227a8be34fbfa089a457e6d9977e4adcfd19
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:25:29 -05:00
Juan Manuel Cruz
eb8ab24ae8 build: make QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol editable
QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol must be editable through
configuration menus and configuration snippets (QA request).
Adding a title for the kconfig symbol makes it editable.

Change-Id: Id0147a50d94033e1392327935bcbfbdb5a9eedd8
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:25:29 -05:00
Vinicius Costa Gomes
40f8914376 spi: Add QMSI-based implementation
This driver uses the QMSI library and mostly translates calls from the
Zephyr API to QMSI ones.

This driver conflicts with the native driver implemenation. In order to
enable it, you must set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI"
CONFIG_SPI_QMSI=y
CONFIG_SPI_QMSI_PORT_0=y
CONFIG_SPI_QMSI_PORT_1=y

Missing:
 - Support for using a GPIO pin as Chip Select;

Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05 20:25:29 -05:00
Anas Nashif
5cf903f22b x86/iamcu: build with -miamcu only when CONFIG_X86_IAMCU=y
Change-Id: I57727893f37bea88ab3b6e6f47f36569d9eef97d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:29 -05:00
Anas Nashif
c4c919dbe0 Move compiler optimization to the SoC
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.

For IAMCU platforms, use the right architecture and tuning.

-march=lakemont -mtune=lakemont -miamcu -msoft-float

Change-Id: I458afca5feb9be5de8dcae559d6dcac3c6d6a2a7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:29 -05:00
Daniel Leung
a8a5597e94 arm/atmel_sam3: fixes incorrect rename to SYS_INIT()
Change-Id: I0c2ce73cd758e5e7472fa7bf66e48d12b1cdf6af
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:29 -05:00
Daniel Leung
bf0e5089dc arm/atmel_sam3: fix SRAM base address for SAM3X8E
The default Kconfig option is missing a condition for the SRAM
base address on SAM3X8E. Add it back so the correct default
can be used.

Change-Id: Ib4103366f693648c76630cbbd71ca98109381d5c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:29 -05:00
Daniel Leung
f6a5bfcfa1 gpio: add driver for Atmel SAM3 PIO controllers
The PIO controllers on Atmel SAM3 family processors can be
used for GPIOs, so this is the driver.

Change-Id: I3d5712f3a0a71025b820ca1c08dd767ee1e136d8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:29 -05:00
Andre Guedes
dacf54de68 i2c: Enable interrupts for QMSI shim driver
Due to an issue with the interrupt-based transfer API from QMSI driver,
the 'transfer' callback from the shim driver (i2c_qmsi_transfer) is
implemented with polling APIs. This is not ideal because we are not able
to sleep the current thread (so another task can be scheduled in) while
the i2c operation is carried out.

The interrupt issue with the QMSI driver has been solved then this patch
fixes the shim driver so it uses the interrupt-based API and adds extra
code to handle the thread synchronization.

Finally, this patch also moves all 'struct device' related definitions
from the bottom to the top of the i2c_qmsi.c file so the DEVICE_GET
macro can be used in transfer_complete() and removes the init.h include
since it is not needed anymore.

Change-Id: I7ef7ce4cea6fcc939e310e5fe12c406645f6a16e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-05 20:25:29 -05:00
Ido Yariv
3db6a541c8 Quark: Set up IRQ routing for PCIe explicitly
IRQAGENT3 is initialized explicitly, but IRQAGENT0 isn't and its value
is based on the value the BIOS or bootloader had set before. Fix this by
explicitly initializing IRQAGENT0, and swizzle the IRQs to reduce
conflicts.

Update the pci_pin2irq function to accommodate for these changes.
Also remove pci_irq2pin function since it is unused.

Change-Id: I7b1dfc7659ab227fe66711a3af5a1f34fd4a7972
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
2016-02-05 20:25:29 -05:00
Ido Yariv
6b6ef8bbb7 QEMU: Add optional PCI support
To debug PCI drivers on QEMU, it may be desired to enable CONFIG_PCI for
QEMU targets. Since the PCI driver requires a SOC pin2irq translation
function, add such function to IA32's SOC header file.

Change-Id: Icf6f88aa14ae29d70fe12dc80a708e6a2e992ba8
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
2016-02-05 20:25:29 -05:00
Andrew Boie
f0a1d22f28 x86: leave the GDT in ROM by default
We don't normally need a runtime-mutable GDT; make it optional to
activate a second copy in RAM. Regardless of whether it is in RAM
or ROM, it can be accessed by the '_gdt' symbol.

Change-Id: I5ce955f4b8875eb60040917ceaacc07d7e5941ac
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:28 -05:00
Daniel Leung
cb76f11259 arch/arc: fixes native C version of atomic_nand
Change-Id: I2f493e2c7cb841ef1273e628701d3b087d402e3f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:28 -05:00
Anas Nashif
abb6e223cf NBLE: Nordic BLE is not a feature of quark se
Move BLE configuration to board and enable GPIO for NBLE.

Change-Id: I99c309656430936edf6766fc99fe83b011801bb4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:26 -05:00
Andrei Emeltchenko
baeb34a950 Bluetooth: nble: Add UART driver for Nordic BLE chip
Adds basic support for communication with Nordic BLE (NBLE) chip
connected to UART.

Change-Id: I3651e291ec18805a63ecd3d240dce62273e3c498
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:25:26 -05:00
Andrew Boie
897ffaeb2c irq: rename irq_connect() to IRQ_CONNECT()
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.

Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:25 -05:00
Benjamin Walsh
a4ec963138 init: use SYS_INIT() where it makes sense
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.

Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:25 -05:00
Benjamin Walsh
d340d4cb3f device: use DEVICE_INIT everwhere
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().

Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:25 -05:00
Benjamin Walsh
0303d8cab9 device: rename SYS_DEFINE_DEVICE()
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.

Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:25 -05:00
Andrew Boie
2ee9aca31a irq: size _irq_to_interrupt_vector_table
Most systems have far less than 256 IRQ lines available, so
save some bytes in ROM by making this a config option.

On systems with MVIC, omit the table entirely as the mapping
is fixed.

The build cmd_gen_idt is slightly easier to read and will fail
immediately if any of the commands in the sequence error out.

Change-Id: I411f114557591e5cd96b618e6f79f97e8bedadf0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:25 -05:00
Benjamin Walsh
bfc27206b2 device: rename DECLARE_DEVICE_INIT_CONFIG()
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.

Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:25 -05:00
Andrew Boie
bd18487727 x86: if no dynamic irqs, omit _interrupt_vectors_allocated
This bitfield is only needed to find unused vectors in the IDT
for installing dynamic interrupts.

Change-Id: I34ecd330774a0e50f240b4396527682eded29627
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:25 -05:00
Andrew Boie
630280c464 build: fix issue with static interrupts on ARC/ARM
Static interrupts rely on a trick where the _sw_isr_table array
is declared with each element in a different .gnu.linkonce
section, initially pointing to the spurious IRQ handler.

When drivers or apps declare their own interrupts, they override
the element with their own containing the real ISR and parameter.

However, this only works if the initial declaration of the
_sw_isr_table array with the spurious handlers is linked last.
App-specific code was being linked later than the core code,
causing static interrupts declared in apps not to be installed
correctly.

If the _sw_isr_table is moved from SOC-specific code to core arch
code, interrupts configured under soc/ should still also work.

Change-Id: Iec7df47386dfbbf2956a807da27dc8aa6e01b268
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:25 -05:00
Fabien Chereau
78b2670032 irq: added a check for dynamic IRQ table overflow
Change-Id: I0128f752f8e42ee38331fa937b7616354bf346e0
Signed-off-by: Fabien Chereau <fabien.chereau@intel.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
c5bb958db4 arm: add software reboot for QEMU
This simulates a reboot by jumping back to the address stored in the
reset vector in vector table found at address 0. It is supported from
interrupt/exception level, which means that sys_arch_reboot() in this
case finds out if it is called from thread mode or handler mode, and in
the latter case, it unwinds the nested exception stack as needed.

Change-Id: Ib67f850f8411f1ee8fc592a5f31f2f70d0af14a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
62c65d7f00 arm: in non-XIP image, make __start alias of __reset
The bootloader expects the entry point to be called __start, not __reset.

Change-Id: I5a5f7f45c248b9398e58fb026c731f8617fe4856
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
bd94d98255 arm: add connecting exceptions at runtime
Add sys_exc_connect() (and its x86-compatible alias nanoCpuExcConnect())
that allows connecting an exception handler at runtime.

The current implementation is a bit of a bastard, to avoid disturbing
the current implementation of the exception handlers. Instead of hooking
_exc_wrapper() in all vectors and adapting the exception handlers, the
current exception handlers are still hooked directly in the vectors.
When an exception is hooked at runtime, _exc_wrapper() gets installed in
the vector and the real handler gets inserted in _sw_exc_table; this
means that the scheme only works with non-XIP kernels.

This should be enhanced so that _exc_wrapper() is hooked in all vectors,
and that current exception handlers (for faults mostly) are reworked to
be inserted in the _sw_exc_table and wrapped in _exc_wrapper().

Change-Id: Icaa14f4835b57873d2905b7fbcbb94eeb3b247d1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
f8807dae89 arm: rename _VectorTableROM
For non-XIP systems, it's not in ROM, so remove the "ROM" part. Adapt it
to coding conventions at the same time, and export it to C code.

Change-Id: Id09a6be8bc9c462667ed71b53be7fa5382c88db3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
cfac189f98 arm: refactor fault handling stack pointer passing
Find out on which stack the stack frame for an exception is in the assembly
code (__fault()) rather than in C (_Fault()). This will allow pushing
more registers on the stack when debugging is enabled.

Change-Id: I1c510b83098536f8930392b17df27511ccd04d80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
c4a093a24e arm: rework _ScbSystemReset() into sys_arch_reboot()
Rename the function and allow it to handle the 'type'
argument, which is ignored in this case.

Change-Id: I3d3493bea4511b2d026747505e7e52c5acc85012
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
2ace19ede8 arm: allow accessing GPRs in ESF by their real name
The ESF was built using the 'alias' names of the GPRs (a1, lr, pc, etc)
rather than their 'real' name (rN).

Change-Id: I49cae5e94869a79a3165dc7f2347d8cec39dbf67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
4465cf47e9 arm/reset: relocate the vector table when a non-XIP image
The processor is made aware that the vector table built in the image is
located at the start of SRAM in the case of a non-XIP image, rather than
at 0 in as is the case in XIP images.

Change-Id: I40b28ca32daf3e8930f103224766ed4e0ccc88e0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
21628d41d0 arm: add support for linking images entirely in SRAM
The image will be linked at a different address and with different
ROM/RAM sizes to allow running a bootloder image that loads a payload
image. The addresses/sizes depend on if it is a XIP image or not
(CONFIG_XIP), and in the case of a XIP image, if it is a bootloader
image (CONFIG_IS_BOOTLOADER) or not.

In the case of a bootloader, it is given the full ROM and
CONFIG_BOOTLOADER_SRAM_SIZE kB of SRAM.  When not a XIP image, it is given
the full SRAM minus CONFIG_BOOTLOADER_SRAM_SIZE kB, and is linked at the
start of SRAM.

Change-Id: Ibbb693c7bff022f313dac40f21c04a61f4bed115
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
d04e3fc134 arm/frdm_k64f: only leave space for security in XIP images
This board needs 16 bytes to be written with a specific value when the
target boots. This is only necessary when running a XIP image which
exists around those 16 bytes.

Change-Id: Ifd26b3842f09137765d9c7d1678476bfda8a563f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
2016-02-05 20:25:24 -05:00
Benjamin Walsh
2858cbf829 idle: fix tasks waiting when NANO_TIMEOUTS is enabled
Fix an issue where, if a task is pending on a nano timeout, the duration
it wants to wait is not taken into account by the tickless idle code.
This could cause a system to wait forever, or to the limit of the timer
hardware (which is forever, for all intents and purposes).

This fix is to add one field in the nanokernel data structure for one
task to record the amount of ticks it will wait on a nano timeout. Only
one task has to be able to record this information, since, these waits
being looping busy waits, the task of highest priority is the only task
that can be actively waiting with a nano timeout. If a task of lower
priority was previously waiting, and a new task is now waiting, it means
that the wait of the original task has been interrupted, which will
cause said task to run the busy loop on the object again when it gets
scheduled, and the number of ticks it wants to wait has to be recomputed
and recorded again.

Change-Id: Ibcf0f288fc42d96897642cfee00ab7359716703f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:24 -05:00
Peter Mitsis
8e35cc8eb4 build: Add C++ support
Adds C++ support to the build system.

Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:23 -05:00
Peter Mitsis
a0e4568760 c++: Add extern "C" { } block to header files
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.

Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:22 -05:00
Jesus Sanchez-Palencia
6504b7e72a gpio: Add QMSI-based implementation
Introduce the GPIO QMSI-based implementation. This is basically a
shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers.

This is an alternative driver that conflicts with the previous
GPIO_DW implementation. In order to enable it you must set:
- CONFIG_GPIO=n
- CONFIG_GPIO_QMSI=y
- CONFIG_GPIO_0=y
- CONFIG_QMSI_DRIVERS=y
- CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI"

Note that this driver currently only supports one controller instance,
GPIO_0. It is implemented this way due to a limitation from the current
version of QMSI. QMSI versions later than 1.0 doesn't have this
limitation.

Missing:
- support multiple controller instances (gpio_0, gpio_1, etc);
- enable level triggered interrupts in sync with system clock,
through setting INT_CLOCK_SYNC properly.

Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05 20:25:22 -05:00
Andrew Boie
123c33a836 x86/iamcu: improve _execute_handler() readability, small optimization
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.

If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used

Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:22 -05:00
Tomasz Bursztyka
6021c64844 spi: dw: Add an initialization priority Kconfig option
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.

Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:25:22 -05:00
Tomasz Bursztyka
9de5705bb2 quark_se_ss: Provide all the informations for GPIOs
Enable both controllers by default if GPIO is enabled, providing all the
necessary information.

Change-Id: I5aab00324b10492eefb67e9595da491775cbd95d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:25:21 -05:00
Tomasz Bursztyka
7602d34949 gpio: dw: Fixing how interrupt unmasking is done for Quark SE SS
There is no such thing as "IA" in Quark SE SS as it is an ARC core. Plus
for this very specific feature it does not require the ARC aux regs
instruction to read/write in the given mask address.
And fixing also the CONFIG_ option to check.

Change-Id: I1f63348ec85f6e006795f7641c912a30fc003709
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:25:21 -05:00
Tomasz Bursztyka
f13fb0f71a quark_se: gpio: Add the Always ON GPIO support in Kconfig
Quarks SE owns a GPIO controller which is always on (so not clock-gated)
thus providing it base address, the pins it handles etc...

Change-Id: Ifceb7cb74e763a91130d615ba19756ddcbe97a23
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:25:21 -05:00
Tomasz Bursztyka
bf20dc9cec gpio: dw: Refactor how general interrupt unmasking is proceeded
This is valid only for Quark SE and Quark SE SS, where it requires to
unmask the interrupt for each specific controller. Thus making the
function generic, using the parameter as the specific mask base address.

Change-Id: Iea0a412b8d94a1ab5e1f3e339eaf632eacee5797
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:25:21 -05:00
Andrew Boie
2a1ae3f436 ARM: ARC: put sw_isr_table in ROM by default
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.

At some point this config option broke, probably when static
interrupts were introduced into the system.

To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.

Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Andrew Boie
efc8ed379f quark_se: increase IPM buffer size and make it configurable
The original value of 128 was selected more or less randomly, and
isn't sufficiently large enough for QA needs.

Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Daniel Leung
21c3118655 serial: adds UART driver for SAM3X8E
This adds driver for the UART controller on Atmel SAM3X8E.
This UART controller only has two wires for RX and TX, and
does not have flow control (e.g. CTS, RTS) or FIFO.

Currently, the driver does not support any interrupt driven
operations.

Change-Id: I63720bccfb70a89888353b8ee3dfc4b80793dc01
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:21 -05:00
Daniel Leung
945ebd74be arch/arm: adds initial support for Atmel SAM3X8E processor
This adds initial support for Atmel SAM3X8E processor, which is
based on ARM Cortex-M3. The SAM3X8E is being used on Arduino Due.

Change-Id: I199efcf29629f9ebacad474e5edc91bc3757f613
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:21 -05:00
Daniel Leung
e55bf6cb0c arch/arm: define flash/SRAM base addresses per SoC
This removes the default flash and SRAM base addresses from the ARM core
Kconfig file. Each individual SoC/processors Kconfig has to define them.
This is in preparation to support Atmel SAM3 family processors as they
have different base addresses.

Change-Id: I97ea9b43386d1e286ee692f583c97cfbb5399b0f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:21 -05:00
Andrew Boie
1f63ec7264 Revert "Move compiler optimization to the SoC"
This reverts commit 778d5b11c5327be4b40c7745e9beaecfd6327e13.

This patch has been identified as breaking the build when trying
to manually build non-x86 applications.

Change-Id: I1857745049dfef7193de58737108314b7aae01c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Andrew Boie
009a19f164 x86: remove option to force IDT in RAM
This option misunderstands how XIP works. The IDT is ALWAYS in ROM,
the question is whether crt0 will copy it into RAM or not. You can't
save ROM space in this way.

Change-Id: I58025e3d71ead35730d0a5026213299b4fcb5eb9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:21 -05:00
Johan Hedberg
390a0784ae quark_se: Kconfig: Remove unused NBLE defines
These are not (yet) used anywhere and generate unnecessary warnings.
Just remove them.

Change-Id: Ibae472c4a639466c221cdc354232780db04e963e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-02-05 20:25:21 -05:00
Daniel Leung
4b2a576c80 i2c/i2c_quark_se_ss: convert to using static IRQ API
This converts the i2c_quark_se_ss to use the static IRQ API.

Note that, even with separate config functions for each instance of
the driver, it is still saving both RAM and ROM space.

Change-Id: Ieb555ff281b384d87d8e69f6914878bbee0e2ee9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:20 -05:00
Andrei Emeltchenko
0715bf057b quark_se: Add default configuration for Nordic BLE iface
Define configuration for Nordic chip connected to UART0.

Change-Id: Ia6007def747932e5f9fbd57f1ea8005892a2f793
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:25:19 -05:00
Andrew Boie
af11f2aa4a x86: iamcu: fix implementation of disable_interrupts()
Change-Id: I3fe6ab5543f7e10113f9d5eb0fa81217135d5b74
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:17 -05:00
Anas Nashif
b43af743b7 Move compiler optimization to the SoC
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.

For IAMCU platforms, use the right architecture and tuning.

-march=lakemont -mtune=lakemont -miamcu -msoft-float

Change-Id: I0f77cffe7a139f8b2620935094437d0dfd160dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:17 -05:00
Anas Nashif
fad531027b kbuild: move SoC Makefile content to Kbuild file
The Kbuild system first looks for a Kbuild file, then it looks for
a make file.
Use the Kbuild for object building and leave the Makefile for definding
build options and compiler flags and other SoC related defines.

Change-Id: I0be59bb5ae02a29108a188efbd6f14dcdb7de4ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:17 -05:00
Andrew Boie
d9cfbd5a61 interrupts: new static IRQ API
The interrupt API has been redesigned:

- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
  It will be used in situations where the new static irq_connect()
  won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
  exactly the same way as its dynamic counterpart. The old static irq
  macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
  generated inline with irq_connect()

ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.

Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:17 -05:00
Andre Guedes
565cb2b020 quark_se: Fix I2C-related options selection
Currently, if we disable I2C_DW through 'menuconfig', I2C_DW_0* and
I2C_DW_1* options are not disabled even if they depend on I2C_DW
option. This makes the menuconfig confusing and we end up with the
wrong config set in .config file:

...
CONFIG_I2C_DW is not set
CONFIG_I2C_DW_0=y
...
CONFIG_I2C_DW_1=y
...

This patch fixes this issue by surrounding the I2C_DW_0* and I2C_DW_1*
options with 'if I2C_DW'.

Change-Id: I7e949b066425bca2533f8b84b9ea7b1915369ff0
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-05 20:25:17 -05:00
Andrew Boie
89ec552be9 x86: iamcu: fix exception NANO_ESF parameter
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.

_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.

The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.

Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:16 -05:00
Anas Nashif
2c74c45be0 quark_d2000: toggle I2C0 when I2C is enabled
Change-Id: I79340a22932cf73b504b8fac8dd65dccb6c10009
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:16 -05:00
Anas Nashif
3280b700d7 quark_se_ss: toggle I2C0 when I2C is enabled
Change-Id: I3e8ff764dd51a1eb59a864b9ce58047977ebd68e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:16 -05:00
Anas Nashif
57e444ffa8 i2c: use a common name from i2c devices
Instead of relying on the Kconfig variables use a common scheme for
naming i2c devices and use it directly in application.

Change-Id: I745af68d7c1767cc8a24f9655fa45fa33f6baf93
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:16 -05:00
Andrew Boie
7cb5276158 x86: remove NANO_SOFT_IRQ from zephyr
This was never implemented on ARC/ARM and has been superseded
by irq_offload().

Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.

Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:16 -05:00
Andre Guedes
7b0076a777 rtc: Introduce QMSI RTC device driver
This patch introduces the 'QMSI RTC device driver' which is simply a shim
driver based on RTC driver provided by QMSI BSP.

Some config options are independent of the driver implementation used,
so use a consistent name for them. In this case RTC Interrupt number and
Priority use the same config options for both the QMSI and DesignWare
drivers.

In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_RTC=y
CONFIG_RTC_QMSI=y

Change-Id: I48292406e5472e5786f3b9abbeb71016a273bfec
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
2016-02-05 20:25:16 -05:00
Daniel Leung
db2d48b66f arc: add atomic operations for ARC EM family processors
The ARC EM family processors do not support native atomic assembly
instructions (LLOCK and SCOND). Therefore, the assembly version
of atomic functions cannot be used. This adds pure C version of
these atomic functions.

Change-Id: Ic64dd31b0367b6dcf3a46f41c0c7ac2c2ce5eb8d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:16 -05:00
Andrew Boie
59a6d3870d x86: fix description for CONFIG_NUM_DYNAMIC_EXC_NOERR_STUBS
Change-Id: I7a73aa261297ed986790973fe65e4e82e5576416
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:15 -05:00
Andrew Boie
4733187f1b x86: put the IDT in ROM if possible
If we are not doing any dynamic interrupts or exceptions, we
can put the IDT in ROM and save a considerable amount of RAM,
up to 2K if the IDT is the default size of 256 entries.

The _interrupt_vectors_allocated table can also be put in ROM
if we're not using any dynamic interrupts.

We introduce a new Kconfig option to force the IDT to be in RAM
for situations where no dynamic IRQs are used, but ROM footprint
needs to be conserved.

Change-Id: I38c9f1a8837b4db9f3dea1caa008374a26cbbf1d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:15 -05:00
Anas Nashif
afffff3a32 kconfig: ram size/start are set in platform Kconfig
The values are set in the board or SoC.

Change-Id: I03b358ba1e82c39a1f65ce80a3fb9c181b671109
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:15 -05:00
Anas Nashif
d50b6a7f5c ia32_pci: remove obsolete soc/platform
Change-Id: I7a6a7ef2339061630d7c6dd693b1c03a95573352
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:15 -05:00
Anas Nashif
32c48d1b2d arc: remove obsolete generic_arc
Change-Id: Ifa1506cd5c8ff6876a8b945507c7d6caf2f3bbc2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:15 -05:00
Anas Nashif
030c004fd3 enable iamcu on relevant platforms
This enables building with the iamcu variant of the x86 compiler
and enabled using the IAMCU ABIs.

Change-Id: Idf71251898e250b8df73c065462c93c289879fe2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:15 -05:00
Daniel Leung
05ba788070 quark_d2000_crb: make I2C controller work
There are a few bits missing on enabling I2C controller on
quark_d2000_crb. This adds the missing bits.

Change-Id: I05bbe8367a9e69962db573d496f1f9f0167ba597
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:15 -05:00
Andre Guedes
1622e4f4b5 kbuild: Move CONFIG_STACK_CANARIES check
This patch moves the CONFIG_STACK_CANARIES check from architecture's
Makefile to the root Makefile since this option is kernel-related,
not architecture-related. This way we avoid replicating the same
CONFIG_STACK_CANARIES check in several Makefiles.

This patch also removes some blank lines from the Makefiles it touches.

Change-Id: I458f92fa6799526c608369d1e56579936bcb196e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2016-02-05 20:25:15 -05:00
Peter Mitsis
5c01c09f4d nano_stack: Simplify nano_xxx_stack_pop() API family
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().

This obsoletes the following APIs:
	nano_fiber_stack_pop_wait()
	nano_task_stack_pop_wait()
	nano_stack_pop_wait()

Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
	TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.

Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:14 -05:00
Peter Mitsis
f0b55aa624 nano_lifo: Simplify nano_xxx_lifo_get() API family
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().

This obsoletes the following APIs:
	nano_fiber_lifo_get_wait()
	nano_fiber_lifo_get_wait_timeout()
	nano_task_lifo_get_wait()
	nano_task_lifo_get_wait_timeout()
	nano_lifo_get_wait()
	nano_lifo_get_wait_timeout()

Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:14 -05:00
Peter Mitsis
54b782a88b nano_sema: Simplify nano_xxx_sem_take() API family
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().

This obsoletes the following APIs:
	nano_fiber_sem_take_wait()
	nano_fiber_sem_take_wait_timeout()
	nano_task_sem_take_wait()
	nano_task_sem_take_wait_timeout()
	nano_sem_take_wait()
	nano_sem_take_wait_timeout()

Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:14 -05:00
Peter Mitsis
cd6db374de nano_fifo: Simplify nano_xxx_fifo_get() API family
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().

This obsoletes the following APIs:
	nano_fiber_fifo_get_wait()
	nano_fiber_fifo_get_wait_timeout()
	nano_task_fifo_get_wait()
	nano_task_fifo_get_wait_timeout()
	nano_fifo_get_wait()
	nano_fifo_get_wait_timeout()

Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:14 -05:00
Daniel Leung
b9c70ce76a uart/ns16550: support divisor latch fraction (DLF)
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.

Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:14 -05:00
Benjamin Walsh
0ad859aaf3 arm/arc: fix typos
Change-Id: I0f1c8ccab38719e095547254fdd27e85125f01dc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:25:14 -05:00
Andrew Boie
4f48ac1c20 arc: soc: fix comment for NUM_IRQS
The semantics of this value is that it allows for the use of IRQ lines
0 through CONFIG_NUM_IRQS - 1.

Change-Id: I0287da931b06253065f4fba076e9a949dcb3cf53
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Andrew Boie
c97150b9ed ARC: correctly generate the SW IRQ table
Too many entries were being created in this table. It needs to
create indexes starting from 16 to CONFIG_NUM_IRQS - 1, since IRQS 0-15
are reserved for CPU exceptions and are not handled through this
mechanism.

generic_arc was still using the old C-based table which is
incompatible with the static IRQ implementation. An attempt was made
to move the SW IRQ table to arch/arc/core, but linker issues were
encountered and this will be done in another patch.

With CONFIG_NUM_IRQS set to 68 on Quark SE, inspection of binary
with objdump -x reveals that we are generating table entries:

00000000 g     O .isr_irq16	00000000 _sw_isr_table
00000000  w    O .gnu.linkonce.isr_irq16	00000000 _isr_irq16
00000000  w    O .gnu.linkonce.isr_irq17	00000000 _isr_irq17
00000000  w    O .gnu.linkonce.isr_irq18	00000000 _isr_irq18
...
00000000  w    O .gnu.linkonce.isr_irq67	00000000 _isr_irq67

Which is exactly what we need.

Change-Id: I8ca1682128ae67e2a24642791b7ce31ebca759bf
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Benjamin Walsh
7e5dd561ca arc: select NANOKERNEL_TICKLESS_IDLE_SUPPORTED
The ARC is an architecture that supports tickless idle in
nanokernel-only systems, and it thus must signal this to the build
system.

Change-Id: I96b0a4e8f78b2ea67d2f1b3384e94a32d8eb80e8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:13 -05:00
Benjamin Walsh
1831900cd3 arc: add nanokernel tickless idle support
Modified interrupt handling and idle code to enter and exit tickless
idle mode.

Change-Id: I3461ab6dba30003a4317027fc50a3ba07e830015
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:13 -05:00
Andrew Boie
41bebcd8e0 arc: correctly size the IRQ vector table
CONFIG_NUM_IRQS expresses the total number of available interrupt
lines in the system, and is used to generate a vector table.
On ARC, the vector table is assembled from two parts, _VectorTable
for the first 16 entries (reserved for CPU exceptions), and
_IrqVectorTable for the remainder. The code that creates _IrqVectorTable
was not taking this into consideration and was 16 entries too big.

Change-Id: I676c8534274de8782178f3773bc53a817b89481f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Andrew Boie
377f616b3c arc: fix alignment of IRQ vector table
On ARC the IRQ and exception vectors are just one big array of
function pointers placed at the very beginning of the binary in ROM.
Vectors 0-15 are for CPU exceptions, 16-255 for interrupts.

In Zephyr these have been logically split into an execption table
followed immediately by the IRQ table, specified in the ARC linker.cmd.
However, the exception vector table defined in Zephyr had only 14
entries so the IRQ table was misaligned by 8 bytes. This went undetected
for some time as in the default configuration every entry in the IRQ
table pointed to the common demux function _isr_enter().

This patch correctly ensures that the IRQ table begins at address
0x40000040 instead of 0x40000038 like it had been.

Change-Id: I3b548df0dcabeb9d986ecd6a41e593bd02e3bd73
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Andrew Boie
d0ab1a816e arc: arm: don't use recursion to create _sw_isr_table
Causes problems for large values of CONFIG_NUM_IRQS.
Some inconsistencies have been noted in how CONFIG_NUM_IRQS is
used on these platforms, with bugs filed. This patch preserves
existing behavior and has been shown to generate the same number
of table entries for both arches using objdump.

Change-Id: I1d3ac5466978acb56e88a6dc3cbe7cc09431e94d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:13 -05:00
Anas Nashif
3218f53fe0 arc: remove defaults for NUM_IRQS let SoC set it
Let the SoC decide the number of the IRQs. Fixes a bug where
Quark SE gets the default instead of the declared value in the SoC
Kconfig.

Change-Id: I978c923fbe2a0737ace27ec951bc3a46e8976584
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:13 -05:00
Anas Nashif
8c31ff783a arc: fixed missed rename of _IrqVectorTable
_IrqVectorTable was renamed to _irq_vector_table

Change-Id: I1488bebc7d8174c08f3ce2dc8bcace6ef567aad6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:13 -05:00
Anas Nashif
d067cdbfdc frdm-k64f: set frequency for SoC
The default for this SoC is 120Mhz.

Change-Id: Ic6ec9eb9181256d103f9ebaed2e96a19d1c46b4f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:12 -05:00
Anas Nashif
2d1465cb4d cortex_m: do not set default flash/sram size
This should be set by the boards.

Change-Id: Ife30fff71cebc2fb7275e039557252cfa00cc965
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:12 -05:00
Juan Manuel Cruz
609d1f72a2 gpio: adds interruption masking for quark se ss
The current gpio_dw_initialize implementation masks the interruptions in the line
dw_write(base_addr, INTMASK, ~(0)) to assign api functions and initialize
interrupt vectors and handlers safely. Immediately after this, the driver expects
that gpio_dw_unmask_int(port) unmasks the interrupts. Without this patch that
implementation is empty for the quark se ss board.

Change-Id: Iac84c8807fcadad8c256c3fcaa4ff624b6337bf3
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:25:12 -05:00
Anas Nashif
c6c6651a4c generic_arc: choice options need a prompt
Warning comes during compilation about missing prompt, this sets
the prompt for this SoC.

Change-Id: If8b422d6a870eb99c219ab872924875eb04fba0c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:12 -05:00
Daniel Leung
7ba9011cac x86/quark_se: Add default config options for PWM
Add default config options for DesignWare PWM driver.

Change-Id: I0760f2e367c77ddc2a20c04867acf3429006dc53
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
10bb38c186 Use SoC instead of platform.
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.

Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
f5f9b71b12 Introduce the Atom SoC
This is a generic Atom configuration that can be inherited by boards
with Atom SoC like the minnowboard.

Change-Id: I06ab999062be7811d14755fd34440dee8f8b81ed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
2eb29347f0 remove qemu_x86 platform and use generic IA32
No need for the same SoC configuration with different names. Use IA32
as the "SoC" for qemu_x86 "boards".

Change-Id: Iee00538701c5ece14d0c3df637b0aaa54790f0e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
31662ea101 remove HPET as default for x86
Using LOAPIC Timer as default since it is the default for most target
X86 systems.

Change-Id: I71c9b307839ebcf46fb28e1b709089de600af83f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
7ed15d6bb7 Add TI platform as LM3S6965 instead of Qemu
Previous it was renamed in favor of Qemu, now that we have board support
we move this to the original name and derive a qemu board out of the
platform.

Change-Id: Ia8769b27defa0a39503ecf2e6ec7fc6304b6ff49
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
c092265792 move pinmux code to boards and split it up
We had one pinmux per platform with support for multiple boards.
This moves pinmuxing to boards as first step. Common functions that
are exposed by the API need to be moved to driver while keeping the
muxing configuration with the boards.

Change-Id: I2b4fabf663db98d644abcb5d51ba83adc6f74541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
05bc26ed37 cleanup pinmux code and make code for boards consistent
Also fix some checkpatch issues

Change-Id: I27965b284e456109d86658d3629c995d488a4054
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
9ee7c3a585 galileo: move galileo related files to board
The Galileo pinmux configuration and reboot code belong into
the board and not the SoC.

Change-Id: If862178569438a8901902088bd085275416c25ef
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
013e6167a8 build: switch to board based configurations
Define boards based on platforms/SoCs and define them under boards/.
Also unify the naming of all platform, SoC and board files and use
platform.h for platforms and board.h for boards.

Change-Id: Icfeb96479ab5800aca98c80a79bdc3cecd645314
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
220c54818c globally include headers for boards and platforms
Change-Id: I1f259cccc73dfb3d35019d6ebf3d3bdc6aec2b23
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
aae72278dd galileo: Split board configuration from SoC
Change-Id: I1cdbe563521d004e4677b3bacb5407a07edba655
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:11 -05:00
Anas Nashif
b04958a006 platforms: introduce Quark X1000 SoC
The Galileo board is based on the X1000 SoC, so move galileo to
boards and create this SoC instead, inheriting all SoC related code
and configuration items.

Change-Id: I9b39f1b44644775ee48acae284b82bae7876fffb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
90102a97d2 curie-101 : pinmux : mapping in the SPI1
According to the schematic, SPI1_M_ should be properly mapped out
on the pinmux.  This should enable the SPI1_M functionality on the
Arduino / Genuino 101 board now.

Change-Id: Ided0147e7c2d835aa58fdc5860e7ca7f55d9e566
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
34d3d9e971 pinmux : quark_se / quark_d2000 : reducing RAM and ROM
Updating the pinmux to use a local static table for each pin select
option.  Instead moving to a static series of function calls that
move the data from the RAM section to the ROM section.

This impacts only the Quark D2000 and the Quark SE chips.  It does
not show any impact to the basic_minuteia tests.

All said we see small changes that amount to some values like:

test                        platform        ram_%_change    rom_%_change
========================    ============    ============    ============
microkernel:footprint-max   quark_se-x86    -0.01           0.0
microkernel:footprint-reg   quark_se-x86    -0.02           -0.01
microkernel:footprint-min   quark_se-x86    -0.07           -0.02
nanokernel:footprint-max    quark_se-x86    -0.02           -0.01
nanokernel:footprint-max    quark_d2000     -0.01           -0.01
nanokernel:footprint-reg    quark_se-x86    -0.03           -0.01
nanokernel:footprint-reg    quark_d2000     -0.02           -0.02
nanokernel:footprint-min    quark_se-x86    0.04            0.01
nanokernel:footprint-min    quark_d2000     -0.07           -0.04

Change-Id: Ib69403eced60a8c784887dca9dd1954ce73a3e70
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
933d231cb4 quark: Add compile fences to the quark platforms
Currently the Quark SE and Quark D2000 platform are only included
through the use of a compile fence one level higher in the Makefile.
Adding in a secondary compile fence to ensure if that check ever
changes, we won't be in trouble.

Change-Id: I5e39faffb4289f80901c0264a50a3e770db3388a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
71a9af15be pinmux: Quark_D2000 : adding in pinmux support
Initial import of the pinmux configuration for the Quark_D2000 series
boards.  Some minor tweaking of default values may be needed depending
upon expected usage scenarios.

Change-Id: I3b22219546a6534c7c695d0917a35f6f46b03cf1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
f6694ed31f pinmux : Quark_SE : add pullup, input enable regs
Adding support for the pinmux pins to set the pullup and input enable
registers.  On the Arduino_101 board some pullup pins specifically can
be used to cause a reset for the Arduino sketch being run.  Its use on
other pins is currently being investigated.

Change-Id: Id3293a4da84ea5bf553bf62ccb12782cb88503a5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
14b5d5c79d quark_se : pinmux : fixing the naming convention
Naming convention should follow the IP_noun_verb concept.  In this case,
renaming several functions from (for example) pinmux_set_pin to
pinmux_pin_set, while also correctly naming the function to their
specific tasks.

This is being done to make way for the ability to change the input
value, pullup value, and the slew as well.

Change-Id: Iec6f1723a48f80b66f3cea44df9bb6925972f6af
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:25:10 -05:00
Dan Kalowsky
e46d5c6229 pinmux: adding pullup and input enable functions
Extending the public interface of the pinmux to allow the end user
to set a pin as an input/output and to pull up the value on
a specified pin.

Change-Id: Ie0a3b6432dd8c7d7a02f32e3d22049bdd99f1410
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Anas Nashif
fdb1daf786 kconfig: add board configurations
First step for adding the new board layer. Create configurations for the
various boards we support on x86 under boards with the new Kconfig variables
defining them.

The board selection is optional, that means you will be able to run

 make menuconfig

and create your own .config and select any SoC.

Change-Id: If08e88e9675d13f0f0501ef6750b9424b15f5dc8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Anas Nashif
2d762243fd kconfig: add BOARD Kconfig variable for defining boards
This variable (CONFIG_BOARD) will store the textual form of the
platform name and will be used for locating files related to the
board in the source tree.

Change-Id: I3c8a05ed428451a6785799a5492f0dd14682f208
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:10 -05:00
Anas Nashif
33ce2c7011 quark_se: quark_d2000: do not set native drivers as default
Allow usage of alternative drivers and do not hardcode drivers
to zephyr own implementation.

Change-Id: Ieb55b5dc88b3643f276b7c48facef7f1c1c42fa7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:06 -05:00
Anas Nashif
8704792c45 grove_lcd: this display is not a feature of the board
The LCD display is an add-on, not a feature of the platform or the
board.
Set the defaults and remove the definition from Galileo Kconfig.

Change-Id: Ic319cd765d2dc1fe08cc65615680821fe9bc6a83
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:06 -05:00
Daniel Leung
cbd7dc65c4 quark_se_ss: enable UART
On Arduino 101, the sensor subsystem also has access to the two UARTs
on board. So this adds the necessary code to enable them to be used.
However, one needs to make sure only one core has access to one UART
at the same time.

Change-Id: I9f6c203916164d1b48559a9752fb1e4d879d7fa4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:06 -05:00
Daniel Leung
5aab5ccbad arc/quark_se_ss: need some magic to enable GPIO interrupts
1. Need to unmask interrupts for the sensor subsystem.
2. The GPIO controllers need their clock enabled before they can
   start sending out interrupts.
3. Setting up ISR on ARC requires usage of irq_connect().

Change-Id: I633b07292f11e5c5e768fc51fabb70769d407609
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:06 -05:00
Daniel Leung
ceb1869bcc arc/quark_se_ss: update GPIO0/GPIO1 interrupt number
The interrupt number for GPIO0/GPIO1 are 20 and 21 respectively.
The old value of 8 refers to the interrupts line on the x86 side
of GPIO controller.

Change-Id: I2e9e061d3506e27cb7b14e0431c3b6201a50aad4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:06 -05:00
David Antler
a99b90e4da Fixed Galileo UART0_RXD muxing bug
The pin mux for Galileo Gen2 isn't set properly to enable UART0_RXD input from
the Arduino headers. EXP1's pin0 OE_N needs to be set HIGH to make the IO0
buffer an Input.

Change-Id: I0167f11ff5ee87bd5afe17300807b1aa4ed17abf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: David Antler <david.a.antler@intel.com>
2016-02-05 20:25:06 -05:00
Andrew Boie
689ec02211 x86: mvic: fix IDT reload
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.

To be extra safe, disable interrupts while we modify the table
and subsequently reload it.

Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:06 -05:00
Daniel Leung
8a3273aeb6 arm/fsl_frdm_k64f: serial/uart_k20: rework UART clock gating
The code to poke the system integration module to disable clock gating
for UARTs only works for UART0-3 since all the bits are in the same
register. However, clocks for UART4 and UART5 are controlled by
another register. This means that we have been writing to the wrong
bit for enabling UART4.

This patch fixes this issue, and moves the clock gating clock into
board initialization. The incorrect code has also been removed to
prevent accidental mis-use. The dev_data struct is no longer needed
for uart_k20, so that is removed as well.

Change-Id: I67845a417e43647bf0ffcbdbda34ce68fa887713
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:06 -05:00
Daniel Leung
1487f4b6e2 arm/fsl_frdm_k64f: hardware initialization has to be done first
Hardware initialization for fsl_frdm_k64f has to be done at the very
beginning at boot, before anything else. So change the init priority
for hardware initialization to 0. This makes sure the hardware is
initialized. Or else any memory/register access will hang
the board.

Change-Id: Idc1c9449bb7cd1ec7b8d8f44004ea76cc7c09a18
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:06 -05:00
Dirk Brandewie
d8a1c8ef17 x86: iamcu: Add support for the IAMCU calling convention.
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf


Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:25:06 -05:00
Andrew Boie
a664aae335 x86: reduce static IRQ stub size
All of these stubs at the end pop the stack and tell the LOAPIC
that we are at EOI. Put this in common code which falls through to
_IntExit(). Saves 8 bytes per static IRQ stub. There is also small
constant savings in the common code for dynamic IRQs.

Change-Id: If17e9f105928a4251a2cb3fc0d192649c1c4d84b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:05 -05:00
Andrew Boie
88808f1247 quark_se: apic: work around EOI forwarding issue
Quark SE Lakemont core has a hardware bug where the LOAPIC does
not properly notify the IOAPIC to clear the IRR bit for level-
triggered interrupts.

This patch introduces a workaround where the vector ID of the
in-service interrupt is manually written to the IOAPIC_EOI
register, resulting in the bit being cleared.

Unfortunately, in the context where EOI happens it's very difficult
to identify which IRQ line is being serviced, so this is done
unconditionally for all interrupts vectors whether they are registered
in the IOAPIC RTE table or not.

Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:05 -05:00
Daniel Leung
9e9922265e serial: simplify interrupt config options
Instead of having two config options to specify interrupt triggering
conditions, merge them into one option and clarify. This is now
similar to other drivers which have interrupt triggers.

Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:05 -05:00
Daniel Leung
c71dddb2c2 spi: dw: intel: move IOAPIC interrupt trigger flags into driver
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.

Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:05 -05:00
Daniel Leung
8effb4fed3 shared_irq: move IOAPIC interrupt trigger flags into driver
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.

Change-Id: Ie7262b69226ebffa7e1b9e35725fda24b3fe089f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:04 -05:00
Daniel Leung
66b99d9cc1 i2c/dw: move IOAPIC interrupt trigger flags into driver
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.

Change-Id: I2d50457a45fae62ff085f7239712d580243253bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:04 -05:00
Daniel Leung
8cb01064f6 gpio/dw: move IOAPIC interrupt trigger flags into driver
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.

Change-Id: Ia0a069464392714f38037841de52e8d265fa4f49
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
407d9e050b x86: irq_offload: don't use the last vector
The APIC by default uses vector 0xFF for the spurious interrupt
vector as described in the x86 CPU manual volume 3 section 10.9.
Make this its own config option defaulting to 32.

MVIC doesn't have a spurious interrupt vector, and due to the
fixed IRQ-to-vector mapping for this controller, continue
to use the last available entry.

Change-Id: I29bd09df700629dc0d15b30a6ae590b0df1ef890
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
a0e427f8a4 x86: remove loapic_int_vec_trigger()
This was only needed for an older implementation of software interrupts,
now superseded by the irq_offload() API (which doesn't interact with
the interrupt controller at all)

Change-Id: I8aa696d370ae1799872f6d70de69f3cb5b47456a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
3589695508 ipi: rename to ipm
To many people, IPI connotes inter-processor interrupts on SMP
systems. Rename this to IPM, or Inter-Processor Mailboxes.

Change-Id: I032815e23c69a8297c0a43992132441c240fb71e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Anas Nashif
487660def2 quark_se: shared_mem.h is local to the file including it
Change-Id: I7071dbb6e43a04a48aaff7462e5e5dd395c7b137
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:04 -05:00
Anas Nashif
938d8958a5 remove stray defconfig left behind during rebase
This one exists in configs/ now.

Change-Id: I7b75f16a837e58dbfaa2c2e3cf3666a89f4b0e26
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:04 -05:00
Anas Nashif
66233116ff kconfig: define CONFIG_PLATFORM only once
define CONFIG_PLATFORM only once in arch/Kconfig and set it
for every platform.

Change-Id: I8554bb36d2d15c3ee71fa63dfc3a763ebca956ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:04 -05:00
Dirk Brandewie
fa2441534a x86: kernel move excstub.S back to core
excecptions are handled the same for i386_sysV_abi and iamcu calling
conventions ATM since we do not have any exceptions that we can
recover from there is no reason to have seperate implementations.

Change-Id: Ica8b332d7756a91b56f7080ac74771ad25d32753
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:25:04 -05:00
Dirk Brandewie
88ce5bc8f5 kernel: remove CONFIG_INT_LATENCY_BENCHMARK fences from code path
Add null definitions for the interrupt latency measurement API so we
can remove compile fences in C code.

Change-Id: If86eedf79afcb49002108814dd4fb864956eb667
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
a50f923504 x86: fatal: report vector number of spurious interrupts
Change-Id: I79de1a77d2b5f87aa3bd1a7aebd0253dbb069252
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
65c16621a1 kernel_event_logger: fix function defintion
functions defined in header files needs to be 'static inline' to
avoid linker issues if they are used more than once.

Change-Id: I2feb3560bde7cbc9a5c7932eca585be8036f3b25
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:04 -05:00
Andrew Boie
902eb1d5f1 loapic: expose _loapic_isr_vector_get() in header
Other internal functions are shown in this header, no reason to
keep this a secret.

Change-Id: Icb7d36206148c281f1960d1ac10368d9bb3033f1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:03 -05:00
Andrew Boie
7770c3ed9d x86: mvic: re-load IDT if it is modified
According to the datasheet, there is some caching going on as a 
performance optimization and the IDT needs to be re-loaded if any
changes are made at runtime.

Change-Id: I23864e1109907512066a9f8f3a36e3f719b9174b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
77d167d004 ioapic: move common init code into driver
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.

Those empty C files are there because the current Kbuild
requires Makefile to be present at those directories,
(due to arch/x86/Kbuild), which requires building some object
files. So the empty source files are there to produce empty
object files to satisfy this.

Change-Id: I14056347ea14cff227d9e8960192e8673c0019b8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
921ee03094 loapic: move common init code into driver
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.

Change-Id: I1d379068f64855d5d4595838040ec50f97f638a0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
8778152298 i8259: move init code into driver
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.

Change-Id: I1af8b2888779b2b58367feaff9ee1a6d97b4873c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
a6f195937e x86/qemu_x86: remove empty init function
There is no need to do empty initialization.

Change-Id: Ic6a4a26e61901b345ccd638af550ca1352dd7b43
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
4331244352 x86/ia32: remove empty init function
There is no need to do empty initialization.

Change-Id: Ic3067d519486ee0ce31ba5937f9fc2c49401058e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
fe44e29da8 arc/quark_se_ss: remove no longer referenced UART #defines
Change-Id: I9c6da7cc3cb3ff8951cd283d4d7cc877148533f5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
d51f3dfd5d arm/qemu_arm: clean up no longer referenced UART #defines
Change-Id: I1993d94856f07f633422107b9b35f0d3df95ae5c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
03afb32308 arc/generic_arc: clean up no longer referenced UART #defines
Change-Id: I1fd2bc92362097281c549d9c8b5ec10377dbfd64
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
f12df08085 arm/fsl_frdm_k64f: clean up UART defines in board.h
These #defines are no longer needed.

Change-Id: I70be4c3b330faddb0a5edf3eb3098b864b71e8e1
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:25:03 -05:00
Daniel Leung
6354e36be7 aio: dw: fix compilation errors
() Fix compilation errors due to variable ordering.
() Fix the default config for Quark/SE SS as
   the kconfig options were renamed in previous
   patches.

Change-Id: I1004ae332fb857b60ed90df59831e7bd9c490cb8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:58 -05:00
Benjamin Walsh
3181df6db4 kernel: add per-thread errno support
Saves an errno per-thread, retrieved via _get_errno(), instead of
changing the value of a global variable during context switches to avoid
a hit to the context switch performance.

Per-arch asm implementations are provided for maximum performance.

Enabled by default, but can be disabled via the CONFIG_ERRNO option.

Change-Id: I81d57a2e318c94c68eee913ae0d4ca3a3609c7a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:58 -05:00
Daniel Leung
3c9592ec59 quark_se: need some extra love for interrupt driver UARTs
() The SCSS has some additional registers to mask interrupts
   from peripherals. This patch unmasks the interrupts for
   the two UARTs on board, so that interrupts can be delivered.
() The UART interrupts are edge-triggerd, so set the config
   options accordingly.

Change-Id: I39a1edccd830a8a19288982efa2e9d0faaaff8ba
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
04f5cfb889 wdt: dw: Add support for optional clock gating
Clock gating is platform specific and not mandatory. Thus making it
Kconfig based as well as generic.

Change-Id: I4ea10eadb077ac3d57c9337b43b1a9fb14763302
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
61c15ba1e1 rtc: dw: Add support for optional clock gating
Clock gating is platform specific and not mandatory. Thus making in
Kconfig based as well as generic.

Change-Id: I01b7831536efd87cc66a95060fcf1faf4a340073
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
d1d66a6200 rtc: dw: Unmasking interrupt is not generic among platforms
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms

Change-Id: I9c273e2e7e33dd077a54e8f9205fa949a5e3707a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
49a6e0ae37 wdt: dw: Unmasking interrupt is not generic among platforms
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms

Change-Id: Ie0a4912f0dfbd97f2273efed963f7810a985c0bd
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
66f05ce4b3 rtc: dw: Make internal primitives Kconfig based
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.

Change-Id: I1c225c1b68d94b22ca10423b50a78a0ba09a27a5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Tomasz Bursztyka
85b49efe67 watchdog: dw: Make internal primitives Kconfig based
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.

Change-Id: Idcc89e6e9f4acc337fafc7d42f8de3061a5ece04
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:58 -05:00
Anas Nashif
275ca60b08 Fixed file description and applied doxygen style
Removed old style file description and documnetation and apply
doxygen synatx.

Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:58 -05:00
Yonattan Louise
8885d093c4 Add support for profiling sleep events in nanokernel.
This patch remove the dependency of the ADVANCE_POWER_MANAGEMENT
for profiling sleep events that was supported only for microkernel.
Allowing us to also use this feature in nanokernel-only systems.

Change-Id: I1761eb6c4d72f477b419dfca5dc152b0fb69ee27
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:24:58 -05:00
Anas Nashif
036f793544 quark_se: change interrupt values for UART
The values for this platform were wrong.

Change-Id: Iaa24ae05b29b7af26437f0be8fe88e6eab12469d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Anas Nashif
8ff397d005 qemu_x86: remove obsolete UART defines
Those are now defined using Kconfig

Change-Id: Ie3518f8865968902f8400d209d1b6c38dfb7eca7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Anas Nashif
0f0d8d2c2f quark_se: set UART IRQ flags
Set correct interrupt flags which are used with the console
handler.

Change-Id: I6a3a76826cedd0b4116f622701f2cb1161dd8adc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Anas Nashif
e6f5702e5f quark_d2000: set UART IRQ flags
Set correct interrupt flags which are used with the console
handler.

Change-Id: I473a1fca6234ffb8d926457e8ccecfa29d1be6a5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Anas Nashif
40e41a968d quark_d2000: change interrupt values for UART
Set correct interrupt values for this platform.

Change-Id: I97361b4420630e73bb8c8f812c943ee972cb8762
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:57 -05:00
Juan Manuel Cruz
bc1a79c4c3 irq: removes priority parameter from IRQ_CONFIG macro
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.

Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:24:57 -05:00
Andrew Boie
4d7181b762 x86: move intconnect.c
Although it contains functions called from ASM-land, there's no
calling-convention specific code here.

Change-Id: I3d912bdf28e6f3e797e6a2d6b745302b4c884b4a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:57 -05:00
Daniel Leung
ddab92c23a hpet: move content of include/drivers/hpet.h into driver
The content of include/drivers/hpet.h is really private to
the driver and does not need to be exposed in public include
directory. So move the content into driver code.

Change-Id: Ica442e43c480a6b079b8d3c4e75e67adcfd0ba6b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:56 -05:00
Juan Manuel Cruz
b51b3da133 quark se arc: irq static initialization support.
Adds static irq support for the Quark SE platform for the ARC core.

New linker sections and sw isr table initialization is needed to support
static IRQ.

Change-Id: I82af98a189f5a156e7f1018f3ecdbfa73ad3e6ef
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:24:56 -05:00
Juan Manuel Cruz
4613fc8c74 arc: adapt to standard IRQ_CONNECT_STATIC signature.
IRQ_CONNECT_STATIC takes 6 arguments on other
architectures, but the ARC one had only 5.

Change-Id: I257e8db12582ee2d6f93bba63af9aa597197a53d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:24:56 -05:00
Sergio Rodriguez
2e2ad8166e qemu: Creation of QEMU specific platforms
Setting up new platforms to handle emulation, and make them the only
ones able to run on QEMU from the Makefile "qemu" target to avoid
confusion with other platforms. We have now platform qemu_x86 and
platform qemu_cortex_m3, also modification to the sanity checks to have
qemu support only on those platforms

Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Change-Id: I9291918a1d58fea4f37750ada78234628f9a5d98
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
ba6f2d9617 uart: remove uart_devs[]
Since all the necessary bits utilizing UART by index have moved to
use device name instead, the uart_devs[] can finally be removed.

Change-Id: Idbae6b46c0af9eef6c22c59e121e9d6a6b52426a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
5cdd4584fe uart_pipe: use device name instead of index
Use device name to find the UART device for uart_pipe usage,
instead of relying on an arbitrary index.

Change-Id: I36aaa4ed8f0b4905e4e741ca1464947e59f30869
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
1720991b81 bluetooth/uart: use device name instead of index
Use device name to find the UART device for Bluetooth usage,
instead of relying on an arbitrary index.

The default device names being used are derived from the original
board.h for each platform. Some of them point to the same device
as UART console. Since this is a Kconfig option, the default
can be overridden so this is not a serious issue.

Change-Id: Ibe82f3968e72ba60f9c033aa3dfcb2fb3c41dc75
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
08b4fd431b console/uart: use device name instead of index
Use device name to find the UART device for console usage, instead of
relying on an arbitrary index.

Change-Id: Iebe01c9bf392dfee6d8284367f67647f7d47561a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
5faca5067a uart_pipe: let UART driver do the initialization
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.

Change-Id: Id3e46135ab993cb6596b1fb5339ab1664c65ab40
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
3d361603e5 bluetooth/uart: let UART driver do the initialization
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.

Change-Id: Ibeca65b3fe64feb7a203a793c01c525ff5e6afda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
91cea2c9a6 serial/nsim: refactor (again) to conform to driver model
() Rename nsim_uart.c to uart_nsim.c. This is to follow
   the driver naming convention.
() Rename functions nsim_uart_*() to uart_nsim_*(),
   following driver naming convention.
() UART ports initialization is moved into the driver itself.
   All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
   in each platform's board.h anymore.

Change-Id: If015f39a6f6b4fcc65625e6e5f973b4469202f54
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
b541dbdf77 serial/stellaris: refactor (again) to conform to driver model
() Renames stellarisUartDrv.c to uart_stellaris.c. This is to follow
   the driver naming convention.
() Renames functions stellaris_uart_*() to uart_stellaris_*(),
   following driver naming convention.
() Renames CONFIG_STELLARIS_UART* to CONFIG_UART_STELLARIS*
() UART ports initialization is moved into the driver itself.
   All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
   in each platform's board.h anymore.

Change-Id: I0eadc3878d69ff24d1637f8df5220fd2f161d24f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
d77f6efe03 serial/k20: refactor (again) to conform to driver model
() Rename k20UartDrv.c to uart_k20.c. This is to follow the driver
   naming convention.
() Move driver/serial/k20_uart.h to drivers/serial/uart_k20_priv.h
   as this contains definitions private to the driver, and
   should not be exposed in public include directory.
() Rename functions k20_uart_*() to uart_k20_*(), following
   driver naming convention.
() Renames CONFIG_K20_UART_* to CONFIG_UART_K20_*
() UART ports initialization is moved into the driver itself.
   All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
   in each platform's board.h anymore.

Change-Id: If1be1fde083aba6ff68062db2059aef08617a286
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Daniel Leung
728d91d598 serial/ns16550: refactor (again) to conform to driver model
() Renames ns16550.c to uart_ns16550.c. This is to follow
   the driver naming convention.
() Renames functions ns16550_uart_*() to uart_ns16550_*(),
   following driver naming convention.
() UART ports initialization is moved into the driver itself.
   All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
   in each platform's board.h anymore.
() Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_*
() Disable NS16550 for ARC as no port is defined anyway.

Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:56 -05:00
Andrew Boie
d95b958cfa quark_d2000: correctly configure timer interrupt
The IRQ line used for MVIC timer interrupts is 0, not 10.

Change-Id: I076bf9c8902e7384e493945e6689fcbefff59cad
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:56 -05:00
Andrew Boie
2ec374a8df irq_offload: ARC implementation
Uses the "trap_s" exception to simulate entry into IRQ context;
offloaded functions run on the FIRQ stack.

Change-Id: I310ce42b45aca5dabd1d27e486645d23fa0b118f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:55 -05:00
Tomasz Bursztyka
8e4aff1079 gpio: dw: Support optional clock gating
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.

Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
61d7f11f0f gpio: dw: Support host interrupt mask on Quark SE
Change-Id: Ie58e8611a8fe9edec9ebcb123532a97f396098f4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Tomasz Bursztyka
6351d6671d quark_se: Exposing only one gpio controller and fixing his bits
There is no secondary GPIO controller on such SoC. Plus, the unique
controller controls at least 28 pins (if not 32, so I set 32), as
verified on boards.

Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
62ca32d692 kconfig: reorganise kconfig for x86
Group options and remove redundant menus.

Change-Id: I8d5297f850aeada5c5b14cfb7a206ce07493e116
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
029a1defc8 arc: set license on Kconfig file
Change-Id: Ib6a116106e1b9a9783b1dbb30688aaa748b7875c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
2318f02a7a watchdog: rework watchdog timer driver and use sys_io function
Simplify driver by using sys_io functions and implement

 wdt_read_config

Change-Id: I119615f1c391daae43a3b8db30319c51167ae05b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:55 -05:00
Andrew Boie
bba9510319 irq_offload: API to run a function in IRQ context
Software interrupts or system calls aren't really appropriate for
zephyr, but we have an ongoing need in our test code to run a
function with arguments synchronously in interrupt context.

This patch introduces irq_offload() which allows us to do this without
separate initialization or having to manage fake IRQs in the
interrupt controller.

ARM assembly code contributed by Benjamin Walsh
<benjamin.walsh@windriver.com>

ARC is not yet implemented but will be in a subsequent patch.

irq_test_common.h has been removed and all test cases updated to
use the new API.

Change-Id: I9af99ed31b62bc7eb340e32cf65e3d11354d1ec7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:55 -05:00
Benjamin Walsh
d7fc200a2c arc: abstract bulk of linker script
The linker scripts for the quark_se_ss and generic_arc platforms are the
exact same, so extract the contents in an includable file.

Change-Id: I2cb90a6f819b12db77880228e41ff14c9755d59a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:55 -05:00
Benjamin Walsh
5709a5daae arc: remove KENTRY from linker scripts
It's not used anymore.

Change-Id: Ia9e7e85fd76744a4617b20f6e52b09f85b066c83
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:55 -05:00
Anas Nashif
bbe94000e4 quark_se_ss: rename platform and remove arc suffix
This platform if actually a subsystem of the Quark SE SoC and is
not standalone. Use a more descriptive name and remove the architecture
from the platform name.

Change-Id: I16b1ab8dd668441683b07fc4512c219924463441
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Anas Nashif
5115fb57ad quark_se: rename platform and remove x86 suffix
Change-Id: I19ac3a4c6081720736c6fbf16b649ccf6ae60e2f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Dmitriy Korovkin
57f2741e4f init: Implement fine-grained initialization policy
Put initialization priorities as device driver Kconfig
parameter.

Initialization priority value for each platform is defined
in the platform Kconfig file.

Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.

Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Dmitriy Korovkin
fb6de2d486 init: Add protection against incorrect levels or priorities
Initialization level can be one of five predefined.
Init priority is numeric from 1 to 99. If init level or priority
is defined wrong, linker prints out the message and stops.

Change-Id: I165a32ffb668cda983fd48eb2aa7b94998e31a18
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:54 -05:00
Anas Nashif
1e3dca51bb build: set platform name without quotes and reuse everywhere
Avoid having to remove quotes wherever the platform name is used
by exporting the variable only once.

Change-Id: I4cb51901e4ac19d70d0310fe6bbacd157f586661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Anas Nashif
fe29e34369 arc: remove defaults and fixed typo k->K in linker.cmd file
The defauls set in architecture Kconfig are not being overwritten
by the platform, so remove those and rely on platform provided
data.

Change-Id: Ia71d9d14dddce94c29b9ca957b4ed3ae8838d96c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:54 -05:00
Anas Nashif
4927ff8d75 arc: use integer RAM_SIZE globally
Using int for the Kconfig variable to resolve warnings from Kconfig.

Change-Id: If2574753fd5761b59f37a8bccea8c5f6699cb363
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:53 -05:00
Benjamin Walsh
a73ccbd7cb arc/arm: remove unused IRQ-to-exception/vector macros
They a) are unused, b) should not be in board.h, and c) are wrong on
ARC.

Change-Id: Ic40397d9cfcdf314544875f1443618865435d5e7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:53 -05:00
Benjamin Walsh
ba31ab92a3 x86: refactor assembly flags in Makefiles
Add comment regarding the use of GAS when using clang, and remove
duplication of setting -Wa,--divide, which is needed for all toolchains.

Change-Id: Iab7257b038d1f4142c37a6c6c5979ef28f78a655
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:53 -05:00
Benjamin Walsh
4c57acb883 x86: split ABI related files
Move the files that *know* about the calling convention in use by the
compiler. The routines exposed by the files moved to the i386_sysV_abi
directory follow the C calling convention specified by the
i386_sysV_abi which is the default for GCC. The upstream GCC has been
enhanced to support the iamcu_ABI that is optimized for processors
that implement the IA MCU instruction set. This new ABI provides code,
data and stack size improvements on IA MCU based systems.

This change is the first step in adding support for the IA MCU
optimized toolchains to Zephyr OS

Change-Id: I13bffee8007fb3f82aa31389b2c241065e8e315d
Original-work-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:53 -05:00
Anas Nashif
c47769bd56 kconfig: move all defconfig fragments to configs/
When building for a certain platform, we have no idea
what architecture we are building for.

We used to specify the architecture alongside the board or platform
name and this was used to find the defconfig in arch/<arch>/configs.

By putting all board configurations we support in one place we do
not have to specify the architecture, just the configuration name.

Change-Id: Ib7e9f63b9a8051714dc207f583fd26ef620497d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:53 -05:00
Anas Nashif
df73d32147 build: use architecture definition from kconfig
Do not depend on host architecture and use architecture definition
from the defconfig file of the board.

Change-Id: Idb3dd42524f26bd167a34d6eb024d4d9816e9730
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
77ba3c3b8b kconfig: define architecture as a kconfig variable
Do not depend on environment variables and use a kconfig variable
for defining the architecture.

In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.

Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
b2bbf5a7b7 arc: only build configured platform
Use CONFIG_PLATFORM to only build the selected platform. This
makes the makefile with drop-in platforms, does not need to be
changed for any new platforms.

Change-Id: I21f4bd88b04a7e53bc80b9710b1e7668def4e407
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
4ca036074d arc: use kconfig wildcards
Use CONFIG_PLATFORM to only build the selected platform. This
makes the makefile with drop-in platforms, does not need to be
changed for any new platforms.

Change-Id: I8720ba1501b6e1929bfec294f5bb1c7466d65049
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
b533cdc302 arm: remove repeating cflags in Makefiles
Do not repeat the same flags for every added platform. Define
the common flags on the architecture level instead.

Change-Id: I0e501d6a909892dd682b106fb2a5072434a39563
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
3816104619 arm: only build configured platform
Use CONFIG_PLATFORM to only build the selected platform. This
will enable support for drop-in platforms. Makefile will not need
to be changed for every new platforms.

Change-Id: I22778e8242422e487e941143df3e521b33f2b0a8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
c3a7fd2844 arm: use wildcards for kconfig
Move platform related data and definition to the platform
directory and include it using:

arch/<arch>/platforms/*/Kconfig.platform

This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodoules)

Change-Id: I6bff4e48490e33cbaf879fe3c424bf2f6a4887ac
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
cd158f3750 x86: only build configured platform
Do not reference every platform, instead use the platform
name to tell make what to build.

Change-Id: I7498da7cdcdada754466222902f59fe4c6487d89
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
a4266c3baf kconfig: use wildcards for platforms
Move platform related data and definition to the platform
directory and include it using:

arch/<arch>/platforms/*/Kconfig.platform

This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodules and does not need to be part of the zephyr
project)

Change-Id: I5e71f5394c22edb346f7d61d9448b8e1c68e1f9b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka
39621510e2 Kconfig: quark_se-x86: Set proper default config settings
Provide the proper irq for i2c, gpio and spi. And make relevant drivers
getting enabled easily once their domain is selected.

Change-Id: Ib8a428e11b6163a1b370b23baa34ea2fab733565
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka
49ea925727 quark_se-x86: Provide the i2c IRQ flags
Without that, it won't built when enabling support for dw i2c in
quark_se-x86.

Change-Id: Icce26488d870c273516dc9f34555176122bcb9c8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Tomasz Bursztyka
14267b85c9 spi: dw: Fix various building and support issues
- Build the actual driver when relevant
- Provide the IOAPIC stub
- Provide the IRQ flags for IRQ_CONNECT_STATIC
- Set the default IRQ priorities

Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:52 -05:00
Szymon Janc
c0baad2262 Rename simple UART driver to pipe UART
Original name was too generic and confusing. This patch renames
driver to pipe UART and moves it to console drivers folder. Kconfig
destription is also improved.

Change-Id: I716fdbf7d636bbdc03b0fce27a59fd866f473246
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
2016-02-05 20:24:52 -05:00
Anas Nashif
42d94e5dbe x86: Add Quark D2000 platform with nanokernel support
The Intel Quark microcontroller D2000, is a low power, battery-operated,
32-bit microcontroller.  Within its small footprint, the Intel Quark
microcontroller D2000 includes an Intel Quark ultra-low-power core
running at 32 MHz, with 32k integrated flash and 8k OTP SRAM.

Change-Id: I6ba121996edb0b5fbe596bd6ef3d6e3979ff73e9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:49 -05:00
Anas Nashif
00c4d32d42 x86: add Quark D2000 Interrupt Controller (MVIC)
This module is based on the standard Local APIC and IO APIC source modules.

This modules combines these modules into one source module that exports the
same APIs defined by the Local APIC and IO APIC header modules. These
routine have been adapted for the Quark D2000 Interrupt Controller which has
a cutdown implementation of the Local APIC & IO APIC register sets.

Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif
b0b936b51c arc: add Quark SE Sensor Subsystem nanokernel support
Change-Id: I8178076e9f8bf98c3149f3622aa2236070446c62
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif
28af1ee421 Move RAM and NSIM option to architecture level
Change-Id: Ic47e263bebe4bc2fecb233856ddd1f5de85c11d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif
226404c4bf x86: go back to integers for ram/rom size
This cause problems with some configurations using hex.

Change-Id: I680c40d46e1fdf3da714f6412c8dda0e1ebb44f9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif
4a4de7069e x86: add support for the Quark SE platform
Intel Quark SE Microcontroller with an onboard sensor subsystem.

Processor
* Intel Quark SE Processor Core
* Intel Pentium® Processor-based x86 ISA compatible CPU
* 32MHz clock, 32-bit address bus
* 8kB 2-way L1 instruction cache
Memory
* 384kB of on-die NVM +8kB OTP on-die NVM
* 80kB of on-die SRAM

Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif
98beac134e add physical RAM address variable
Keep things consistent across all platforms and make this
configurable and avoid hardcoding in linker.cmd file.

Change-Id: Iddeb5107854139249fda70378e07b83066d8a7a1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:48 -05:00
Daniel Leung
d3d64ca4cf bluetooth/uart: register driver at boot if enabled
The driver should handle the initialization instead of relying on
platform initialization. This is to conform to the driver model.

Change-Id: Idc95d59bce2470b5118e416ee05f07548991a15c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:48 -05:00
Dmitriy Korovkin
470ce8482c Initialize UART irq number statically
When PCI bus is not enumerated, I/O memory and IRQ
numbers need to be statically initialized.

Change-Id: I4efcccd95d8048910f6c900c8daf46cbe3a5fa00
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:48 -05:00
Andrew Boie
f6dd6d5fd8 x86: atomic: don't use '__asm__ goto'
Not supported in LLVM/clang.  As it turns out,
this new implementation is 4 bytes shorter than its
predecessor.

Change-Id: I1f63b7a245dafcfc5a6dadc293875f00d02b997c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:47 -05:00
Anas Nashif
db26a98c93 Fixed various clang build issues
Fix a few spots where building with with clang fails.

Change-Id: I621c7cb8daf119bf89ad512168d70e1c9b67e53f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:47 -05:00
Anas Nashif
1b702154b5 kbuild: add clang support
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.

To build with clang for x86:

make  CC=clang  -C samples/microkernel/apps/hello_world/

You still need the gcc cross environment for various tools.

For now, only x86 was tested.

Change-Id: Ic5aeab4f80d312e1d1312a4a9fc885a43f760270
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:47 -05:00
Dmitriy Korovkin
f1420515a7 irq: Add flags to IRQ_CONNECT_STATIC() macro and irq_connect() function
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.

The change in API means that device drivers and sample
applications need to use the new API.

IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()

Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:44 -05:00
Tomasz Bursztyka
74e29ac373 galileo: Use SCH GPIO driver for it's legacy bridge GPIO controller
Such controller offers 2 blocks (respectivelly Core Well and Resume
Well) on Quark x1000, with 2 and 6 GPIO pins to use.

Change-Id: I50075f0880bef4574e9eeb1c65602082e8da647a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:44 -05:00
Anas Nashif
6ba5c09d23 kconfig: change RAM_SIZE to be in hex
We already had this kconfig defined as hex for arc. Make it
readable and change the variable to hex to comply with what
we had already.

Change-Id: Ib8bc72f27d1b97ba2c886201ec29fb13aa4fa429
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Anas Nashif
c5ad109c7b fsl_frdm_k64f: do not declare kernel type
This is done from the kernel fragments, no need to declare it here.
(micro kernel is the default anyways)

Change-Id: I88511c03f44538cab3e8fbf8292e179e01005b0d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Anas Nashif
a3f8d81614 cortex_m: re-add __start definition for cortex_m
This was removed as part of some Diab cleanup, however it is needed
and without the definition we get the following when building
for the FRDM-K64F  board:

arm-none-eabi-ld: warning: cannot find entry symbol __start; not setting start address

Change-Id: Ie0604a600b6f7a4faa321c58aa63c5617a163107
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:43 -05:00
Andrew Boie
c065ed5d78 x86: reduce footprint of exception debugging
We're smart, we can look up the vector IDs in a book if we
don't already know what they are.

Change-Id: Iaff3986d7c96dea597be4b2a5b13721ab57980fa
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:43 -05:00
Vlad Lungu
3fc0f0f422 fsl_frdm_k64f: Increased NUM_IRQS to 86
Needed for the Ethernet MAC

Change-Id: Iecef5be818c87c34280ea32123f05b8f5974a998
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh
665dd5d331 galileo: disable SPI_PORT_1 by default
Unused, uses IRQ17, which conflicts with UART1.

Change-Id: I5d285ee8a2e7e5d45b38a85a417bd36f0e4bb92e
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Dmitriy Korovkin
ea5ff12110 galileo: Add ADC configuration
Change-Id: I694d2812496220e54e757cb89ce0c529f3bad48f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis
c7a76a226d galileo: Fix SPI speed and configuration values
Change-Id: If15b2931e00d3a5748a56cea673e694389a7e963
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis
c5b10c6006 x86: Display registers on fatal error
Change-Id: Idb05fbb707f2c95173423c928acda2a07e962989
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis
6338c4518c x86: Update NANO_ESF and NANO_ISF structures
As the system always operates in ring 0, neither the SS nor ESP registers
are pushed onto the stack when an exception or an interrupt occurs.
However, as the ESP field is still relevant to debugging fatal errors, a
place has been carved for it in the NANO_ESF.

Change-Id: Ibb2578c69fa6365fd6e9dbf7b51f461063dadc68
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Peter Mitsis
e7018455d8 x86: Remove cr2 field from NANO_ESF structure
As page fault exceptions can not occur in the system as it is currently
designed, there is no need to track the CR2 register as part of the
exception stack frame.

Change-Id: I75d7a74c5d2c6efcc0e9141d2662861bc2052629
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh
b0edae6047 x86/qemu: do not use -no-reboot flag when REBOOT=y
The -no-reboot flag causes QEMU to exit when trying to reboot through
the RST_CNT register.

Change-Id: I01262753587d2fc4e787262a8368ddba39fdeaa1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh
f9127ecf52 reboot: add support for galileo
Implementation of the sys_arch_reboot() call for galileo, using the
RST_CNT register (I/O port 0xcf9).

Change-Id: I00fbf4aaaf746f640674da6880e1d6c5aa230e06
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:43 -05:00
Benjamin Walsh
3ab75623fa x86: add kconfig options for RAM/ROM size
CONFIG_RAM_SIZE
	CONFIG_ROM_SIZE

Available to x86 based platform configurations.

Change-Id: I3dda770a9063e3c717023b1a83761f32caa2c590
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:42 -05:00
Peter Mitsis
3e06e7293f arc-linker scripts: Add _image_[ram|rom]_[start|end] symbols
Adds the following standard symbols to the arc linker scripts:
	_image_rom_start
	_image_rom_end
	_image_ram_start
	_image_ram_end

Change-Id: Ib1dfa1dcb85140193557e72536145e74eb3ebb91
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:42 -05:00
Peter Mitsis
abc1694614 arc-linker scripts: Replace __text_start/end symbols
Standardizes on using symbol names _image_text_start and
_image_text_end instead of __text_start and __text_end.

Change-Id: I160ed6b4f117483fcffdfa04ce10bd6a5151704a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
05d6c92621 x86: cpuhalt: rewrite using inline assembly
Eliminates issues with compilers that have different C calling
conventions.

Change-Id: I9318edd5eea6b6bacdf3da2c28e0e29315d5cdf5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
033ee894b9 x86: use GCC inline asm for MSR read/write
Eliminates issues with compilers that expect different C
calling conventions.

Change-Id: Ic70a15926380671a7b9c058b53400b10b5c870a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
6bf328b6ea x86: use GCC inline assembly for atomic operations
This doesn't make any assumptions on calling conventions or
the structure of the stack, and should thus be portable to
compilers that implement different C calling conventions.

In order for the rewritten functions to take up the same code
size as the pure-asm counterparts, -fomit-frame-pointer has
been specified for each of them, otherwise an extra 4 bytes
is used for every function.

The generated assembly code by these new functions has been
verified in GDB to be the same as the old ones, except a few
trivial things like particular registers used.

Change-Id: I9a896cbfc3e7f4c2497d749140729d28b32f1c9d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
30f01d86e0 x86: remove CONFIG_LOCK_INSTRUCTION_UNSUPPORTED
This was only needed on legacy platforms which are no longer
supported.

Change-Id: I4a3312f3698c4fc8bbf0df4610af7b69a9056f80
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
8a2104e16a x86: remove CONFIG_UNALIGNED_WRITE_UNSUPPORTED
This had bit-rotted to the point where it was breaking the build
and was only needed on legacy platforms that are no longer
supported.

Change-Id: I4fcfc38bacac58761fba475701e0c27d7b8b7a27
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:42 -05:00
Anas Nashif
6de1c20809 core: remove NO_ISRS feature
This option is not building and currently not supported, removing
it because there does not seem to be a use case for it.

Change-Id: Idb8ffedf83f43cffc68a01573c6f2d1a90fc40fb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:42 -05:00
Anas Nashif
14cb8da750 Revert "kbuild: add clang support"
This reverts commit 58fd0778c6dcc6bd3148b5d07615cd7bd777f456.

Change-Id: Ibffe036d2e182652b3c966c10ed405c9386f823c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:42 -05:00
Andrew Boie
b43758d22a x86: remove dynamically generated IRQ and exception code
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.

Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.

CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.

Some other out-of-date verbiage in comments related to supporting
non-APIC removed.

Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.

SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.

All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.

_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.

Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:41 -05:00
Anas Nashif
0d0cb8e661 kbuild: add clang support
Clang support already existed in the Makefiles but was not complete
and some gcc options did not work with clang. Move those to be conditional
on the compiler used to make clang work.

To build with clang for x86:

make  CC=clang  -C samples/microkernel/apps/hello_world/

You still need the gcc cross environment for various tools.

For now, only x86 was tested.

Change-Id: I1a50c3a82d79ff3001beb4366961ca810eeb6006
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:41 -05:00
Yonattan Louise
e378747706 Rename Profiler to Event Logger.
In order to have a name according to the functionality of the feature.
This commit rename any text, function and variable related with the
Profiler name to Event logger.

Change-Id: I4f612cbc7c37965c35a64f06cc3ce5e3249d90e5
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh
334c14e66e x86: CLFLUSH and cache line size detection
Detect the presence of CLFLUSH instruction and cache line size at
runtime. It is still possible to set them manually via kconfig options
if the values are known.

Change-Id: I00bda1de4c5c241826ead6f43b887b99a963cc7b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh
aed578cb03 x86/cache: rename _SysCacheFlush to sys_cache_flush
Change-Id: Idb1bbedea9577856ea6db08683ea4a4ead92e14d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00
Benjamin Walsh
b7875a0bc8 x86: Rename PHYS_ADDR/VIRT_ADDR to paddr_t/vaddr_t
Change-Id: I8e037278f2f1d409360c52276cb4dae87b9ad440
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:41 -05:00
Andrew Boie
8397dc5028 _irq_handler_set: don't require old function as parameter
This was kept around since it used to be necessary for x86, and we
want our APIs to keep partity across arches, but with the x86 IRQ
refactoring this is no longer needed.

Change-Id: Iacd61f4c4d3cc33b4a15bfa083e106ba6d5da942
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:41 -05:00
Dan Kalowsky
7ed1abfdda checkpatch: warning - new_typedefs
Removing many of the typedefs that are only used once to lessen the
checkpatch warning about creating new typedefs.  A handful have been
behind as they would require a more invasive change to the code.  It
has yet to be determined if this is a worthwhile endavour.


Change-Id: Ibeb29e0a1d37e8121218fccf0d986cbebd226e85
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:41 -05:00
Michael LeMay
ef2a2254e6 eth: dw: galileo: Provide pre-set MMIO base address and IRQ
Provide a preconfigured base address for MMIO and a preconfigured IRQ
pin identifier for the first PCI Ethernet MAC in the Intel Quark X1000
SoC.

Change-Id: I1b527df6c3b1b65da9f0233464e54157029f04f5
Signed-off-by: Michael LeMay <michael.lemay@intel.com>
2016-02-05 20:24:38 -05:00
Anas Nashif
2ad03b930d define range for FAULT_DUMP config variable
Only allow valid values to be set for this option.

Change-Id: I11dd7381ddbf6d4d9985255b9b784544074aba63
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:37 -05:00
Jeff Blais
b746ec13bc galileo: Fix pinmux function assignment comments
Change-Id: I099773701448b09bc3fa0607552fadec39e24407
Work-by: Jeff Blais <jeffrey.blais@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Signed-off-by: Jeff Blais <jblais@windriver.com>
2016-02-05 20:24:37 -05:00
Benjamin Walsh
34f53085f3 galileo: add missing configure call for PWM0
If PWM had been configured by some other application after the last
power cycle, it would appear to work fine. However, an application using
PWM loaded right after a power cycle would not work, since the configure
call was missing during boot.

Change-Id: I389ca2122e1a4a7ea6d298efb327438761336d75
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:37 -05:00
Allan Stephens
0a58ade768 x86: Revise appearance of floating point configuration options
Streamlines the prompts and help text for the floating point
configuration options to make them easier to understand. Also
fixes a help text error that said fibers using the floating point
registers needed to provide additional stack space, which is
incorrect.

Change-Id: Ib6fc13460999ec7f737118728a363b4e10d23fcf
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:36 -05:00
Anas Nashif
a5c85bb010 doxygen: various doxygen layout fixes
Change-Id: Ic1d3d3bb6c4ca2b67098331f9fcfb320a2c47402

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:36 -05:00
Dan Kalowsky
ec1772b69f system: fix comment of file name
galileo.c currently calls itself system.c in a comment.  It lies.
ia32.c currently calls itself system.c in a comment. Don't believe it.
ia32_pci.c currently calls itself system.c in a comment.  It lies.

Change-Id: Icdba074ff2e2e478529bc5757c90b5adbc9dcb8a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:36 -05:00
Tomasz Bursztyka
5938cf1a0a pinmux: galileo: Set SPI1_MISO correct settings
GPIO7 and SPI1_MISO share the same muxer and SPI1_MISO is an input pin.

Change-Id: Ib55e03680fadc3f8ce2725fad6761b3551134081
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:36 -05:00
Dan Kalowsky
d89c3b598b checkpatch: warning - space_before_tab
Change-Id: I8d36cdcdd1822cafa7f53f8b8a8788992b0703e3
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:36 -05:00
Dan Kalowsky
2a57d02400 checkpatch: warning - spacing
Change-Id: Ia63d6c9d8d3c1bd9c540a039263cb8507af82b1e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:35 -05:00
Dan Kalowsky
2a63743192 cleanup: removing NOMANUAL
The \NOMANUAL tag is a remnant from days of yore and is no longer
needed or useful.  Cleaning up the code references to this.

Change-Id: I1b8cc9c9560d1dbb711f05fa63fd23386789875c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:35 -05:00
Andrew Boie
090385b666 x86: remove boi handler support, eoi argument
This was only needed for the older 8259A style PICs which are no
longer supported.

Since we now just support APIC, we always just call loapic_eoi which
no longer requires an argument and informs the IOAPIC that the interrupt
is complete if necessary.

Change-Id: I15c9b7b4f03b872656220af32220b62e043bfa6b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:35 -05:00
Tomasz Bursztyka
e560c90c0e galileo: SPI and pinmux init level need to be reversed
SPI port 1 needs the pinmuxer to be initialized first. Or then, all
modifications required from the CS GPIO logic won't apply.

Change-Id: Ibe4b2d4096065a9add23373075090d5e8a014650
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:35 -05:00
Tomasz Bursztyka
95116abb0b spi: galileo: SPI port 1 uses DW GPIO pin 2 for CS
As for the SPI port 0, SPI port 1 needs a GPIO pin to emulate the CS.

Change-Id: I00911cd25c3fa0ae17a02ee6f43cbea7f4fbcca2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:35 -05:00
Peter Mitsis
0362db8a63 x86: use _IRQ_TO_INTERRUPT_VECTOR() with ioapic_irq_set()
ioapic_irq_set() needs a vector number: all calls to it now use the
_IRQ_TO_INTERRUPT_VECTOR() macro as expected.

The previous change by which interrupt priorities are now honoured
correctly when connecting ISRs to IRQs statically also changed the way
the interrupt vectors are assigned.

Instead of computing them like this:

    interrupt vector ID = IRQ + INT_VEC_IRQ0

They are now determined by a macro:

    interrupt vector ID = _IRQ_TO_INTERRUPT_VECTOR(irq)

Change-Id: Icc4576ac9bc6891c8662bcc17a543333eb8745e0
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:35 -05:00
Anas Nashif
280452061d doxygen: use @a on parameters instead of < >
Change-Id: I2933df165a3c1f95b1d02f57f38bc7587008ce5d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:35 -05:00
Anas Nashif
a5c3644bca arc: replaced wrong config variable
Change-Id: Ib72e35105e575dc5744fe59fd27265e6ed203daf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:35 -05:00
Peter Mitsis
47888a31db Update static IDT generation to use IRQ priority
Updates the 'gen_idt' tool to generate a mapping of IRQ numbers to
interrupt vector IDs, thereby allowing the IRQ priority to be utilized
when statically connecting an interrupt.

Change-Id: I2e54ceb65145682820dfbd8ca1ee6ec68d71ce1a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:34 -05:00
Peter Mitsis
5084b6da56 Fix various default IRQ priorities
Changes the default IRQ priority level from 0 to 2 for the following
kernel configuration options as priorities 0 and 1 are reserved for the
first 32 IDT entries.

	SHARED_IRQ_0_PRI
	SHARED_IRQ_1_PRI
	I2C_DW_0_INT_PRIORITY
	GPIO_DW_0_PRI
	GPIO_DW_1_PRI
	SPI_INTEL_PORT_0_PRI
	SPI_INTEL_PORT_1_PRI

Change-Id: I0fc821c68156eb1e1fe776b2bd4ff5890bba40e8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:34 -05:00
Peter Mitsis
80c18a1d3d Remove Kconfig option NUM_GDT_SPARE_ENTRIES
The Kconfig option NUM_GDT_SPARE_ENTRIES is no longer relevant.

Change-Id: Ie41ed3bef50bd4198c4cee45e160f008c53bfed4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:34 -05:00
Peter Mitsis
4ebdf7f84b Rename NO_NESTED_INTERRUPTS to NESTED_INTERRUPTS
Renames the Kconfig option NO_NESTED_INTERRUPTS to NESTED_INTERRUPTS
as it is typically easier to follow positive logic than it is to
follow negative logic.

Change-Id: I68f9220621545a72254ba561aa3cb488e59e402a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:34 -05:00
Andrei Emeltchenko
3cc5b7b15e ia32: Remove unneeded define and mark parameter unused
CONSOLE_HANDLER depends on UART_CONSOLE so this define is not needed.
Also mark parameter unused.

Change-Id: I58b52955a22de3fb3216454a1d802eef63c9f845
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:34 -05:00
Andrei Emeltchenko
7c9206e9b0 galileo: Correct init layers for UARTs
Copy initialization sequence from ia32 configuration.

Change-Id: Idd33f2dcd5aeefeddfe50ec8a6b054cad38c0022
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:33 -05:00
Andrei Emeltchenko
9eaa84a40d galileo: Specify IRQ number for UART1
Change-Id: I87a53c0c539777b9d2b18c30e3168fcae36342aa
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:33 -05:00
Andrei Emeltchenko
1e1bb51da2 Bluetooth: Configure Bluetooth for galileo platform
Configure IOAPIC for Bluetooth interrupts connected to UART.

Change-Id: Iad58f52e95c05245d38dd0f4cb10494b53bad8e0
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:33 -05:00
Andrei Emeltchenko
3195016822 Bluetooth: Configure Bluetooth IRQ for ia32 platform
Configure IOAPIC for Bluetooth interrupts connected to UART.

Change-Id: Ia93f71a8e8435c523dd8ee232f9ce4cf9266b978
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:33 -05:00
Andrei Emeltchenko
5713a749af Bluetooth: Configure Bluetooth IRQ for ia32_pci platform
Configure IOAPIC for Bluetooth interrupts connected to UART.

Change-Id: Ib9c208a1d396bb6f51531e970d515e42ff416e6c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
d81d8bcbfa checkpatch: error - spacing
Change-Id: Ie051000e3d3f0f5bdc330d0265010c37acb873bd
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
45eb81f32d checkpatch: warning - static_const_char_array
Change-Id: Iff0d922a7b9ad498820527e71b31701bb06c400e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
890cc2f1ef checkpatch: warning - line_spacing
Change-Id: I2276676142deea21cf8079449ce153f2fb887a8e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
e45956c9a0 checkpatch: warning - leading_space
Change-Id: I34a54230bc4a63c8a4391d03ff530835910c3705
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
e8563c2f97 checkpatch: error - trailing_whitespace
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
9760129627 checkpatch: error - open_brace
Change-Id: Ie655181d5ed11a71cadfa218f396f0b64992ca34
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
da67b29569 checkpatch: warning - block_comment_style
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:33 -05:00
Dan Kalowsky
3a109b1f00 Adding in doxygen comment headers
Moving many of the functions from the old format of inline comments to
the newer doxygen format.

Change-Id: Ib0fe0d8627d7cd90219385a3ab627da8f9637d98
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:33 -05:00
Allan Stephens
027ed5682b x86+arm: Remove symbols needed only by Diab toolchain
These symbols are no longer required.

Change-Id: I99f6afad0ffb116efde1e2ff28252a2e4d8b7fb4
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:32 -05:00
Allan Stephens
7011b1c8da x86: Undo workaround required by Diab toolchain
This workaround is no longer required.

Change-Id: I797237be77b7568fe836df0e82640027d8d4882b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:32 -05:00
Allan Stephens
eff3508f16 x86: Remove cosmetic traces of Diab toolchain
Updates several files to remove mention of Diab toolchain
support, which is no longer supported. These changes do not
affect system operation.

Change-Id: If9de85e595f6685295e565bc94ca17f51d87513f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:32 -05:00
Daniel Leung
fed1cc8833 x86: galileo: pinmux: update get/set functions
This implements the get function for the Galileo pinmux
driver. Also modify the set function so that the get
function would work correctly.

Change-Id: I463b01a903389a9c640bb1354ce92b9c0e37030f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:32 -05:00
Anas Nashif
bcc16634ac spi: move static stubs to driver directory
Change-Id: Idd08e79eec429df00673a10790ec85afbe3183f6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:32 -05:00
Anas Nashif
87fe9387fb shared_irq: move static stubs to driver directory
Change-Id: I55808e5e460486c7f61919eca0aba9e2f4b434e1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:32 -05:00
Anas Nashif
47869287a4 gpio: move static stubs to driver directory
Change-Id: I6077aaeba4d572ddfa9d696014c6aec08abd3d3a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:32 -05:00
Andrei Emeltchenko
e3f542cf2f galileo: Correct typo and mark variable unused
Change-Id: I0a386b293ddff54bbce8035670a282201eb5358b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:32 -05:00
Andrei Emeltchenko
c7b152932d galileo: Remove unneeded defines
If console handler is defined uart console should also be defined.

Change-Id: I3efcc6c837f8f1621340f7f13bf0603d7dc42fb2
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:24:32 -05:00
Tomasz Bursztyka
17e06fb457 uart: Move generic API to root directory of include
Only driver specific public headers should be found in include/drivers.
All generic API are found in include/ directory.

Change-Id: Ic50931987bb9460fd4a3843abc6f5de107faf045
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:32 -05:00
Dirk Brandewie
ad5af93f25 x86: Add context value to loapic_mkstub and ioapic_mkstub macros
Add a context value to the ioapic and loapic mkstub macros to allow
the developer to specify a context value that will be passed on the
stack to the interrupt service routines.

All the invocations for the loapic_mkstub and ioapic_mkstub macros
have been changed to pass in 0 so there is no functional difference
ATM.  This change removes the need for drivers to have trampoline ISR
routines to pass a context vaule to their generic ISR routine.

This is the first step in getting rid of the hack where the driver
needs to look into the __initconfig_* linker objects.

Change-Id: I2c5eaa20d8cb5a42ef445762c426854be32c8452
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:31 -05:00
Dan Kalowsky
a60c866c70 checkpatch: error - open_brace
Change-Id: I434037ce969bcd1fc08bd4b407f9508773e64b1e
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00
Dan Kalowsky
39063598db checkpatch: error - spacing
Change-Id: Ie6e1c43581dd4b0734625b3a4e59a4ca79619e99
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00
Dan Kalowsky
3bc4039601 checkpatch: error - switch_case_indent_level
Change-Id: I9cbd6ab80b0c0f170626bb1c6b2d07498038fb8f
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00
Allan Stephens
a860cb7bff init: Support fine-grained device initialization priorities
Introduces the SYS_DEFINE_DEVICE() macro, which supports 5 distinct
levels of device initialization and 100 priorities within each level.

Note: The existing init macros (e.g. nano_early_init()) have been
adapted to utilize the enhanced initialization model, but will
eventually be retired.

Change-Id: If677029d8b711a3fae9b2f32b5470cd97d19aeda
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:30 -05:00
Allan Stephens
acd9ffe5fb init: Simplify code for array of UART devices
Gets rid of obsolete #ifdefs, since the name of a UART device's
associated variable is now constant regardless of when it is
initialized.

Change-Id: Ic6b5ce7777f067fb57aee33899a644c63040d41f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:29 -05:00
Allan Stephens
7b006066a4 init: Simplify symbol name generated by DECLARE_DEVICE_INIT_CONFIG()
Gets rid of the trailing initialization level character from the
name of the device variable generated by the macro, since it serves
no useful purpose. (The linker scripts place the various initialization
sections in ascending order based on the name of the section, so there
is no need to embed the initialization level in the variable name itself.)

Change-Id: I56bb79a513b8f77fb1f3fbaccec14454c2520772
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:24:29 -05:00
Andrew Boie
be3e3b0f8c x86: Improve exception/trap debugging
Currently when an unhandled exception or trap occurs, we don't know
specifically which one happened. The CONFIG_EXCEPTION_DEBUG option
installs handlers for various exceptions and prints out details
when they happen.

Change-Id: I4d3fe4544c3e2583c4f83b306b86ac0595d9ce0e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:24:29 -05:00
Javier B Perez Hernandez
f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Peter Mitsis
5705d06874 x86: Properly initialize _interrupt_vectors_allocated[] bitmap
Updates the 'gen_idt' tool to generate a bitmap of (statically) allocated
interrupt vectors that is linked into the final image in a manner similar to
the static IDT. The kernel then uses this bitmap when dynamically connecting
an interrupt vector, thereby preventing the dynamic irq connections
from clobbering the static irq connections.

Change-Id: I0a8f488408dad4912736865179f32f63ff1ca98f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:28 -05:00
Peter Mitsis
56fa1a98d0 x86: Update generation of static IDT
Adds two new fields to the ISR_LIST structure (irq and priority) to allow
the decoupling of the vector ID and priority from the IRQ number at some
future time.

As a result of the addition of these two new fields, the gen_idt tool is
modified to both process these new fields as well as validate them.

Change-Id: I343dac68d99c78168a25b19784140f85d5db7578
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:28 -05:00
Peter Mitsis
3bcaad8a39 x86: Simplify _IntVecAlloc() logic
Instead of using logic choosing between invoking find_lsb_set() and
find_msb_set(), mask out the unwanted bits and always invoke find_lsb_set().
This also has the side benefit of simplifying the error checking when DEBUG is
enabled.

Change-Id: I7f3e529ab3807b4433291197793e79e371d06ae3
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:28 -05:00
Peter Mitsis
616ca21599 x86: Lock interrupts when connecting interrupts
When dyanmicaly connecting an interrupt via irq_connect(), interrupts must be
locked both when allocating a dynamic interrupt stub and when updating the
interrupt descriptor table (IDT) to prevent race conditions.

Change-Id: I9c68c1f73dda478880f1a32793a84cb6eb87735e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:28 -05:00
Anas Nashif
1cc1ac4b2f move cflags setting to arch/<arch>/Makefile
Move Zephyr specific CFLAGS that depend on config options to
the Makefile where they can better be managed among other cflag
options.

Change-Id: Ia79a2f2def4f51857f6d661aa78e9fb7eb7a5e22
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:28 -05:00
Anas Nashif
2ce8d30892 remove nano/micro defconfigs, use 1 file only
Do not use micro_* or nano_* defconfigs, instead maintain platform
in one single defconfig and merge nano or micro support on top.

Change-Id: I0d5184f37865ed8312e516e48cf5a8584a287dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:28 -05:00
Tomasz Bursztyka
5fbf815419 galileo: Kconfig: Add pre-configured settings for Galileo's ADC chip
Setting up the right SPI port, its configuration and max frequency.
Also, setting NANO_TIMEOUTS by default as it is required for delayed
operation inside ADC's driver.

Change-Id: I63b2b872ff858f1d80065a94ba3e2f303d279a67
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:28 -05:00
Tomasz Bursztyka
b6303c0236 galileo: Kconfig: Make SPI built by default
Taking the opportunity to set simpler driver names for port 0 and 1.

Change-Id: I994bc43daaf6bc43b0dad564a72577c874f72d2d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:27 -05:00
Tomasz Bursztyka
93f38d26c2 spi: galileo: Fix SPI port 1 settings names
*_PORT_1_* not *_PORT_0_* obviously.

Change-Id: Idefad40c25b4ad54d9558355daab224bc634c2e7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:27 -05:00
Tomasz Bursztyka
77d6c32fc2 spi: galileo: Set the right default interrupt type
Galileo SPI interrupt is of type level low, thus setting it to this
value in Galileo's defconfig and removing useless entry in Kconfig.

Change-Id: I90bcc74be1a957bf59912d6f8c2234cfa4fe2329
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:27 -05:00
Jukka Rissanen
966401307e x86: Allow use of simple_uart driver with ia32 target
Needed to get simple uart driver working in qemu with
SLIP networking or qemu<->qemu network testing. Because
this is only needed in qemu the patch only touches ia32
platform.

This can conflict with Bluetooth in x86 and qemu so caveat emptor.

Change-Id: Iba20543f968c8fd37ee36747d9aa1ad3f782057d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2016-02-05 20:24:26 -05:00
Dmitriy Korovkin
45a0e81871 Add PCI legacy bridge to Galileo configuration
Galileo uses PCI legacy bridge to set up the following
PCI interrupt pins to IRQ mapping:
INTA -> IRQ16
INTB -> IRQ17
INTC -> IRQ18
INTD -> IRQ19

Change-Id: I8113ee16c6712f3166340d5eb0f2e0f440a37636
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:24:23 -05:00
Anas Nashif
fb473e9553 kconfig: galileo: fixed choice default values
Kconfig can't set the default for a choice, so it has to be done
using select.

Change-Id: I1d952eb48a7bcda79b4f8ff475110c7430be7b4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:22 -05:00
Anas Nashif
1dc809b23b kconfig: use zephyr as the binary name globally
do not use microkernel or nanokernel as the output binaries,
instead, use zephyr globally.

Also change the documentation to reflect this.

Change-Id: I8405761d1a0392c90cdfeec5c67d72eb4e5a76ff
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:22 -05:00
Tomasz Bursztyka
0fb4574305 gpio: galileo: Pre-configuring DW's driver in Kconfig
PCI information and integration of designware's gpio controller
with shared irq.

Change-Id: I80c7fed35ff328e06d87ebad3e2f68fdd6f5672e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:22 -05:00
Tomasz Bursztyka
a15c4a6be0 pci: Removing pci enumeration debug info
Since the console is not yet setup, there will be nothing to be printed
out. Also, it adds a dedicated init function which is only useful for
it. Instead, debugging PCI enumeration can be simply done in application
side.

Change-Id: Ia8384caa97d43f0bc4300ecf36bc11d1b8bd5581
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:22 -05:00
Tomasz Bursztyka
529ee68ef3 ns16550: galileo: Provide pre-set base address registers
As long as PCI_ENUMERATION does not work for all IP block, let's provide
pre-configured base address registers for ns16550 on Galileo.
Once PCI_ENUMERATION will be fixed, such pre-configured settings will
not be used at runtime.

Change-Id: I514b3a5759e3af04132c7801f37033108a7b279b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:22 -05:00
Tomasz Bursztyka
553cee8aea spi: galileo: Pre-configure SPI ports present on Galileo board
Providing the right settings through Galileo's Kconfig.

Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:22 -05:00
Tomasz Bursztyka
3f5083e9f6 spi: ia32_pci: galileo: Add options to allow SPI IRQ trigger
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.

Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:22 -05:00
Daniel Leung
fba6c4bedf x86: galileo: shared IRQ config has to be earlier
Perform configuration of the shared IRQ has to be done earlier,
as the config code masks the interrupt by default. If configuration
is done after shared_irq_enable() is called, the interrupt is
effectively masked. So move the init level a bit earlier.

Change-Id: Ic7f059628e3cf122d323513e171c7d1a09e5d4a6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:22 -05:00
Daniel Leung
c97474c73b x86: galileo: HPET IRQ config init to be done after IOAPIC
The IOAPIC driver resets all interrupt vectors, so any configuration
has to be done after that. Move the HPET IRQ config to later init
level so we are sure that the configuration is being done.

Change-Id: Id169461cce15252f7fb77e9c07961300233f3344
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:22 -05:00
Daniel Leung
28079bec81 x86: galileo: fix typos from __ to _
With the typos, IRQ triggering conditions are not set correctly.

Change-Id: I0698ce69c3368411a2f91a32ac27608e9f1de252
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:22 -05:00
Daniel Leung
9299ef07cc x86: galileo: expand pinmux to setup GPIOs on SoC
This expands the Galileo pinmux driver to configure the GPIOs
on the DesignWare IP block, and the core/resume wells on
the legacy bridge.

Change-Id: Ia1df4b6fd3b104f08563fe9eab93f01efbb53b66
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:22 -05:00
Daniel Leung
87ba6358d9 x86: galileo: enable GPIO and all pin muxes by default
This enables all the GPIO blocks, and pin muxes on Galileo Gen2
board. GPIO and I2C are now sharing one interrupt line so both
can now get interrupt driven events.

Change-Id: I31a4823abba84539ce5d1cc84e85b7dc335cf831
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:22 -05:00
Anas Nashif
a4907a8e98 galileo: disable debugging by default
Debugging should only enabled in the application using this
platform, not for everyone.

Change-Id: If5c17d0a87ac1d15d19ece7de93102eb2461c324
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:22 -05:00
Peter Mitsis
9664bc1a03 Remove use of SUPPORT_FP_SHARING
The Kconfig option SUPPORT_FP_SHARING does not exist.  In fact, it had been
previously renamed to FP_SHARING (this one case was missed).  Fixing this
allows the use of conditional directives in _ExcExit() to be simplified.

Change-Id: I61f98191afe776f70af3c9d9265c38c559be3486
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:21 -05:00
Peter Mitsis
8571845c15 x86: Fix default ESF
Fixes the initialization of the default exception stack frame to ensure that
every field of the structure is initialized to the dummy value of 0xdeaddead.

Change-Id: Ic7a5b66204172b53a657c9540196f01a74e1000c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
91ea542816 x86: galileo: enable shared IRQ support for I2C
The DesignWare GPIO and I2C are PCI devices which share the same
IRQ line. This patch enables the shared IRQ support for I2C. GPIO
support is to be followed.

This also enables I2C for nanokernel on Galileo.

Change-Id: I66681d71899914bdcb35c4af649d077ffb8d7970
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
32121585da i2c: dw: add shared IRQ support
On some platforms (e.g. Galileo), the I2C controller is on PCI bus,
which shares IRQ with other devices (GPIO on Galileo). This patch
adds support for utilizing shared IRQ.

Change-Id: Id4e4714aed37c2893d0ffe9ed1e4edaabb338121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
25c5ceaad1 gpio: dw: add shared IRQ support
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.

Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
0b45e8b0c2 x86: galileo: setup shared IRQ triggering condition
This adds the code to setup the IO-APIC for shared IRQ.
The code to enable shared IRQ with GPIO and I2C will follow.

Change-Id: I6e7de69f83bf7f1dd0da0571dbcb417beb2c232b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Dirk Brandewie
002c53b225 drivers: add shared interrupt driver
This driver allows multiple drivers to share a common interrupt
line. This functionality is required on system that conform to the PC
interrupt structure.  In the context of Zephyr this is needed for
SOC's that have their I/O IP blocks behind a PCI interface. Due to the
limited number of interrupt lines provided by the PCI interface
multiple IP blocks may be configured to share an interrupt line.

Drivers that share interrupts  must be modified to *not* register their
own interrupt service routine as part of their configuration/initialization
but instead bind to the correct instance of this driver by name, then
register their interrupt service routine with this driver.

Change-Id: I57b517b97ebeabce484ba53c8f940da993cb391d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:21 -05:00
Anas Nashif
0e503e54a3 kconfig: set range on IDT_NUM_VECTORS: 32-256
The first 32 entries are for well-known exceptions

Change-Id: I3342c48af6e7f687065fafd0c2af4dabc04d421e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
8834967827 x86: galileo: config: MMIO GPIO is to use I/O port access
The GPIO ports on the legacy bridge have to be access by
I/O port read/write, instead of direct memory access.

Choices in Kconfig cannot have default values in Kconfig,
so it has to be done in defconfig instead.

Change-Id: I479f3776edf5690f73d8e857ce6683285db092c0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Dan Kalowsky
ccb9b8f338 i2c: dw: interrupt selection no longer controller specific
The interrupt selectionss are no longer specific to a particular
controller (e.g. I2C_DW_0), but apply to all controllers on
the platform.

[DL: Extracted these changes into their own patch, instead of
     being squashed with others. Also modified the Kconfig
     options to move them into proper position.]

Change-Id: Idc7ac9769e947447b868dccf772a95dbb5fc8021
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
4c549fc021 x86: galileo: enable I2C by default
This adds the default config option to enable the I2C controller,
for both nanokernel and microkernel.

Note that choices in Kconfig cannot have default values in Kconfig,
so it has to be done in defconfig instead.

Change-Id: I2ac0c880629db68e5b9a6bf61e49939ab7418a89
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Daniel Leung
2104dcde39 i2c: dw: provide default configuration for controller at init
This adds the Kconfig option to specify default configuration
for the I2C controller during driver initialization.

During boot, the controller needs to be configured before
communication to slave devices can start. After boot,
an app can re-configure the controller if needed.

Change-Id: I7bf252f75a31943ae444e4d914f3a9a1a3f3d91f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:21 -05:00
Dirk Brandewie
d47dfdb001 x86: kconfig: rename "General Platform Configuration" menu
Change-Id: I560001a920e41dbcb01a34dcacc9e7914f45edaf
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
6feebeac94 x86: kconfig: move misc config options down in menuconfig
Change-Id: I23b4d32b8f6f4e1744ab787f0d447842bb2c5038
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
98a9c4abfa x86: remove obsolete BOI_HANDLER_SUPPORTED option
Begining of interrupt (BOI) is only supported on systems with a 8259
interrupt controller all modern x86 systems use APIC interrupt
controller.

Change-Id: Ife2b3b1971bbebeda597bfa1f96005f79cd7e959
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
c55c858ffc x86: remove obsolete option PROT_MODE_SWITCH
Zephyr requires that the processor be in 32 bit protected mode on
entry.

Change-Id: I71792eeb154281881e8516a7a8a2291a52f83fc6
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
3012166000 x86: remove legacy BOOT_A20_ENABLE option
BOOT_A20_ENABLE relies on the kernel being on a system that has a full
PC BIOS and requires that the A20 line be enabled to boot
correctly. None of the supported platforms satisfy either requirment.

Change-Id: I05805a050f5531de0348b60a4f0cb974e464b279
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
ca97c3863d x86: collapse AUTOMATIC_FP_ENABLING into FP_SHARING
This avoids the case where the system has multiple threads using
floating point and the threads were not properly configured to use
floating point. The misconfigured threads will only take the fault on
first use of a floating point instruction.

Change-Id: I2be9f9f145bc4e7659e07154021ccc237774897b
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
076326d053 x86: expose SSE_FP_MATH unconditionally
Allow the user to see the configure option without relying on
FP_SHARING being set.

Change-Id: I7e802c18a1c1087f7672925b18ae32dcc20787da
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
8ce92e7a5b x86: remove CPU_FLOAT_UNSUPPORTED config option
The default for x86 floating point support in Zephyr is *no* this
option is redundant and more that a little confusing.

Change-Id: I41fad33467321c483a4df028230ecbb28b4486f9
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
412390451c x86: remove CPU_SSE_UNSUPPORTED config option
SSE instructions are controlled by the FLOAT and SSE config variables
this option is redundant

Change-Id: Iab43d21315655a00daeac24994ee29a8e1c70207
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
ecbdcd9be4 x86: remove ENHANCED_SECURITY from Kconfig
The projects depend on the options enabled by ENHANCED_SECURITY select
required options explicitly. Forcing selection based on
ENHANCED_SECURITY is redundant.

Change-Id: I4473996355e67c99be91413b55d7c6685d9263b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
c081a6e987 arc: Remove STACK_CHECKING config
STACK_CHECKING is not implemented

Change-Id: I6d00e4121740a1d164d48a1a284940ee653b6925
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Szymon Janc
83e0faf19f Remove not needed stack growth direction defines
All supported platforms have descending stack (growth direction is
down). To avoid confusion just remove not needed stack direction
defines.

If new platform with stack direction up is added is should be
configured by adding Kconfig option eg STACK_GROWS_UP and
CONFIG_STACK_GROWS_UP should be used in code that depends on
stack growth direction.

Change-Id: I786ff1ab28d8f8bad3f6d1bbe64defc0e81d1707
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
4db419b6fa init: rename pure_core_init to pre_kernel_core_init
Change-Id: If61a5bdc9831c7375492446b02ecae513f054de4
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
f96f61d2f0 init: rename pure_early_init to pre_kernel_early_init
Change-Id: Id52cd7a5c1a715a5c609f88f940ec2e27341d81e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
4365f02391 init: rename pure_late_init to pre_kernel_late_init
Change-Id: I9561315a892933370d60fcf36c10d38078d66233
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
58a534b929 init: add pure_core_init level
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.

Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:20 -05:00
Dirk Brandewie
c48418f2bd init: remove pure_init macro
This macro is legacy from an early implementation of the init system
before the pure level was split into early and late phases remove it
now to avoid confusion going forward.

Change-Id: I6720874c840c9e14888fd6f411a8182e7420ca29
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:19 -05:00
Dan Kalowsky
be199be6ce pinmux: Enable the Galileo pinmux
[DL: changed mapping, and to set GPIO directions.]

Change-Id: I4153c5565b341215998645377eaad0d91da4febf
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
d9af71bcff build: fixed wrong logic for setting options during debug
From old build system -DPERF_OPT was set with no optimisation, that
was buggy and did not function as expected with new Makefiles.

Change-Id: I21ebbe0e9314d0a25cb53c6455ff244252e44af0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
74e2870366 makefile: remove quotes from platform path
Change-Id: I54ff58be05e193969a3e569f612b66e83f38a63f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
d7a1e577df build: sse compile options should not depend on a platform
Dependency on ia32_pci here is wrong, also simplify the variable
handling and logic.

Change-Id: I535e25e12283c288250b23327b2a8f698da31341
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Tomasz Bursztyka
b445e06cad x86: Add an option for legacy IO ports
Those ports uses different instructions to get accessed: in/out
instructions. It differs in many ways with memory access, and it's much
slower. It's unset by default, but some arch exposing legacy UART ports
might need it.

Change-Id: I06f2a7c7812e720863957bd20d5c2b8b02c10734
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
a1735cfacb galileo: enable I2C driver in board defconfig
We have GPIO enabled which depends on I2C

Change-Id: I289fc4cdb440e1bc95e6848e7108a3edf6638db0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
26712b6129 galileo: enable nano timers
Change-Id: I85e79877fa5951c3a731ad0898edf94f55dcb73e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:19 -05:00
Anas Nashif
2dab2bd255 i2c: move irq stubs to driver
Change-Id: I4d6a40d3c5343b444678a4adcd78a8e3fe9ab515
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
3dd4cf2fd0 galileo: rely on values from platform Kconfig
Avoid adding platform data to defconfig directly and instead
use Kconfig. This will allow overrides.

Change-Id: I95984cb691e8a796ff14b92c6985fceccb0b9cad
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
e34cd9c1cc galileo: Update Kconfig with defaults for gpio-mmio
Change-Id: I5d396fa58f9ef9f217c94d491897ec931c2efa81
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
f61a620872 galileo: set PCAL9535A gpio defaults for platform
The default values for the platform will be used when running
make *_defconfig instead of hardcoding them in the defconfig directly.

Change-Id: If2945cc11cfca787c2b93a96b502650f1dddd29d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
c842bdd76d galileo: add as a standalone platform
Change-Id: I8ca4856d9e6a9461208044242950fdde710c4ffd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
dcbf8d52b5 i2c: rename config variables I2C_DW0 -> I2C_DW_0
This makes variables readable and consistent with other drivers
we have.

Change-Id: I816f133279497eafd5d5614013c8d224d5909590
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
00cf074796 gpio: Move GPIO option from platform to driver
Change-Id: I136efa8a86314137904e191957bb0922fecdb757
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
722f42c6de i2c: move i2c kconfig entries from platform to driver
Change-Id: I1f93ccce09235fef65ad06a4a246315709203cba
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Anas Nashif
6d107887c6 i2c: rename DW_I2C -> I2C_DW
This driver naming is an exception which compared with all other drivers
we have. To keep things consistent the configuration options and variables
are renamed to <type>_<name>.

Change-Id: Ib95aa09630a507848f78d8f2c28706b545eed06d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:18 -05:00
Daniel Leung
98cc82786e x86: galileo: enable Legacy Bridge GPIOs
On Galileo, there are additional GPIO pins on the legacy bridge.
This adds the config options to enable the driver for those GPIOs,
using the MMIO-based GPIO driver.

Change-Id: I0014018238a40577631bafbdf55ed0c6c0886194
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:18 -05:00
Daniel Leung
553b8eeae2 x86: galileo: enable PCAL9535A in defconfig
There are 3x PCAL9535A GPIO chips on Galileo gen2 board.
This enables the driver for all of them.

Change-Id: Ie4d1aec9427e159a60322caac541b75e7ef973db
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
e09e80d8e7 x86: rename ia32*/*.c files have ia32 as their base name
Rename system.c and platform_config.c files in preparation for merging the ia32
based platforms to remove code duplication.

Change-Id: I88caf5294817e06c235379e92cd8ee7472e88028
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
4210a4df18 x86: Change I2C IRQ configuration function to init system routine
Change-Id: If57b8b0166a7f78b948c65f1c702475fbcb5ed9e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
c52e6481fe x86: Change GPIO IRQ configuration function to init system routine
Change-Id: If511362ec3f2dba5010052863fc350407f87aedc
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
cf80269f52 x86: Change CONSOLE IRQ configuration function to init system routine
Change-Id: Ie343b241009ab5b63c6dd877b7ce4505fe84fc6d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
1ac4e50ed8 x86: Change HPET IRQ configuration function to init system routine
Change-Id: I8adc0fe190bd253202145418ab7898bb95b7d7ec
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
25c9d021a5 x86: move IOAPIC driver to device model/init system
Change the IOAPIC driver to be initialized directly from the init
system. The function signature of _ioapic_init() function is updated
accordingly.

Change-Id: I2f824ac745926966eebb23f60445a41e1df9eb8f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:18 -05:00
Dirk Brandewie
be1b1a4e35 x86: move LOAPIC driver to device model/init system
Change the LOAPIC driver to be initialized directly from the init
system. The function signature of _loapic_init() function is updated
accordingly.

Change-Id: I5ed26d53524c8526d413a05ac9a7a58dd4264c5a
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:17 -05:00
Dirk Brandewie
1bcb7a339a x86: Move PIC driver to device model/init system
Change the PIC driver to be initialized by the init system. To be
initialized by the init system the function signature of the
_i8259_init() function needs to be changed to the standard *_init()
function signature specified by the device model.

Change-Id: I63bf1cd0ce78920fa20da94f5966e5aab4bf41b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:17 -05:00
Dirk Brandewie
6865fb658f x86: i2c: Move system binding code to dw_i2c.c
The code fragment to bind the instances of the I2C driver is not
platform specific but is driver specific.

All the information required to bind a driver instance comes from
CONFIG_ variables.  Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.

Change-Id: I9ea132c9340437ccb292bb8f3fa3d3a2b2a794db
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:17 -05:00
Dirk Brandewie
f4ded7a0c1 x86: spi: Move system binding code to intel_spi.c
The code fragment to bind the instances of the SPI driveri is not
platform specific but is driver specific.

All the information required to bind a driver instance comes from
CONFIG_ variables.  Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.

Change-Id: Iff40227e3e25d431ae870d585445971f35d934dd
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:17 -05:00
Dirk Brandewie
586776f961 x86: gpio: Move system binding code to gpio-dw.c
The code fragment to bind the instances of the GPIO driver were being
replicated in every platform_config.c  This code is not platform
specific but is driver specific.

All the information required to bind a driver instance comes from
CONFIG_ variables.  Having the binding code with the driver code
avoids duplicating the code fragments in each platform where the
driver may be used.

Change-Id: Ie07a3d12d25201e82ce7074455e6c036f463851b
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:24:17 -05:00
Anas Nashif
3206f0b231 kbuild: remove unnecessary if statements
The c files actually check for the Kconfig variables, so there is no 
need to do the checking in the Makefile again adding double logic.


Change-Id: I8521047bd575c8f9d64f7d8e5abfb5eee8a40cb3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:17 -05:00
Anas Nashif
66b55a3f7c arc: if printk is disabled, do not set variables
if printk is disabled, the variables will be unused and we will
get compiler warning.

Change-Id: I5dad791ae89d7a8c98f9e4660da472ef0caacc92
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:16:17 -05:00
Anas Nashif
d510cab958 arm/x86: update defconfig
Use fragments instead of full defconfig

Change-Id: I558d3bfa709bbea874ac3362a659252f24aca834
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:59 -05:00
Anas Nashif
81cce4ee73 arm: defconfigs: Use fragments instead of a complete config
Change-Id: I5c51a42bfc84fe506b650c12a184e0282a8a7ff8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:59 -05:00
Anas Nashif
184003a924 x86: Use fragments instead of a complete config
This reduces the defconfig file to only those options needed
for the platform. We also introduce a kernel independent config
file (no micro/nano prefix) that be the default.
Sanity checks depends on the nano/micro file naming, so until it
is modified to support the new model, we keep the old files.

Change-Id: Ife1744d88f7bf229c1da04d5b86db26678af7f6c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:59 -05:00
Anas Nashif
c124e6b3ec defconfig: Update all defconfigs before we move to fragments
In the future there will be no need to deal with such updates anymore.

Change-Id: Ib66b826f054f444ccb8f7e6f0e6a31e8d93f342f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Andrei Emeltchenko
fe39066e25 ia32_pci: Refactor UART configuration for ia32_pci
This makes platform configuration more readable and cover cases when
Bluetooth is enabled and Console disabled.

Change-Id: I49aba6e47031de86f4bb5fbe988495a1db318666
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Anas Nashif
fc3f76d751 arc: move source files to core/
Change-Id: Ic30b2579098a54ff7ab777d9d167ab58bf08ad93
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Anas Nashif
8976762df8 arc: rename generic platform to generic_arc
The generic name is too generic and when it appears on its
own, for example nano_generic_defconfig, it is not
visible what the file is about, so call it generic_arc the same
way the Kconfig platform is called.

Change-Id: Icf737f305d84142dad4f52fd26a5c7481f9fc5be
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:58 -05:00
Andrei Emeltchenko
a81c6afa4c ia32: Refactor UART configuration for ia32
This make platform configuration more readable and cover cases when
Bluetooth is enabled and Console disabled.

Change-Id: I17da603915e7e32f8e76f497d91d786ca727ca92
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:58 -05:00
Dirk Brandewie
8570e3cac2 arc: add support for generic
Add support for a "generic" ARC implementation. This is a misnomer
since ARC platforms are synthesized by the SOC vendor and are specifc
to a given vendors implementation/configuration.  This platform
support if for an SOC where we are allowed to let the code to support
the SOC into the wild but not allowed to name it in public.

This change allows to work on support for the SOC in the open and let
the rest of the community see the evolution of of the platform.

Change-Id: Idbb52fc80464ec04e91665871951f6ea79e5299d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:15:41 -05:00
Tomasz Bursztyka
608fc5071b gpio: ia32_pci: Add options to allow GPIO IRQ trigger
Add Kconfig option to specify how interrupt is triggered for GPIO.

Change-Id: I8db988efb0c081a18e585ccc6dd121bff61d6ccc
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:41 -05:00
Dirk Brandewie
dbd25aeb3b x86: Change SHUTOFF_PIC to PIC_DISABLE
Make config variable name match the function.  The PIC is never turned
on in the zephyr code so there is nothing to shut off.

Change-Id: I1627e5a35cc37ef7959f36758c1e1aec03e22782
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:15:41 -05:00
Dirk Brandewie
728baf1336 x86: arm: Remove deprecated PLB_* macros
Change-Id: I24a9ea61ff8ffb0602e30cf929aeb47f5b9a53b7
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:15:41 -05:00
Daniel Leung
e495f95a43 x86: ia32_pci: add options to allow I2C IRQ trigger
Add Kconfig option to specify how interrupt is triggered for I2C.

Change-Id: I5f5afdf6bfc2adbfc2f66bdc1f58bd3a8fc60ecf
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:41 -05:00
Daniel Leung
80c880c8cb x86: ia32_pci: allow disabling 8259 interrupt controller
This simply copies the PIC disabling code from ia32 into ia32_pci.

Change-Id: Ib48cb96d3f0ba7356431ce1b2221f3f346e61c8d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:41 -05:00
Anas Nashif
e81942e538 arc: do not include arch/cpu.h, nanokernel.h has it
Change-Id: Ic8537168211292fcedcb9c1d283d638029473932
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:36 -05:00
Anas Nashif
8e6e3dd380 make disabling nested interrupts configurable
Change-Id: I43b8e2e20f8c9ad3923415b943dc5a7c97bd0121
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:36 -05:00
Tomasz Bursztyka
26e7aaf1f1 ia32: Removing useless inByte/outByte declarations
ns16550 was the only driver using those, and now that it properly uses
sys_io.h functions we can remove inByte and ouByte from ia32's board.h
files.

Change-Id: Id2a691b8ecf43baacd64bc9be09feb15ef9eb339
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:36 -05:00
Tomasz Bursztyka
a566afbebd ia32_pci: Add support for the designware i2c controller
Only 1 port is available on Quark through the PCI bus.

Change-Id: Ie0e0173686947134d2553dd0fd0230ffa5a1d456
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:36 -05:00
Dan Kalowsky
998cc8e3d4 i2c: import of Synopsis DesignWare I2C
Initial import of Synopsis DesignWare I2C driver functionality
for the Zephyr Project.  This import has been tested for host
master control.  While it does contain the code to work as a host
slave, this code has not yet been completely tested and validated.

Change-Id: I3df0214f6e3b6798f7dad4819d09c3ec5998e508
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:15:36 -05:00
Tomasz Bursztyka
e6252dd0ba ia32: Handle CONFIG_EARLY_CONSOLE
This will initialize the UART console port at an earlier stage than
usual in order to get early debugging outputs.

Change-Id: Ica90fe3481687ef20488b59f6d554a8af1d22559
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:36 -05:00
Tomasz Bursztyka
cb1774c548 gpio: Correct the PCI pre-set informations
- Device ID was wrong
- Setting default class id

Change-Id: I9fd1df284eca4067c21beffa7599307a40be5144
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:36 -05:00
Tomasz Bursztyka
c0800e9248 galileo: Provide pre-set base address of the 2 UART ports
This way, it will be possible to use Galileo and it's UART ports without
PCI_ENUMERATION set.

Change-Id: I9498aca818b128a6ee69fde21aa5c4b9cd6bc1ad
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:35 -05:00
Anas Nashif
b3b16c6323 kconfig: add NSIM option to arch Kconfig
The option is being referended by the same file
but is not being defined anywhere.

Change-Id: I5e0ec4c29cba773a5256bae52190a117fcc12bf3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:35 -05:00
Tomasz Bursztyka
989e59590e irq: Remove CONFIG_PIC #if/#else since such option does not exist
Change-Id: I651df6069c4b5fea3b0e5319a6de6b64056ff9b7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:35 -05:00
Anas Nashif
f488e8c02c kconfig: update defconfigs for release
Change-Id: I37ff5d1390acadd79298ea97dfa9844701e86904
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:35 -05:00
Anas Nashif
34f42b5676 Kbuild: fixed arc compiler options
This was messed up due to lack of arc platform to test.

Change-Id: I5abda172dddf54532c1bcb66f36d02db7f7d7ff4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:35 -05:00
Andrew Boie
33282f2aaa profiler_arch.h: remove broken, unnecessary #include
Change-Id: I8744413a156a928dab9d71b0e6f0b4aa5f13a300
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:15:34 -05:00
Anas Nashif
b0bddce1f5 Update defconfigs with all new CONFIG options
Change-Id: Ie6dfd01b86818962a1473f411bd49f5d2a04f3cd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:34 -05:00
Anas Nashif
db0f9c1841 Remove offsets Makefile, it is built using top-level Kbuild
The top level Kbuild file builds the objects and generates
offsets.h using the gen_offset_header tool.

Change-Id: I24569572085d40547e893942203233f4aa647fac
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:33 -05:00
Anas Nashif
be26b52406 Sync arch/<arch>/Kconfig files
Put architecture option and ARCH_DEFCONFIG on the top
and simplify default options for the architectures.

Change-Id: I4cae73f3e9ec24913e201269ec6dc8eddc2fd7c1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:33 -05:00
Anas Nashif
e3ac0907df Move scripts/Makefile.<arch>preparch to arch/<arch>
Follow the model of the Linux kernel for adding arch
specific CFLAGS by using the Makefile and Kbuild combination
in the arch/<arch> directory.

This will also allow adding architecture specific targets and is
easy to maintain when alongside the architecture.

Change-Id: If51a78e8845baa71d9090c4a4f49fcd013354840
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:33 -05:00
Andrei Emeltchenko
d6ddf7bf4e ia32: Add UART configuration option
UART uses level triggered interrupt, low level

Change-Id: I7c3257aca00c559bb0d9ac48571bf9ed67d5aa23
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Andrei Emeltchenko
728a068d7e galileo: Add UART interrupt configuration option
Change-Id: I7d8a3cf06625b6592e5ce7abbbd8e4e249bb5822
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Andrei Emeltchenko
69871aaecc uart: Configure ioapic for UART interrupts
Follow similar configuration for other platforms.

Change-Id: I1478d10799cbb375c715bed4d30d1bcf223d282f
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Andrei Emeltchenko
672022d920 uart: Use standard config based ioapic configuration
Follow other boards configuration method.

Change-Id: I045f9bbeb3d7d0a0ed1abe76c33be93dade07b9e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Andrei Emeltchenko
7373f784f0 platform_config: Remove unneeded check
CONFIG_UART_CONSOLE is already checked so this one is not needed.

Change-Id: I557880bd190f4ef0b7e439520991669354bb3b4f
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Andrei Emeltchenko
41f1fe3571 system: Remove unused IOAPIC serial configuration
Change-Id: I90017525b8fae661856cfdbc13612f37a6d9ea11
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:32 -05:00
Tomasz Bursztyka
c75bf6275d arch: Add gpio support for ia32_pci
Change-Id: I45900966367beea7d74e4f54cb33b6ad272f9f24
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:32 -05:00
Dirk Brandewie
77a78f0827 gpio: Add driver for Synopsys DesignWare GPIO devices
[DL: captilize commit message title; fixed some whitespaces;
     changed the __initconfig_gpio_* from level 0 to level 1,
     which is the level of pure_init; and added include path
     to board.h; ]

Change-Id: I7eea6a6ca9e4b7cf8d1ccabb57f07f786da93ef0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:32 -05:00
Tomasz Bursztyka
1e39d6274b uart: Properly integrate driver config within PCI context
- Makes the code simpler in driver side
- Configuration is done on platform's config.c file and not the driver
- Handles CONFIG_PCI_ENUMERATION setting

Change-Id: I9b8376cebd7e0b62279251da132a2c4ee7b2e148
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:32 -05:00
Tomasz Bursztyka
e4479cd0cf spi: Handle the support for PCI_ENUMERATION
Without it, it won't go through a pci scan, and will just trust the
pre-set information for the bus/dev/function to enable the memory
mapped registers.

Change-Id: Ica9156be541619dce9684dd45f70e05b69782a7c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:32 -05:00
Tomasz Bursztyka
018bcfe8d4 pci: Add an option for enumerating PCI devices
This option will be used to disable PCI enumeration (not PCI bus) to
gain in code size and execution as long as driver will be properly
configured statically. Thus setting this option as set by default.

Change-Id: I7da5d154c8ee89e44fc2bad8e85a5a20f498927e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:32 -05:00
Anas Nashif
d968cacc64 defconfig: Update all defconfigs with new options
Change-Id: I0706039df412400aa538aca8c66de8e98651365a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:31 -05:00
Yonattan Louise
13d583dc06 Rename microkernel struct field 'Args' to 'args'.
Rename field 'Args' of the struct:
- 'k_proc' in the file include/microkernel/base_api.h
- 'k_args' in the file kernel/microkernel/include/micro_private_types.h

Change-Id: I5847a2f1e9c7dd34dea37857b4fadeb37ced489b
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:29 -05:00
Yonattan Louise
36d55187f2 Rename microkernel struct field 'Group' to 'group'.
Rename field 'Group' of the struct:
- 'k_proc' in the file include/microkernel/base_api.h

Change-Id: I0d83ec7e82c67a7c2c37df8bb0a5d83b2109a8ed
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:29 -05:00
Yonattan Louise
617501354c Rename microkernel struct field 'Ident' to 'id'.
Rename field 'Ident' of the struct:
- 'k_proc' in the file include/microkernel/base_api.h

Change-Id: Iec787e0a8aa1791c968b371017cf96211a60cef1
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:28 -05:00
Tomasz Bursztyka
d96943b04c spi: Add support for Intel's SPI controller
Such controllers are found in Quark's X1000 series, and thus are found
on Galileo boards v1 and v2.

Change-Id: Ib71486c9f27de1b6c48ce3cb3dd138d69833c2ea
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:28 -05:00
Tomasz Bursztyka
ff39559146 pci: Add support for filtering by function
This will be useful for PCI based drivers to integrate fully within
the device driver model, where they will have to provide the function
they are found.

Change-Id: I7d64a4c6727cee52cbcb743c859cda43ac1a853b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:15:28 -05:00
Yonattan Louise
5c6ef8fdb5 Profile low condition events.
Add the sleep events point for x86 and ARM arquitectures that gives
information about when the CPU went to sleep mode, when it woke up
and which interrupt causes the CPU to awake.

Change-Id: Iaa06a678eab661357d084ee1f79c4cfcf19bf85d
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:28 -05:00
Yonattan Louise
d2108bf084 Profile interrupt events.
Add the interrupt profile points for x86 and ARM arquitectures. This
gives information regarding the time when interrupts occur.

Change-Id: Ic876c0e7f9e8819d53e0578416f09146f4456d3d
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:28 -05:00
Anas Nashif
6b3d8acf98 arm: cleanup whitespaces
Change-Id: Ic119697615c641db80f80d7997f43d3a3cab6b91
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:28 -05:00
Anas Nashif
2b33b09387 x86: cleanup whitespaces
Change-Id: I42fc5113a1ba5f6d3acc6fb6db8afc0c1c52b4ec
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:28 -05:00
Andrei Emeltchenko
c4c2bdda71 Bluetooth: Add console configuration to ia32_pci
Added static Console configuration for ia32_pci. IRQ and other
parameters might be received from PCI scanning but that needs to be
reworked with functions like IRQ_CONNECT_STATIC which requires fixed
static interrupt number. When this is fixed we use PCI dynamic
parameters.

Change-Id: I07c07f16fbac8f5de999f9cf8746eea0d453198b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:27 -05:00
Andrei Emeltchenko
1f94f6ee2a Bluetooth: Add configuration for Bluetooth to ia32_pci
Added static Bluetooth configuration for ia32_pci. IRQ and other
parameters might be received from PCI scanning but that needs to be
reworked with functions like IRQ_CONNECT_STATIC which requires fixed
static interrupt number. When this is fixed we use PCI dynamic
parameters.

Change-Id: Iac0796fd3f78b92237999e40de5c3d563b2bc319
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
e80d06deed arch: rename context.c files to thread.
Also for ARC, rename context_wrapper.S to thread_entry_wrapper.S.

Change-Id: I83318ae352a688996f8436cf3252f6108ec23dc5
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
97f2622f55 arm: rename instances of CortexM
Directory names: CortexM -> cortex_m
Code comments: CortexM -> Cortex-M

Change-Id: If946ed25fac863e0be9dbb6f6c275199402b0b0a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
4dca2dfad3 util: make is_power_of_two() a public utility
Somewhat useful utility that should only have one implementation, so it
can impede on the normally-available application namespace.

Change-Id: I085850177c231fdf58634f97e897c4d2e1a5cffb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
0dcad8331b clarify use of term 'context'
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.

APIs that had their names changed:

  - nano_context_id_t is now nano_thread_id_t
  - context_self_get() is now sys_thread_self_get()
  - context_type_get() is now sys_execution_context_type_get()
  - context_custom_data_set/get() are now
    sys_thread_custom_data_set/get()

The 'context' prefix namespace does not have to be reserved by the
kernel anymore.

The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):

  - struct ccs is now struct tcs
  - tCCS is now tTCS

Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
b981326ae9 microkernel: remove last remnants of 'process' from text
There is no concept of a "process" in the system, so remove last
mentions of that concept from free-form text (doc, comments, macro
parameter names).

Change-Id: Ic1b73371c448ed93b0db46bc9bb412d1e1dbc8bd
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Benjamin Walsh
bed144b179 microkernel: rename k_proc to k_task
k_proc was a legacy leftover that does not make any sense, since there
is no concept of a "process" in the system. Rather, that data structure
refers to a 'task control block', i.e. the representation of a task
execution context from the microkernel's point-of-view (not to confuse
with the 'struct ccs', the representation of a thread execution context,
from the nanokernel's point-of-view).

Change-Id: Ic29db565af023be629ce740bbcb652ece7dc359f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:27 -05:00
Juan Manuel Cruz
044bfc60c5 build: INIT_STACKS memset fix.
This commit fixes an issue with INIT_STACKS configuration option.
k_memset is substituted by the libc memset routine to initialize a
block of memory.

Change-Id: Ic3e286d0976f618110b2828f6da76417b868aef0
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:15:26 -05:00
Peter Mitsis
f5f78432ed x86: fix basic_atom's SYS_CLOCK_HW_CYCLES_PER_SEC
The Kconfig option SYS_CLOCK_HW_CYCLES_PER_SEC for the basic_atom platform
configuration was mistakenly left at 900000000.  That value was necessary
when basic_atom used the LOAPIC_TIMER, but as it now uses the HPET, it must
use 25000000.

Change-Id: If2735895edfe2f67905bf57e4008efbee50084f7
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:26 -05:00
Dmitriy Korovkin
fa05dcee01 Make HPET use level-triggered interrupts on galileo platform
In order to cover maximum of code, make different platforms
use different driver configuration. This way basic_atom uses
legacy emulation combined with edge-triggered interrupts while
galileo platform uses normal mode combined with level-triggered
interrupts.

Change-Id: Ib80553dbb16cf6bbe61ee5e41788031037f41860
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:15:26 -05:00
Dmitriy Korovkin
c1c867af08 Fix HPET interrupt triggering for basic_atom platform
HPET in legacy emulation mode uses rising edge triggered
interrupts on real hardware.

Change-Id: I4f734a5147864b492618a887e1d0d780e6e17aa8
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:15:26 -05:00
Dmitriy Korovkin
93b0ced44b Order hardware and device initialization
The initialization procedures need to be called in the
following order:
- basic hardware initialization;
- devices initialization;
- hardware clock initialization, that the kernel needs to
  run the kernel server.
This way, the board initialization routines is placed
to the pure_early_init level to make sure it runs first,
all device initialization procedures run at pure_init level,
so they are initialized early enough to be used for debugging
if needed. Hardware clock initialization is placed on
nano_early_init level to make sure hardware clock is initialized
just before the kernel server starts.

Change-Id: Ieecf9f0252c47c621b7208969687dc1113fc2ad0
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:15:26 -05:00
Dmitriy Korovkin
a34780f663 Fix system hardware clock frequency for FRDM k64f platform
The board runs with 120 MHz CPU frequency, the systick
uses CPU frequncy. This way 120MHz is a correct value.

Change-Id: If47f1ce6371fb7202ececb4d5f8f7c984aa66598
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:15:25 -05:00
Anas Nashif
cae3f84d99 idtEnt.h: fixed coding style
Change-Id: Iba12b41b78b4bd8c773aad80dd481405b7b0c17a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:25 -05:00
Anas Nashif
b2f5c48755 remove shared/ and create files directly
The files idtEnt.h and segselect.h in shared are linked from
the source tree for no good reason adding and extra top level
directory that might be confusing.

The shared/ here means shared between host and target, this is
not longer necessary in our build system.

Change-Id: Id9665e10de7a1d290888d9069be3db9f4330d284
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
e564035521 serial: rename struct field int_pri to irq_pri
This is just a cosmetic change to unify anything interrupt related
under 'irq'.

Change-Id: Ib8804d194e11eb49526fda952d9efc0f2ffac2df
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
f20e07003b arch/arm: ti_lm3s6965: do not force enable Stellaris serial
This allows the serial driver to be excluded from the build.

Change-Id: I74549b058d85bf35acf9d719643139901ae5973e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
af1a297358 arch/arm: fsl_frdm_k64f: do not force enable K20 serial driver
This allows the serial driver to be excluded from the build.

Change-Id: I1be0ee5bc6817ac03ed23dcc9925cff1b694d584
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
ad4d624e6b arch/x86: Kconfig: do not force enable NS16550 serial driver
This allows the serial driver to be excluded from the build.

Change-Id: Ibd65cea07e753de0d452879bfdac8f3a421db5e7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
d8f10f4c01 uart_console: make baud rate configurable
Move the baud rate selection for uart_console into Kconfig.
This allows apps to specify custom speed. Default is 115200
which should be supported by almost all RS232 and USB adapters
out in the past few years.

Change-Id: I78649bf2a1b2ddfc90a20d611a6454e3ad3b1b3a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
40147440f5 serial: utilize dev->driver_api for new driver model
This is the final step to convert serial to the new driver model.
The dev->driver_api is now being used by individual drivers.

As a side effect, it is now possible to build multiple serial
drivers in the final image (though it won't make much sense).

Change-Id: I5d864e6503a5431b29006c311320155adf81cf5b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
c384571add console: uart_console: introduces CONFIG_UART_CONSOLE
This introduces the config option CONFIG_UART_CONSOLE,
and also CONFIG_CONSOLE. The UART console can finally
be disabled if desired.

The defconfigs are also being updated.

Change-Id: I5ebaf6471986deca105971e67fcddb43374de94a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
ad2d29689e console: uart_console: decouple uart console init from UART init
With this, the UART console has its own initialization which is not
dependent on UART init routines.

This will allow the app to utilize all UARTs for other purposes,
instead of always reserving one for console. Future patch
will enable this choice.

Note that the console init is effectively demoted to pure_init
from pure_early_init. The UART console depends on UART being
initialized, but there is no deferred init at this point.
So this initializes the console a bit later than UARTs,
simply to make sure the UART is initialized before using it.
Once there is a mechanism for some type of deferred initialization,
the UART console init can be promoted back to pure_early.

Change-Id: Iba95197b13384cb1a46e34c78638348b7a0bec8c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
2fd29e2667 serial: converting to new driver initialization model
This restructures the device structs and now utilizes the new
driver initialization model. This is another step towards
converting the serial driver to the new driver model.

Note that the serial driver does not initialize the hardware
unless it is being used by another driver. The configuration
of the serial port needs to be done by the driver utilizing
the port (e.g. baud rate, interrupt priority, etc.).
Therefore, some serial ports are declared but not exactly
configured.

Also note that the UART console is being initialized at
the same time as the serial port. This will be removed
in future patch, so the UART console driver will do
its own initialization.

Change-Id: Idd89954b2d0649a557ba8c869ee96512fec898e4
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
199c47987f serial: introduce CONFIG_SERIAL
This encapsulates the whole serial drivers Kconfig sections, and
allows the whole section to be deactivated.

Change-Id: I84f8d35da74f3c00a44d8c17786ea2297422d68b
Signed-off-by: Daniel Leung <danielcp@gmail.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
0f7a78ce1b bluetooth: move static device definition to platform configs
This moves the static device definition from the driver file,
drivers/bluetooth/uart.c, into the platform config files for
each platform.

This is another step towards converting UART drivers to
the new driver model. Also, platform config files are a more
logical place for the definition.

Change-Id: I668a52de5a38005b8b2bcb67d74437ead377cb16
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
a4212108f7 serial: remove unused CONFIG_EXTRA_SERIAL_PORT
Change-Id: Ibb8ffcd377d9b7c34370c522fb06ce797f4feaed
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Daniel Leung
1ad2a56ee3 serial: rework functions to use struct device...
... instead of an array index to a global array. This is
an intermediate step to make the drivers conform to
the new driver model.

This only changes from using a direct array index to using
device structs. The UARTs are still staticlly defined.
Later patches will make the drivers utilize the driver
initialization procedure specified by the driver model.

Change-Id: I18041bbb4b0efdf8ae87088fd000b391d0827e9b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:15:25 -05:00
Benjamin Walsh
1bab46dca1 ffs: rename find_[first|last]_set to find_[lsb|msb]_set
The new names reflect better what the functions do: they find the first
bit set starting from the least or most significant bit, i.e. they find
the least or most significant bit set, in a 32-bit word.

Change-Id: I6f0ee4b543f6f37c2f08f7067e14e039c92a6f6a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:25 -05:00
Benjamin Walsh
910970ed0f ffs: remove non-inline find_[first|last]_set()
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.

Change-Id: Iee2e6adcfb5da1fe0a978a05aa854e10ae82a8b8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:25 -05:00
Peter Mitsis
92d1810def Fix typo: occured -> occurred
Change-Id: I40150719135108f18834a35db1c5be7ca4c5c9b2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh
2c5086cc65 irq: remove non-inline irq_lock/unlock
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.

Change-Id: I7314b96c42835f15df4c537ec11ab7961d4ee60f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh
6469e578cb irq: do not use _inline versions of irq_lock/unlock
Standardize on using the irq_lock/irq_unlock (non-inline) symbols
everywhere.

The non-inline versions provide absolutely no benefits, so they will be
removed in a subsequent commit, and the inline versions will have their
_inline suffix removed.

Change-Id: Ib0b55f450447366468723e065a60adbadf7067a9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh
aa78793e40 microkernel: rename K_swapper to _k_server
Align with the newer terminology used for microkernel internal symbols.

Change-Id: I623b383f90d9e37a49429a79774c7f7a4953bd5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Benjamin Walsh
c1f9fd888d irq: make utility functions private
irq_handler_set, irq_priority_set and irq_disconnect have been made
private by prepending an underscore to their names:

	irq_handler_set -> irq_handler_set
	irq_priority_set -> irq_priority_set
	irq_disconnect -> irq_disconnect

The prototypes have been removed from header files when possible, and
extern statements used in C code where they were called.

_irq_priority_set() for ARM is still in the header file because
IRQ_CONFIG() relies on it.

Change-Id: I2ad585f8156ff80250f6d9eeca4a249a4477fd9d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:21 -05:00
Yonattan Louise
520542bef2 Add context switch profile point.
Add the context switch profile point for x86 and ARM arquitectures.

Change-Id: Ib7205059104ed47b96ba75b8cfefec3ff35f6813
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:20 -05:00
Yonattan Louise
efd8e246cc Add profiler method.
Add a standardized mechanism to add profiling points to the Kernel
with a single interface for the user to collect the profiling data.

Change-Id: I4fa34ac1b42f73a73ba1fd805e755ee2fd00dff7
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:20 -05:00
Yonattan Louise
8c85c15a2f Add event logger.
Add a log event tool with a single interface for the user to
add/collect the event log data.

Change-Id: Ia4b78836748c5d7e44ba1bdd50c28434e8a55d65
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:15:20 -05:00
Andrew Boie
91156d9c7a arc: standardize ffs function names to match other arches
Change-Id: I4f384960f4c6698ef98ecf3941c30f849832135e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-02-05 20:15:20 -05:00
Benjamin Walsh
4c63796838 ia32_pci: rename N_PIC_IRQS to NUM_STD_IRQS
That number is not representing the number of PIC IRQs, but rather the
number of "standard", fixed-number IRQs on a (legacy) x86 PC platform.

Change-Id: I1f0fff4c6d24f1d49764efef93f6e5ca3f181168
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
c963861d47 Remove PIC code, but not PIC disabling code
Removes the non-PIC disabling PIC code as the PIC is not a supported interrupt
controller.  The PIC disabling code remains as it is needed to prevent the
generation of spurious interrupts from the PIC (see CONFIG_SHUTOFF_PIC).

Change-Id: Ic59aa17ab96f34685a5d7b5f24cab391de47edca
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
dba5ac622c Remove PIT code
The PIT is an unsupported device.  On x86 based platforms, the LOAPIC_TIMER and
HPET_TIMER are the only supported timers.

Change-Id: Ic890838c811b7eb62008aef0c8a92786f1579217
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
dbaa4a45ed Use LOAPIC and IOAPIC Kconfig options
Removes the LOAPIC and IOAPIC macros from board.h as they are no longer
appropriate since Kconfig options exist to use in their stead.

Change-Id: I2ce41a7a08d1859682389f35cd5a97c0e2cd5bf7
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
2db3db4ce2 Create IOAPIC and LOAPIC Kconfig options
Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove
those settings from the relevant board.h files.

Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
658bb54ed1 Use LOAPIC timer Kconfig options
Removes the LOAPIC timer macros from board.h as they are no longer required
since appropriate Kconfig options exist to use in their stead.

Change-Id: Id0b509eba7cce1839b400f95b989bf886322e1a8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:20 -05:00
Peter Mitsis
8760c49d80 basic_minuteia to use HPET timer
Updates the basic_minuteia platform configuration to use the HPET timer as both
the PIC and PIT will be removed in a future commit.

Change-Id: Ieefcf48175d6d2731acd6b39a5e73879902940b1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
578d417e87 Use HPET timer Kconfig options
Removes the HPET timer macros from board.h and uses the HPET timer Kconfig
options in their stead.

Change-Id: Ia0b3cd87716277ac25f12deb31d5c5934f355050
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
366962557c HPET: Add additional Kconfig options
Adds additional Kconfig options to the HPET timer for setting its base address,
IRQ, IRQ priority and condition for triggering an interrupt.

Change-Id: I80349c60237380129da9ef41ccf6850c6b874c3c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
bbb57b5f80 ia32: Add HPET timer initialization abstraction
Initializes the HPET timer if it is configured into the system.

Change-Id: Ia9474e868101abe88e031266b956c6a559745d75
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
097a1a17dc ia32_pci: Abstract device initialization
Abstracts the initialization of the following devices:
    LOAPIC, IOAPIC, and HPET TIMER
This allows for a more configurable ia32_pci platform.

Change-Id: I05d0d983c163be499dd967ffe0121290a4305c9e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
9216a2cbb9 cosmetic: Fix camel case in ia32 and ia32_pci platforms
Converts camel case routine names to lower-case with underscores to comply with
coding practices.

Change-Id: I9fac0d3858389039c00882a7d2e97fcd4e4c812b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
3ecf65e5ef x86: Rename quark_init() to ia32_pci_init()
The new name corresponds to the platform (ia32_pci), whereas the old name
referred to the old platform/bsp name.

Change-Id: I1b6f3416db146af4fdbadf70d0ab153741c781d5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
0ea6e60035 x86: Rename pc_init() to ia32_init()
The new name corresponds to the platform (ia32), whereas the old name referred
to the old platform/bsp name.

Change-Id: Ia8fe5d2b35bceb7e04dd8ac9c41b9de7947ed1f9
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Peter Mitsis
503dd66334 x86: Remove obsolete IOAPIC initialization comment
Change-Id: I26d75e36191f348598a807f5f943de99cc3bcf67
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:15:19 -05:00
Anas Nashif
abb4404689 Move PCI settings to drivers/pci
Change-Id: I92ccbcdd1292f8f4f017b45968c2204c06e6f73e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:15:19 -05:00
Benjamin Walsh
add6b9794b arc: fixes in context switch explanation comments
There were some typos and some weird phrasing.

Change-Id: I7b183755058e5ffedca97d434c43f448aafd1926
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:19 -05:00
Benjamin Walsh
ac60583b76 drivers: rename cortex_m_timer to cortex_m_systick
The name of the device is SYSTICK. The device name should be part of the
file name, like all other timer drivers we support. The name
'cortex_m_timer' said nothing about which device the driver is for, since
it's way too generic: it could be for any timer present on any Cortex-M
board.

Change-Id: I39b4f79c32516ec9aff82c55c0ca639fad1b52bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:15:19 -05:00
Daniel Leung
74c8852d05 microkernel: remove kernel service dispatch table
This change removes the internal number-to-function mapping
of microkernel services. Instead, function pointers are used
to specify which service to use.

This is in preparation for private kernel objects. Before this,
only kernel objects that are defined in MDEF files would have
corresponding functions included in the final binary, via sysgen
by populating an array of number-to-function mapping. This
causes an issue when a certain type of objects are all defined
with source code, and never in MDEF file. The corresponding
mapping would be deleted, and the functions are never included
in the binary. For example, if no mutexes are defined in MDEF
file, the _k_mutex_*() functions would not be included.

With this change, any usage of private kernel objects will hint
to the linker that those functions are needed, and should not be
removed from final binary.

Change-Id: If48864abcd6471bcb7964ec00fe668bcabe3239b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2016-02-05 20:14:46 -05:00
Peter Mitsis
619eec89ce x86: Renames "Specific CPU Capability Support" menu
Renames the menu to "Processor Capabilities" as it is both more concise and
it gives a more "consistent feel" to the menu names (referring to the platform
equivalent "Platform Capabilities".)

Change-Id: I1f835e11e382f811720c17e194b4bf410ef74d31
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
1c701bc83a x86: Merge platform capability related menus
Reduces redundancy in the x86 Kconfig menus.

Change-Id: I90ff7d6aedda2aa02528b6821eeaf7eb6bea321c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
e8839abb4a Remove Kconfig option PROT_MODE_SWITCH_PROMPT
The Kconfig option PROT_MODE_SWITCH_PROMPT was being used to conditionally
display the "Boot Sequence Options" Kconfig menu. It is simpler to include
both PROT_MODE_SWITCH and its dependent BOOT_A20_ENABLE in the parent menu.
However, doing so necessitates that the name of the parent menu be changed
from "Bootloader Options" to "Boot Options".

Change-Id: I9b9a074a0d4ec5209f5349b42178409c73875b00
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
39fc84e65a x86: Change order of floating point options
Changes the order of the floating point options so that the SSE Kconfig options
are not interspersed with the floating point options.

Change-Id: I8390b5049f95b3088e7abf48bf492a544e7f5f50
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
9d5599af05 x86: Fix selection of unsupported FLOAT/SSE Kconfig options
It makes more sense to have the x86 Kconfig options CPU_FLOAT_UNSUPPORTED
and CPU_SSE_UNSUPPORTED to be selected by the CPU than have those options
dependent upon the selected CPU.

Change-Id: I862baabee6a81cc79206c37a50b8594354a40403
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
4d092e9510 x86: Remove superfluous Kconfig dependencies
There is no need for any x86 Kconfig to have a dependency upon the following
Kconfig options as they are always true when building for ARCH=x86.
    X86_32
    ISA_IA32
    ARCH="x86"

Change-Id: I810e9712589199871953f043e8be746ab03230f8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
34b1a9043f x86: Remove leading spaces in Kconfig files
Uses tabs instead of spaces for consistency.

Change-Id: Ic85b710dc7f667f9b28b97839f020921afe13f3f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
125fe19205 x86: Remove HARDWARE_BP_SUPPORTED Kconfig option
The Kconfig option HARDWARE_BP_SUPPORTED is not used.

Change-Id: Ifed886f733e8125ef1c45926e46e31ff48d06316
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
87de8c493f x86: Re-order x86 Kconfig menus
The top-level menus "x86 Core Options" and "Bus Options (PCI etc.)" are now
sub-menus to the the top-level menu "General Platform Configurations".

Also, the "Board Capabilities" sub-menu has been hoisted out of the
"x86 Core Options" menu and placed as a renamed sub-menu
(Platform Capabilities) to the top-level "General Platform Configurations"
menu.

This helps to create a more logical flow when using "make menuconfig".

Change-Id: I3a837b039eb735ec4073a1721f00753705fba020
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
55ffc8cc61 x86: Fix up "Board Capabilities" summary lines
Fixes up the summary lines in the "Board Capabilities" menu so that the
descriptions are more consistent with each other as well as their option names.

Change-Id: I6a030af702340c5ef634217ff6d4bfd046ed24c5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
ae6ea21005 Kconfig: Create PLATFORM_IA32
Combines the following Kconfig options to create PLATFORM_IA32:
    PLATFORM_GENERIC_PC
    PLATFORM_PCMINUTEIA
    PLATFORM_ATOM_N28XX

The new name aligns with the 'arch/x86/platforms/ia32' platform directory.

Change-Id: I4474cb43040f888d5164382184c27bbb38527440
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
739489f337 Kconfig: Rework PLATFORM_QUARK to become PLATFORM_IA32_PCI
1. The new name aligns with the 'arch/x86/platforms/ia32_pci' platform
   directory.
2. A shorter prompt works better with menuconfig.
3. Removes IOAPIC selection as HPET_TIMER selection makes it implicit.
4. Removes LINK_AUX_COMPILER_LIBS selection as it does not exist.
5. Removes CPU_MINUTEIA selection to permit CPU_ATOM as a valid choice.

Change-Id: I55694d2594a103f4f5ca233c279df0556ff1327f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
fa97d9e386 x86: Update default platform configuration files
Updates the default platform configuration files as they had not been properly
maintained.

Change-Id: I5f554c287af51f4d7dcf224b7816f40d14c576d4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:45 -05:00
Juan Manuel Cruz
f1a3ba3931 FP_SHARING duplication.
This commit removes the FP_SHARING and AUTOMATIC_FP_ENABLING
Kconfig symbols.

This Kconfig symbols were defined in arch/x86/Kconfig and
arc/x86/core/Kconfig as well.

Change-Id: I2ed19c32dbb8e16935343b71fb2c2739228e9fb2
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:45 -05:00
Juan Manuel Cruz
78296611b4 CONFIG_ADVANCED_IDLE duplication.
This commit removes the ADVANCED_IDLE and ADV_IDLE_STACK_SIZE
Kconfig symbols.

This Kconfig symbols were defined in arch/x86/Kconfig and
kernel/microkernel/Kconfig as well.

Change-Id: I17cc28cdf6f07c8a85acad7318b2b4ce6a06f4bc
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:45 -05:00
Peter Mitsis
ed610c5bd5 x86: Replace references to BSP with platform
Removes references to obsolete BSP terminology.  Where appropriate, replaces it
with platform terminology.

Change-Id: I41fc099844d137dd0ea87cce0f675dc6f022ad40
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:43 -05:00
Peter Mitsis
7175ec33a2 arm: Replace references to BSP with platform
Removes references to obsolete BSP terminology.  Where appropriate, replaces it
with platform terminology.

Change-Id: I26c199c50fefc9729ec07c48083bedc86890cc89
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:43 -05:00
Peter Mitsis
fd0f9a2047 arm: Rename IRQ_VECTOR_TABLE_BSP to IRQ_VECTOR_TABLE_PLATFORM
Replaces references to obsolete BSP terminology with platform.

Change-Id: Ibd083558bbbb08a16a68d58251774fb4c84cbbf8
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:43 -05:00
Peter Mitsis
f1bcbf51f0 arm: Remove obsolete SW_ISR_TABLE_BSP Kconfig option
The Kconfig option SW_ISR_TABLE_BSP is not used anymore.

Change-Id: Ifc1be395f5ed7e5d1072a783d800385e69fbc4dc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:43 -05:00
Dmitriy Korovkin
5a57c36a6c Fix galileo configuration to HPET
Add to the configuration that HPET timer legacy emulation
mode is not used, as hardware does not support it.

Change-Id: I51175a0ce8f06c9c38a3fc36f9723e431fc72dd6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:42 -05:00
Dmitriy Korovkin
6ab23e30da Port basic_atom configuration to HPET
In order to work reliably on QEMU and not depend on the
host CPU frequency change basic_atom configuration to use HPET.

Change-Id: I1253a0224bcbff4a7d54406b089c29b5ace32080
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
89e922243b arm: Use new SRAM and flash Kconfig options
The configuration of SRAM and flash options are no longer hardcoded in the
platform's linker script file, but are instead defined in the platform
configuration file.

Change-Id: I557a8228080d607f6add5f86b9b2509ed3fd31ce
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
741086e119 arm: Add SRAM and flash Kconfig options
Adds Kconfig options for specifying the following platform attributes:
    SRAM size
    SRAM base address
    Flash size
    Flash base address
This will allow them to be hoisted out of the platform's linker script file
in a later commit.

Change-Id: I09ba5c09d8f34eea5d787c669d77d27d4389d824
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
36e352dc2f arm: Improve Kconfig option organization
The Cortex-M related Kconfig menus and options no longer show up at the top
level when "make ARCH=arm menuconfig" is issued.  They show up under the
"General Platform Configuration" menu.

Change-Id: I6bf012e628212340f5e089d0193a9a71d90c79b9
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
916dcff7a8 arm: Move bsp/CortexM to core/cortex_m
Eliminates bsp directory as part of transforming BSPs to platforms.

Change-Id: I8b5366bf32797ddbb1bfa3520ddfeed6344cec2f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
0167aa16fa arm: Fix whitespace
Fixes whitespace issues found by checkpatch.

Change-Id: I0bfa6721dcf2d6c0413b4ca39d3c5ea98631b96d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Anas Nashif
c9b1b61340 cleanup: remove unused CONFIG_TICKLESS_IDLE_UNSUPPORTED
Change-Id: Iedb179a244f66cf403243d5d6eca020293397295
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
fee3e3c308 basic_atom: update default SYS_CLOCK_HW_CYCLES_PER_SEC
The basic_atom uses the LOAPIC timer, which means that the proper value for
SYS_CLOCK_HW_CYCLES_PER_SEC is dependent upon the hardware.  Although the
proper value for the atom_n28xx hardware is 150000000, that value does not
necessarily play well with QEMU and the host development platform as it has
been observed on many development boxes to result in a real tick frequency
that is too high.

It is recognized that the developer's host platform can not be controlled for
and that the new value of 900000000 will not be ideal for all systems. Pending
further feedback, it should be an improvement over the previous.

Change-Id: Ibe4e1ad91d3b3ae090893ff3dc855b4343972e24
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
d2857404f5 Kconfig: fix SYS_CLOCK_HW_CYCLES_PER_SEC dependencies
Fixes the SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option dependencies such that
it can be overridden by a modified platform configuration file.  This is
particularly important for the LOAPIC timer driver as
SYS_CLOCK_HW_CYCLES_PER_SEC is dependent upon the target's CPU/bus frequency.

Change-Id: I0fb49b4c540888cb1988c76e2a711a85e756f82c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:42 -05:00
Peter Mitsis
96726f0a58 x86: Move source files from arch/x86/ to arch/x86/core/
Moves the source files from arch/x86/ to arch/x86/core/ as part of transforming
BSPs to platforms.

Change-Id: I0ef6622762cda8ce201944fd87f2ee8f73e3e511
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
e611fbd811 Fix typo: specifc -> specific
Change-Id: I7677253567a5fb0ee087112647a49368e037c1a9
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
83b83b5317 Fix typo: accomodate -> accommodate
Change-Id: I64d45055baf3f2b742585984f05f94f1af0ed9c9
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
f297068949 Fix line length warning flagged by checkpatch
Change-Id: Ia3eab1b2cf359985e1f9db1514c5dbf7e74f6012
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
d8a5c03404 Kconfig: Update timer driver dependencies
Updates the timer driver dependencies to simplify the selection of a timer
driver.  The timer driver menu only lists those drivers that are compatible
with the previously selected interrupt controller.

Change-Id: I5deea315f7c373c6660bacc411c6374e7b0ae84d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
dff49566e0 Kconfig: Update CONFIG_IOAPIC dependencies
Selection of the IOAPIC requires that the LOAPIC be previously selected.

Change-Id: I13d95d4bb4ff02c1aebb0b5e573cb2b89dbe530b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
61f0ce44c7 Kconfig: Remove option LOAPIC_TIMER_FREQ
The LOAPIC_TIMER_FREQ Kconfig option is not used.

Change-Id: I919fd2128f667e0b91467cb542041449738dd992
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:41 -05:00
Anas Nashif
6b9577d2f5 fix white space issues
Change-Id: I8def24a7928121def14d6ff3f8e1f05c6fb1bad6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:41 -05:00
Anas Nashif
abeaeacab0 Kconfig: TICKLESS_IDLE_UNSUPPORTED is not used
Change-Id: Id6767a0d6b04eea6b76065d4792245b57fb0a657
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:41 -05:00
Anas Nashif
274cc72aee replace negative CMOV_UNSUPPORTED with CMOV
Change-Id: Id2aba9402495d99176eb499b1c74f86349e1164b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:41 -05:00
Anas Nashif
09821973ca Add missing includes for ARC
include nanokernel.h and misc/util.h

Those are needed after the restructuring and changes done
to public APIs.

Change-Id: Icbb1d182419e793afe7a74b14af1f31180967f39
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:41 -05:00
Peter Mitsis
2871ca32d3 Rename x86 platforms
Changes the the names of the x86 platforms so that they are more generic.
  generic_pc -> ia32
  quark -> ia32_pci

NOTE: it is expected that the two platforms will eventually be merged into one.
one. At present, the two platforms support different hardware.  For example,
the ia32 supports bluetooth whereas the ia32_pci does not, and the ia32_pci
supports both PCI and HPET whereas the ia32 does not.

Change-Id: I8a980aaef55be8c59f7d19ddeb7fafbf11253408
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:39 -05:00
Peter Mitsis
213db12fbf Move platforms to new arch/<arch>/platforms directory
Change-Id: I9ad5d51329d381c091aa47b482a8e38e7c194118
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:39 -05:00
Peter Mitsis
3019daba6a Cosmetic: Fix issues found by checkpatch
Change-Id: I6beb9ca93a98784d456740d76737996b50a65a71
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:39 -05:00
Peter Mitsis
9d63adf3ea Renames supported platform configurations
Renames supported platform configurations to conform to new platform
configuration naming scheme.

Example usage with PLATFORM_CONFIG:
    make PLATFORM_CONFIG=basic_cortex_m3
    make PLATFORM_CONFIG=basic_atom
    make PLATFORM_CONFIG=basic_minuteia
    make PLATFORM_CONFIG=galileo

  xxx_ti_lm3s6965_defconfig           -> xxx_basic_cortex_m3_defconfig
  xxx_generic_pc_atom_n28xx_defconfig -> xxx_basic_atom_defconfig
  xxx_generic_pc_minuteia_defconfig   -> xxx_basic_minuteia_defconfig
  xxx_quark_defconfig                 -> xxx_galileo_defconfig

Change-Id: I696eb8b9ad9a72d7a72efbe1341ce23500335764
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:39 -05:00
Anas Nashif
c2762f5b5b Remove unused BOOTLOADER_GRUB
This option was remove as part of linker script cleanup
a few months ago.

Change-Id: If04d69096eb3ef682d72258be90bf710ed931e69
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:38 -05:00
Anas Nashif
0e34c459db kconfig: Update defconfig files with new options
Change-Id: I393dfa270a7e6cd23171c66e298ffc46418a4a67
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:38 -05:00
Peter Mitsis
c141aaae37 arch/x86: Remove pentium4 Kconfig options
Removes CONFIG_CPU_PENTIUM4 and CONFIG_PLATFORM_PENTIUM4 as Zephyr does not
support the Pentium4.

Change-Id: Ieb1970894eda184f4c33d03e3563fb08f861ec6c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:38 -05:00
Peter Mitsis
42f8ae553f arch/x86: Remove unsupported platform configuration files
Removes the generic_pc and generic_pc_pentium4 platform configuration files
as Zephyr will not support them.

Change-Id: Iffa917d8e31702e6280eca3cbc9cdaf3f8ed9c98
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:38 -05:00
Peter Mitsis
a7644b86a5 Rename CONFIG_BSP_xxx to CONFIG_PLATFORM_xxx
Updates Kconfig option names as part of transforming BSPs to platforms.

Change-Id: If397bcac8b058e5700e82c3cabbfe64588316d1d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Peter Mitsis
07a587c8d6 arch/arm: Relocate 'bsp' Kconfig contents
As a step towards eliminating the ARM's bsp subdirectory (as has already been
done for the x86 arch), the contents of 'arch/arm/bsp/Kconfig' have been merged
into 'arch/arm/Kconfig'.

Change-Id: I813b5c9e19187347147875635deb851a3357dd55
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Peter Mitsis
4a36991e66 arch/arc: Move fatal_error.c into 'core'
One of many steps in the transform BSPs to platforms work item.  At the end
of this work item, there should not be any code in the 'arch/arc' directory.

Change-Id: If72a6a858eb4b0f1521191fca441bed4acc6d8ce
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Peter Mitsis
29092fe935 arch/x86: Move sys_fatal_error_handler.c to 'core'
One of many steps in the transforming BSPs to platforms work item.  At the end
of this work item, there should not be any code in the 'arch/x86' directory.

Change-Id: I78bf1738f4450faa078a8510ab342eb9d9277b91
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Peter Mitsis
d1955e06fb arch/arm: Move sysFatalErrorHandler.c from 'bsp' to 'core'
Moves (and renames) sysFatalErrorHandler.c out of the 'bsp' directory and
into 'core' as a step towards removing the directory 'arch/arm/bsp'.

Change-Id: Ie10aa2099f07380e4583dbbd32cdda917b4999ba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:37 -05:00
Allan Stephens
cca9dfea44 Remove references to defunct _ContextUsrEntryRtn()
This function no longer exists.

Change-Id: I8e4a41b0556e1178b96c64432147d6e1d1bfdcd0
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:37 -05:00
Dirk Brandewie
fce979ef3e init: Change _InitHardware() to be called from init system
Change the function signature of _InitHarware() function and rename
the function to a platform specific name now that it will be called
via a function pointer and not by name.

Call the platform *_init() function at PURE_INIT time.

Change-Id: I5168dfea81f406da135d491a2b4a24e8255f418a
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:37 -05:00
Anas Nashif
db404bbdf9 Do not check for DO_CONSOLE_INIT, use Kconfig variables instead
This commit removes 2 levels of checking and checks directly against
define Kconfig variables. Also reduce the code to one block and check
only once instead of twice.

This is a cosmetic change.

Change-Id: Ia427d9f15a9d09ea59d0230913168060d752ae99
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:33 -05:00
Peter Mitsis
8efb4b570b Remove config1p.mdef references from build system
Since SysGen generates the code to invoke _sys_clock_driver_init(), the build
system no longer needs anything from the config1p.mdef files.

Change-Id: Id22615ff137c9d146ccc5c3777a75b2d3bfee73a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:33 -05:00
Anas Nashif
f367f071b6 doxygen: add @brief and capitalize
Remove function name from comment and add @brief instead.
Also capitilize first letter.

Change-Id: Ib708b49bf02e5bc89b0066637a55874e659637e0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:33 -05:00
Anas Nashif
1362e3c162 doxygen: RETURNS: -> @return
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.

Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Anas Nashif
ea0d0b220c doxygen: change comment style to match javadoc
The change replaces multiple asterisks to ** at
the beginning of comments and adds a space before
the asterisks at the beginning of lines.

Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:32 -05:00
Oleg Zhurakivskyy
e5cdfc8ecc uart: Get rid of camelCase style
Change-Id: I3b0f0c3ead18416105a356794b6c79444f7e29cf
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
2016-02-05 20:14:27 -05:00
Oleg Zhurakivskyy
58dbcfd589 Expose uartGenericInfoInit()
This is helpful when working with UART through dynamic
interrupt stubs.

Change-Id: I91d64f575aa755fcfd894d678a1c078219447f16
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
2016-02-05 20:14:27 -05:00
Anas Nashif
8d879a5c32 define UART_CONSOLE_INDEX using Kconfig
Use Kconfig to define this variable and remove its
previous definitions from board.h. This will simplify
creation of different variants from a single platform.

Change-Id: I0aaa5aa81dedf096c6d8c1ea2d509c71817336d3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
d5f926fb4d Relocate Cortex-M timer driver
Moves the Cortex-M timer driver so that it resides with the other timer
drivers.

Change-Id: I3324c53356efd9f5fd88752a98e4ae301ea38d47
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
10a56b5a00 Add CORTEX_M_TIMER Kconfig option
Adds the Kconfig option for selecting the Cortex-M systick timer.  This helps
pave the way for moving the Cortex-M systick timer into the drivers/ directory.

Change-Id: Iee040083a425c9c1dbc5973991b89239e0a72eee
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
616b922841 Rename ARM systick driver
The new name indicates that the ARM systick driver is specific to the Cortex-M.

Change-Id: I43a9e5f467b83cb6050356419089d8f4da42c589
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
1b8f923595 Cosmetic: Fix whitespace
Fixes whitespace errors detected by checkpatch.pl

Change-Id: I4d0193fc282f5028c6770e4dc642dccc5f434dff
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
1ffabeaf3d Rename BSP_DIR to PLATFORM
Updates references to CONFIG_BSP_DIR to CONFIG_PLATFORM as part of the
BSP -> platform clean up.

Note that despite the renaming, the usage of the config option remains
unchanged.

Change-Id: I2846c3f761cf09871019c0855bf1824ae03e6b3c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Peter Mitsis
5d01d49058 kbuild: remove references to non-existent bsp directories
The following directories do not exist:
    $(srctree)/include/bsp
    $(srctree)/target/src/bsp

Change-Id: I27990cc404502d96e323df8b95e1ac105e6d5265
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:27 -05:00
Anas Nashif
66f83ece6e arc: make the defconfig use a nano kernel by default
On ARC the default should be nano kernel.

Change-Id: I7671fda1357abbe1fd04a74f44856dbcc26bddbf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
ac47c45ca0 Rename Zephyr OS into Zephyr Kernel
We are a kernel, not an OS.

Change-Id: Ib987e3e511e1bdbed6293ab5e15e598bff00b09b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
bde0949049 Update default configurations
also change Zephyr OS to Zephyr Kernel.
Use a script to check and update all default configurations.

Change-Id: I9614d698fd5b7c803590e83a7429403357c09a94
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
edb02f0274 kconfig: move bootloader options to misc/
More bootloader options moved to 1 single menu.

Change-Id: I6908de8e26b4a15617ad5aa738c9dc2a928ad6a4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
def4fc89c1 kconfig: move bootloader options to misc/
Repeating options per BSP should all be maintained in one
single place.

Change-Id: I45394a5230978effa8fff93ecef736ba44e382d2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
6eb30a3edb kconfig: remove MAX_PCI_DEVS, it is not being used
This options is not being used anymore. Was removed as part
of PCI driver rework.

Change-Id: I0b93e9c5e2c9425cabcd7112eb0ac49cfbb2806b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
10487575c9 kconfig: Create a menu for PCI
The options were seen in the top level menuconfig menu, gather
them under a the Bus menu. This includes the PCI option itself
and any related options.

Change-Id: Ib09e2ed0c35dca5ad1c2e086d0f4a479a847291f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
e943f69950 kconfig: move serial port options to drivers/
We had those options defined per BSP. Moving them
to a more generic place makes more sense. In this case
they are moved under serial drivers.

Change-Id: I8faf31321fc433eaa168bf36f2b590a6b8402f9e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
fc43a2bb57 arc: move files from bsp directory
Change-Id: If087cfa77bee31a97a1b959de7506ea33f8a2417
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
1371d5e25e arc: move arc NSIM to drivers/
Change-Id: I5c92ec6a49d24737367ee874280aef10fab05d79
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
f547c36df8 arc: move arc timer to drivers/
Change-Id: If4dccbf3bbe67c89b69aed1d62025bf867405d22
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
9687ed0b37 arc: add defconfig
Change-Id: I7365d7eb31254e0fc29b1a82444f4c0fd3c05f02
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
08f8b65f25 arc: move interrupt controller to drivers/
Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Anas Nashif
cfb9332c30 arc: add missing Kconfig/Makefiles to architecture
Change-Id: I99e96853e5ddc9eb0dd9ca9711921d5b57448db7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
478128cf9e Rename kernel's clock_vars.h to sys_clock.h
The revised name better reflects the fact that the file defines
macros in addition to declaring variables. In addition, most of
these APIs use the "sys_clock_" prefix, which aligns well with
the new file name.

Change-Id: Ib33517d4b19ec2455303b87200c677e87640fcbc
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
22364188a4 Rename nanokernel's offsets/common.h to nano_offsets.h
Eliminates unnecessary "offsets" subdirectory, and aligns file
name with gen_offset.h which resides in the same directory.

Change-Id: I8cea3bc54b5ceae3091d4a5c77c59ab826339f75
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
e8f50f5717 Rename nanokernel's genOffset.h to gen_offset.h
Eliminates use of non-standard camelCase file name.

Change-Id: I809de5f72b40adfd49cbc128992de934e3ec66e3
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
92c9c47265 Standardize naming of nanokernel core source files for ARM
Gets rid of "nano" prefix on these nanokernel files.

Change-Id: I78c4dd4ebbbbd91f6fdd4e54ffc82de9bd232c7d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
35cf49d479 Standardize naming of nanokernel core source files for x86
Gets rid of "nano" prefix on these nanokernel files.

Change-Id: Ib87323b14779bf3673ec2826023eb94b4b7cc81e
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
c29d41cab7 Rename nanokernel's nanok.h to nano_private.h
The new name better reflects that this file contains all private
nanokernel APIs that are used by various kernel subsystems.

Change-Id: I4c258d582e93753eec9e575fdb5f9f2109417a0f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
96d746d3c1 Rename microkernel's minik.h to micro_private.h
The new name better reflects that this file contains all private
microkernel APIs that are used by various kernel subsystems.

Change-Id: I5e52172a9e33aa130ce55ce59e887bba5c1c175a
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Allan Stephens
7da1dd860b Rename microkernel's kernel_struct.h to micro_private_types.h
The new name better reflects that this file contains private
microkernel APIs (types, structs, etc.) that are used by various
kernel subsystems.

Change-Id: I7a89be893455b3daaf30baa40a0ec8e0cde7cc36
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:26 -05:00
Dmitriy Korovkin
8d065343c2 Use static interrupt registration in device drivers
Make device drivers use static interrupt registration procedure.

DYNAMIC_INT_STUBS configuration parameter was used only by device
drivers to switch between static and dynamic interrupt registration
procedures. Now it is obsolete and is removed.

uart_int_connect() function is removed. If UART device driver still
needs to register interrupt dynamically, it should use
irq_connect(uart_irq_get()).

Change-Id: I80c695f337456e9b0c1b0fd56716e35794f7bdb7
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:25 -05:00
Dmitriy Korovkin
660878e4e2 irq_connect for x86 uses static stub array
In order to provide the same irq_connect() on all platforms
on x86, irq_connect() now uses a static array of interrupt
stubs. Device driver does not need to provide interrupt stub
to irq_connect() function.

Add NUM_DYNAMIC_STUBS configuration parameter, the number
of interrupt stubs used for dynamic interrupt registration.

Modify tests for unified interrupt register API

Tests that deal with interrupts are modified to work
with the new interrupt registration API.

Add CONFIG_NUM_DYNAMIC_STUBS option to dynamic interrupt projects

Projects that use dynamic interrupt handler registration on x86
have to include CONFIG_NUM_DYNAMIC_STUBS parameter in the
configuration.

Change-Id: Ic90c726485521a57cf695fd3edc8cac85d0b827d
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:25 -05:00
Dmitriy Korovkin
f661feee55 IRQ_CONNECT_STATIC implementation for ARM platform
IRQ_CONNECT_STATIC() macro provides static interrupt registration.
It creates an entry for _sw_isr_table, table of interrupt handlers.

IRQ_CONFIG() macro provides interrupt controller configuration.
On ARM platform it configures the priority of each interrupt.

_sw_isr_table is implemented the way that each of it's elements
is located in individual section. Sections are marked a "linkonce",
thus when a device driver declares an interrupt handler, it overwrites
the default _sw_isr_table entry.

Change-Id: I182bf7158dd67f45b597783dca038a4f78166a03
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:25 -05:00
Dmitriy Korovkin
6dd108a263 IRQ_CONNECT_STATIC implementation for x86 platform
In order to simplify x86 interrupt stub creation, each interrupt
controller implements an interrupt stub definition macro.

Add IRQ_CONNECT_STATIC() for static interrupt registration, and
construct the interrupt stubs name from device and interrupt
handler names.

Add IRQ_CONFIG() macro for the interrupt controller configuration.
On x86 platform it programs APIC to associate an IRQ number with
the interupt vector.

Add HPET_TIMER0_INT_PRI parameter to Quark platform header to
make it build correctly.

Change-Id: I24ad25e1aa807ffa63733a27ad882877fcad72af
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
8601dc9488 Break forced selection of CPU_CORTEX_M3
Makes the ARM CPU type a choice between CPU_CORTEX_M3 and CPU_CORTEX_M4
(similar to the choice of processor for x86). This completes the breaking
of the forced selection of CPU_CORTEX_M3 when CPU_CORTEX_M4 chosen, thereby
making CPU_CORTEX_M3_M4 the true umbrella option for the Cortex M3/M4
processors.

Change-Id: I1d1f39352d85a5848b13102ceb8365c7dede0959
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
25fd37d9d5 Rename option CPU_CORTEXM to CPU_CORTEX_M
Makes name more consistent with other CPU_CORTEX_M* options.

Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
3e6c31207b Rename option CPU_CORTEXM4 to CPU_CORTEX_M4
Makes name more consistent with CPU_CORTEX_M3_M4 option.

Change-Id: I6f0a14322b7774df54a3459f91cd3acf07819b04
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
a9941af3ee Rename option CPU_CORTEXM3 to CPU_CORTEX_M3
Makes name more consistent with CPU_CORTEX_M3_M4 option.

Change-Id: I0b89a50a5c0b728167cd76219d25ddf98243c0dd
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
9bf659afa5 Introduce CPU_CORTEX_M3_M4 option
CPU_CORTEX_M3_M4 replaces CPU_CORTEXM3 as the umbrella option for Cortex M3/M4
processors.

NOTE: Selecting CPU_CORTEXM4 still currently forces the selection of
CPU_CORTEXM3.  Breaking that forced select will be done in a later commit.

Change-Id: I0f36b3a2adc5c6c66db4e9b6353b921199544deb
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
30a49f8d4a Set Quark as default x86 platform
Quark is the preferred target platform for the x86 architecture.

Change-Id: I2bf9bf209a85c93e38ea554e19de3f32813c3a69
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Peter Mitsis
4aac2a5280 Introduce CPU_ATOM for x86
Atom based BSPs now select an atom processor.

Change-Id: Iebe90a60d9e7f2025ce6b23fe918b86cd11fdea7
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:25 -05:00
Benjamin Walsh
6bed1bd9d4 arm: fix RUNTIME_NMI failures
The type of the handler variable was missing, causing compile failures.

Change-Id: I33c0f8d2893de0c6ad14f33ecb03b106c87cf758
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:14:22 -05:00
Anas Nashif
bfd2d5f4cc x86: cleanup x86 bsp directory
Some files were left in bsp/ after a failed rebase.

Change-Id: I26d34387d751ddd831b2dfef5c8cb6a1a8904b3c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:22 -05:00
Benjamin Walsh
2672025969 nanokernel: add and initialize timeout fields in ccs/s_NANO
s_NANO contains the timeout queue, and each ccs needs a struct
_nano_timeout object that gets linked in the nanokernel timeout queue.

Change-Id: Iad027eaaebcffe190e95f0b9d068f047062559c2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:14:22 -05:00
Benjamin Walsh
f9d34ff899 nanokernel: rename struct s_CCS to struct ccs
Follow coding conventions.

Change-Id: Ie398d66e6255b76b4546aa9c827997b5dfb0743c
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:14:22 -05:00
Anas Nashif
9485729b3a Rename *.s files to *.S
Change-Id: I706a06e287f9e8e52c1cee4863c36673b21762f7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
b33e1eccf1 x86: Remove arch/x86/bsp directory
After moving the driver code out of the bsp directory all the code
that remains is common to all x86 platforms move the code and
assocoated config variables to arch/x86.

Change-Id: I76617070bb165fd157f0c3a127f1b9829b86c283
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
02ef939831 x86/bsp: move timestamp "random" driver to drivers/random
Change-Id: I7a7e7627f1ef60c652c15ad482a4f84f00d79c44
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
11edf422b4 x86/bsp: move local apic timer driver to drivers/timer
Change-Id: I74f7297d21f3acf4a457ca335162602b35f4f6c1
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
73d74a5abb x86/bsp: move hpet driver to drivers/timer
Change-Id: I63c361a586d2fd8c03674febd58bc1dfd2658fdc
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
09d2770377 x86/bsp: move io apic driver to drivers/interrupt_controller
Change-Id: I00f400e0405f526dd17cf22c703fab4a4968fce0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
124a27f210 x86/bsp: move local apic driver to drivers/interrupt_controller
Change-Id: I69350493c3b94d754f89fb37eaebe50a8076384b
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:21 -05:00
Dirk Brandewie
526e132eb1 x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller
Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2016-02-05 20:14:20 -05:00
Juan Manuel Cruz
308f1586d6 Kbuild: Assembly code extension.
This commit set back .S as the assembly code extension for Kbuild.

Change-Id: Ib0119876bd0bed6617bbfbad2ca6a44e172ab042
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:20 -05:00
Anas Nashif
5005986d06 Update default configs
- Use Zephyr OS instead of Tiny Mountain
- Update with latest config options and values

Change-Id: I64084c37ce28b25587462468de86e4a904749433
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:20 -05:00
Allan Stephens
893726ccb6 Eliminate duplicate registration of system tick event handler
Since the system generator pre-registers K_ticker as the handler
for the system tick event, there is no need for the timer driver
to re-register it at run time.

Change-Id: I7f20c19e5c6ccc7dfb6117aa2d2647b9dec0e549
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:19 -05:00
Anas Nashif
274622ea69 Rename VXMICRO_ARCH_arm -> CONFIG_ARM
Change-Id: I32b2e39781825504e7936b3df0c864988650c35c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Anas Nashif
191fc279ce Rename VXMICRO_ARCH_x86 -> CONFIG_X86_32
Change-Id: Ie1bcfebce1db838ea994cb3626396ea032225830
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Szymon Janc
6d27b0a33c Add simple UART driver
This driver is a very simple UART driver that can be used to implement
a protocol in application. It has no protocol logic and just allow
application to receive and send data over UART in platform independent
manner.

API is designed to minimize number of required memory copies.
Application is able to provide new buffer every time it decides to
consume received data. It is also able to just alter offset and
reuse current buffer eg if data was corrupted or otherwise invalid.

Change-Id: I8d3827fe2e242196e986d0419bc5487357481558
Signed-off-by: Szymon Janc <szymon.janc@tieto.com>
2016-02-05 20:14:16 -05:00
Allan Stephens
815c6406bc Rename VPF files to use MDEF file extension
The file extension indicates a "Microkernel DEFinitions" file,
and no longer reflects the obsolete VxMicro/Viper branding.

Change-Id: Ib95b271404a4a4737e851d603c371244fa609e4d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
5189844df5 Eliminate VxMicro branding in kernel code
Eliminates references to the obsolete OS name. In most cases the
name is simply removed, as it isn't necessary.

Change-Id: I32f9e7390e436aec008a9454b72657e129d65152
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
ec2d3fb6de Eliminate Viper branding
Gets rid of references to the obsolete OS name. (Note that removing
the build system comment entirely makes sense, since there are no
other comments for anything else in the file.)

Change-Id: I4473b016c1c85be48ac9ab8d5b8f6a5b11dd58d0
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Johan Hedberg
24c44026db atomic: Add const declaration to atomic_get
The atomic_get() function is a read-only API which doesn't modify the
value given to it. The input parameter should therefore be declared as
const.

Change-Id: I084b7beb623610412f9237fc9dae6139580e2636
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
f5777f87bc Continue consolidation of arch-independent private nanokernel APIs
Eliminates duplication of these entries by the various architecture-
specific include files for private nanokernel APIs.

Change-Id: I711c3b42fe375d1574ce4a540142c3b507b71557
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
bff7fc17fe Begin consolidation of arch-independent private nanokernel APIs
Introduces nano_internal.h, which will declare all architecture-
independent non-public nanokernel APIs. This file is automatically
incorporated by the various architecture-specific include files
for non-public nanokernel APIs, and will not normally be included
directly by any other files.

Change-Id: I9f3de812a5747cc720fa0ff739007315e8d07dd9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
69555e8efd Cleanup of nanokernel's fiber scheduling routine
1) Renames routine to conform to kernel naming conventions.
2) Relocates routine declaration to include files for
   non-public nanokernel APIs.
3) Relocates routine definition so that it resides with the
   nanokernel's other fiber manipulation routines.
4) Eliminates an unnecessary argument to the routine.

Change-Id: Ia139280dfea36262ca8417708786b4989f3eaee1
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
0c3fd0afc2 Relocate declarations of _nano_fiber_swap()
These now appear in the files which declare other non-public
nanokernel APIs.

Change-Id: Iea01d6de44851a08b308004b2c3104c08b020970
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:15 -05:00
Allan Stephens
bb9ab0322e Eliminate unnecessary references to cpu.h and cputype.h
Gets rid of places where there is no need to include these files
at all, or places where these files are being indirectly included
due to the inclusion of nanokernel.h.

Change-Id: I7b58148af454b977830c00a6b519a78d0595603b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:14 -05:00
Juan Manuel Cruz
64fd17d96a Kconfig default configurations update.
This commit add the symbols CONFIG_RANDOM_GENERATOR
to the default configurations.

Change-Id: Iff0e5a7d144993bf1cc9967bcffff037333cdf30
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:14 -05:00
Allan Stephens
a1bd59de35 Eliminate obsolete coding convention comments
Gets rid of single-line comments required by a previous set of
coding conventions. These comments provide no value to readers
and just clutter things up.

Change-Id: I2a08b12cf5026253de56979efdfc510e7e68defe
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:14 -05:00
Allan Stephens
60f6a74efe Eliminate non-standard NULL definitions
Revises kernel so that it uses the standard NULL symbol defined
for C99, rather than having its own custom symbol.

Change-Id: I74342f192e95899a83db879e8b1c8fe89ac8b92d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:14 -05:00
Peter Mitsis
6232a85059 Fix closing CONFIG_MICROKERNEL block comments
Closing comments to two CONFIG_MICROKERNEL ifdef blocks incorrectly identified
the ifdef block as NOT belonging to the microkernel.

Change-Id: Iee415e33d7f8a88c41009c5783b37da3a431461b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:14 -05:00
Peter Mitsis
4fe98a46f5 Initialize stack area in _NewContext()
Instead of initializing the stack (when INIT_STACKS is enabled) in start_task()
and _fiber_start(), do it in _NewContext().  This helps to both reduce code
duplication AND ensure that all contexts get an initialized stack (previously
the background/idle task's was missed).

Change-Id: If2d50309d2be48fac937f5d0ae96b9de185c0fe2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:14 -05:00
Juan Manuel Cruz
6ec8b8cdd5 Kbuild: Set XIP as default for CortexM.
This commit sets Execute in Place (XIP) option
as a default for CortexM architectures.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: Ib9bd361a9ac6c64d9755c6bf3ac5c8df6c1b22f2
2016-02-05 20:14:14 -05:00
Anas Nashif
aae59d0b62 Use a simpler form for including BSP headers
Change-Id: I44427225658e90b64dbc0881e4effc1debafeda6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:14 -05:00
Anas Nashif
bbe84f8ae5 Use ccflags-y and asflags-y instead of EXTRA_CFLAGS
According to section 3.7 of Documentation/kbuild/makefiles.txt, using
EXTRA_CFLAGS in Makefiles is "still supported but their usage is
deprecated." However, using make EXTRA_CFLAGS="-DSOMETHING" results in
EXTRA_CFLAGS from Makefiles being overwritten, obviously breaking the
build.  This patch converts to them to the newer ccflags-y which also
fixes the problem.

Change-Id: I6309439599d4c9cc184f9ecd941bde841982ef07
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:14 -05:00
Peter Mitsis
40b5200c73 Optimizations to _NewContext() and _NewContextInternal()
Since the address of the new context is known before _NewContext() is invoked
(due to it being passed a properly aligned stack), there is no longer any
need for _NewContext to return the pointer to the context.

Furthermore, as a direct result of the properly aligned stack, the pointer to
the new context does not need to be passed as a separate parameter since it
will always match the passed stack pointer.

Change-Id: Ie57a9c4ad17f6f13e8b3f659cd701d4f8950ea97
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
a45f691d12 Remove runtime stack alignment from _NewContext()
Runtime alignment of a context's stack is no longer necessary in _NewContext()
as the memory is aligned (via the __stack tag) before calling _NewContext().

Change-Id: I31b7fd883ea3f1dcdb378e8ff508430bc75afcde
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
ad74658009 Add __stack tag for aligning task/fiber stacks
The "__stack" tag is to be used to align an array (to STACK_ALIGN) for stack
use by either a fiber or task.

Change-Id: I5828f3ee1b09b0b5ba894ea30689d179de347494
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
db8a41c90d Replace use of __attribute__((packed)) with __packed
The __attribute__ keyword is toolchain specific.

Change-Id: Ia3c0ff54d778785679c864704f8db6a3ba898948
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
bcfc0a8415 Replace PACK_STRUCT with __packed in kernel code
The PACK_STRUCT macro is being phased out in favor of using __packed.

Change-Id: I4f231ce99d104377436d14c5a8fa3eb0c6513b35
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
ad39ee1c96 Replace __attribute__((aligned(x))) with __aligned(x)
The __attribute__ keyword is toolchain specific.

Change-Id: I2183d154ccdb9b5bed3bc245cc37cbf4c5cc62cc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
5c892eeccc Remove references to user mode tasks
User mode tasks are not supported.

Change-Id: I414e0957431b7a1df7b34cf438597dfab72b5a0f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
86c817ab60 Remove references to _NewContextUsr()
The routine _NewContextUsr() does not exist.

Change-Id: Ia20ddd3c9066930bd94e02850880a2f777081e82
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
19a0ee4d24 Rename missed instances of nanoFiberStart()
Completes the renaming of nanoFiberStart() -> fiber_fiber_start().

There is little value in listing the callers of _NewContext() in its function
header.  Not only was the (deleted) list both incomplete and wrong, keeping
it around and properly updated requires error prone maintenance.

Change-Id: Ic45f51b285c027a2e8be331c0d28c16bdc97647d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
86ebbf406c Remove comment listing callers of _NewContext()
There is little value in listing the callers of _NewContext() in its function
header.  Not only was the (deleted) list both incomplete and wrong, keeping
it around and properly updated requires error prone maintenance.

Change-Id: Iec069847762fdef6b6b2f54ad23c69ab3fa6e592
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
07c45d9e75 Cosmetic: Fix whitespace for checkpatch
Checkpatch generates an error if any spaces follow the '*' when declaring
pointers.

Change-Id: If8fc4b185c5c508eadc78bcc9fa7a5050ccbdad4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Peter Mitsis
7d2fc8ec22 Add _NANO_ERR_ALLOCATION_FAIL fatal error code
This reason code will be used indicate that the kernel failed to allocate a
critical resource (such as a command packet or a timer packet).

Change-Id: I6d4c3d96fc70b2b8cab4027b1b8e4febf4d6c474
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:13 -05:00
Allan Stephens
d216a00adc Clean up private APIs that mark context as (non)essential
1) Renames APIs to align them with conventions used by other
   general-context nanokernel APIs.

2) Relocates implementation of these APIs to the architecture-
   independent portion of the nanokernel.

Change-Id: I1aa60029aaa96697cd8fcb594bbae23ba6656661
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:13 -05:00
Allan Stephens
63720a9af3 Eliminate secure string error handling
This is not required since the secure string library routines
have been removed.

Change-Id: I284a21e4167d9bb6f78354d809c563a4c52f619c
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:12 -05:00
Dan Kalowsky
c02dd34277 Renaming include/nanokernel to include/arch
Renaming the directory include/nanokernel to be include/arch, which
better reflects the real nature of the directory and the contents
inside.

Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:14:12 -05:00
Dan Kalowsky
40e7780e65 Renaming CONFIGURE_UART_PORT macro
Renaming the CONFIGRUE_UART_PORT macro to UART_PORT_CONFIGURE.
Done to better align with the current naming process, but also to
remove some possible confusion over the macros source now that
the tree has moved over to Kconfig/Kbuild options.

Change-Id: I1a7691d09818c3d529de346e7fa347ce5ac19aed
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:14:12 -05:00
Dmitriy Korovkin
ec8a461bfb Introduce public APIs for random number generation
Convert the existing non-public random number generation APIs
into public APIs (i.e. sys_rand32_init and sys_rand32_get).

Change-Id: Id93e81e351a66d02c08cf3f5d2dd54a3b4b213c5
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:12 -05:00
Dmitriy Korovkin
27bcb431cb Random number generator driver unification
Remove ARM specific driver that duplicates the platform
independent one.

Rename x86 specific driver to make it unique.

Added configuration options for random and non-random
number generators.

Change-Id: Ie1b277d2927cdfe877650ae09134db7c86becb76
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:12 -05:00
Dmitriy Korovkin
6313939f8d Remove CUSTOM_RANDOM_GENERATOR from atom_n28xx platfotm
The BSP does not have hardware random number generator
device driver.

Change-Id: Icaf4726174ec5c9120db4bd90d2ea2a4a30a8837
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:12 -05:00
Andrei Emeltchenko
5831c25d93 serial_console: Use dynamic irq connect
Follow common practice and use standard dynamic irq connect mechanism.

Change-Id: Ibb29858da77909ede1fe2dacb056274e49687473
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:14:12 -05:00
Szymon Janc
4aff07c4e0 arm/timer: Include headers based on selected BSP
Board specific headers should be included conditionally based
on the selected BSP.

Change-Id: Ia8c32c56e94670f4c59f7acac28557dd178e44f1
Signed-off-by: Szymon Janc <szymon.janc@tieto.com>
2016-02-05 20:14:12 -05:00
Dmitriy Korovkin
a91736ab9a Convert PCI_DEBUG parameter to a configuration parameter
Change-Id: Ie0272b52bbba56e3381cf33fded873aaa0709af6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:11 -05:00
Dmitriy Korovkin
4187747e4d List PCI devices after console initialized.
In order to display PCI devices, make sure console is initialized
and list all the devices.

Change-Id: Ia7f47e58cee1a0da0ee1f86d9229a3e23e7a0dbb
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:11 -05:00
Dmitriy Korovkin
c3c75902fe Fix UART on Quark platform
UART on Quark platfor, according to Quark BSP Programmer's
Reference Manual, is located in the following order on PCI bus:
COM2 BAR0: 16550 registers
     BAR1: DMA registers
COM1 BAR0: 16550 registers
     BAR1: DMA registers

So, the driver on Quark platform has to specify BAR (Base
Address Registers) number, the pci_bus_scan() function looks for.

As long as UART is a concole device, calling pci_show() during
it's initialization does not make any output.

Change-Id: I2261fbcc8f9e3ebc22d5307fdcbb18cb649c1224
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
94c6f058c5 Update defconfigs for all variants
Change-Id: I44704fd93112e6cbca111f4b2c9949ff0bf0c521
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
f1bad47cd7 Kconfig: update ARM BSP configs
Change-Id: Id0a09e5ca7049504b118bbd34129347ff31b839d

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
615b6debd2 Kconfig: update arm defconfig
Change-Id: Ie99fbabef905c18ab7d8ce88a7bf7ba910384dbf

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
2e67281420 Fix CONFIG_NUM_IRQS for arm
Change-Id: I46184b36ad9f7d436fd2c2736d08ab4fdcae373d

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
3446d62412 Kconfig: use correct serial driver for arm
Change-Id: Ic06eb63af3c2247371cacab1077b6ddd4a739c35

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
5282665b3c Update arch defconfig for ARM
Change-Id: Ic0d3794b4c00504bd2386fbb20b05a844de2d8e7

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
dd3e676fdb Update defconfigs for ARM
Change-Id: I6189947283476e56e082a820b812d0b3689cc484

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
4a6a236f23 Kconfig: update quark defconfig
Change-Id: I68ab854d052b080019312d8988bdc8dc94a0ea74
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
1b3bdc414f Kconfig: make processors a choice
Change-Id: Ica78b4c20e506a9c17780cb44f81b481d14317ab

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
fcc1c1e113 changed defconfig for generic_pc and x86
Change-Id: I65cc5b6fa1471e8441f3826e324dfb29783bb812
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
fff0c84caf Kconfig: make arm kconfig independent
Change-Id: Ib5d6253396162f33d1135cb3529319167f7ecd4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
745c2b66fd Remove sourcing of arch kconfig to root
Change-Id: I052721288a58ae27c49b59f8e42bdab469f3b2f3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
3ae5d713ef Kconfig: make architecture kconfig independent
Change-Id: I242cb49d11a8131054730059a07154031e0035dd

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:11 -05:00
Anas Nashif
1339edc104 remove defs.objs file
Replaced by kbuild

Change-Id: I61a21ed164b02c7770a181919b35ffafbde4f49e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:10 -05:00
Anas Nashif
382194906d pci: add PCI config option
Change-Id: I5c6cedf696d4acaf32b8d9832b0593730223b41e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:10 -05:00
Anas Nashif
f4f5cc138c Kbuild: include files dynamically based on BSP_DIR
Change-Id: If36a03acb633c772d599ae1492ebabf04c432306
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
2a4f8741ab Kconfig: Fix for PIC and LOAPIC/IOAPIC dependency.
This commit fixes the dependency between PIC and LOAPIC/IOAPIC
configuration symbols.

Change-Id: I476961dc904bca286267ccd3bd5c0cbe23430fed
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
0423e2d99d Kconfig: Fix empty Boot Sequence configuration menu.
This commit fixes an empty "Boot Sequence" configuratio menu.
The menu has a dependency against the PROT_MODE_SWITCH_PROMPT
ksymbol.

Change-Id: I57cb9d01a6512d6a5a1b66701d1be310c2af8da6
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
e69f4dcf79 Kconfig: Fix for x86 kconfig typo.
This commit fixes the "randmon" typo in the
x86 Kconfig file.

Change-Id: Ic88a4e971dc2e21b9885d591ad6949aebed6b48d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
e1bb46881a Kconfig: Fix to floating point blank page.
This commit fixes an error when the floating point menu shows a
blank page.
This menu has a dependency against the FLOAT option selection
and the ENHANCED_SECURITY option selection.

Change-Id: Ib9f558f386b9a9883d4aa393e3cb913d187b5ce9
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
cc438c208e Kbuild: Fix for Kconfig menu typo.
This commit fixes a simple Kconfig menu typing error.

Change-Id: I470be613d24a51aefa477cdbebfeb35ee3ec5bc8
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
d15251fec5 Kbuild: Kconfig license headers.
This commit add license headers to Kconfig files.

Change-Id: I79e60263b8c7b696463ecc84b8ad411af5415117
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:10 -05:00
Juan Manuel Cruz
e65cec5c75 Kbuild: Additional default configuration for x86.
This commit adds specific default configuration for various
x86 processors:
 - microkernel/nanokernel atom
 - microkernel/nanokernel minute ia
 - microkernel/nanokernel pentium 4

Change-Id: Iafa0eb29a1ee2e3b467dfe1e1f9ddb587200101e
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:09 -05:00
Anas Nashif
b18ebe3bd6 ARM: update defconfig for arm
Change-Id: I70c44e9e4cb0aaa22298eada120ed4b4e47a32b7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:09 -05:00
Anas Nashif
527aca9f73 X86: Update defconfig
Change-Id: If3ab286899c3b40e34f420c747bcaa49ccdfe008

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:09 -05:00
Anas Nashif
6b84a49a48 Kconfig: fix NUM_IRQS value
Change-Id: Ied0cf8862cd6a9ab998a22d23e59068f114bbff6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:09 -05:00
Anas Nashif
c6ccdb7b3d CONFIG_TICKLESS_KERNEL -> CONFIG_SYS_CLOCK_EXISTS
Change-Id: I84991965ddc741b07def5f584ae6e19b9583eba2

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:09 -05:00
Anas Nashif
d2ca03270e Kbuild: Fix sanity checks for quark
Change-Id: Id142f337f715590fa63d9f7b957f51c203743566
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:08 -05:00
Juan Manuel Cruz
638fb2c181 Kbuild: Bluetooth driver support.
This commit adds the Makefile and Kconfig files
to support the bluetooth driver in the Kbuild system.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I1f72b13aca8fb098eece04c4f0e1b680639b520f
2016-02-05 20:14:08 -05:00
Anas Nashif
5a446171ac Kbuild: building nmi is not conditional
We need to always build nmi.c for ARM, this should not
be conditional on RUNTIME_NMI.

Change-Id: I27c0cb07b3f63eddd2141d07cb988548ef0050ec
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:07 -05:00
Anas Nashif
805a0edaff Kbuild: remove obsolete directory from CFLAGS
$(srctree)/kernel/common/bsp does not exist anymore,
remove it from CFLAGS

Change-Id: I948ed9aa97469498a803916060935deb7a1a0271
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:07 -05:00
Anas Nashif
4acde800b0 Kbuild: User kernel instead of TiMo
TiMo is very ambigous, be generic and call it kernel.

Change-Id: I66b3e436afbc89e874f31a89b98cc04aa821c787
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:07 -05:00
Anas Nashif
00fb07d361 Kbuild: fix building of task_abort for arm
Change-Id: I25d93da95f2a9e93c7041f22303499c1109c5266

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:07 -05:00
Juan Manuel Cruz
a25a5f76af Kconfig: Update on arch x86 Kconfig symbols.
This commit add the Kconfig symbol SSE_FP_MATH.

Change-Id: I565a5a4665edbe72b40eb1e48a3279af98523034
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:07 -05:00
Juan Manuel Cruz
5a9d51850d Kbuild. Fix for timer hpet build on quark BSP.
This commit fixes the include path for the hpet timer build
for quark BSP.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I38345e1ec46e3c3684e1f5ecded8114ad58b5443
2016-02-05 20:14:06 -05:00
Anas Nashif
4ed8df8c5a Update defconfig for x86
Change-Id: I482859501de28c115e25f8cb36a7b31b044f82d8

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:06 -05:00
Anas Nashif
afbc7026ea Update defconfig for ARM
Change-Id: I9fd8358f895edc7ae3040d1c131891f64f6929a1

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:06 -05:00
Juan Manuel Cruz
35591e5c07 Kbuild: Update on defconfig arm files.
This commit update the defconfig files for the arm
architecture with additional Kconfig symbols.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: Ib9bbde65ae333387cebf63949b7a2e9275489f35
2016-02-05 20:14:06 -05:00
Juan Manuel Cruz
027163c3f8 Kbuild: Update on defconfig x86 files.
This commit update the defconfig files for the x86
architecture with additional Kconfig symbols.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: Iacf0a47f832b7e8ed688f74276d94b4a2a9da3f8
2016-02-05 20:14:06 -05:00
Juan Manuel Cruz
b25405283f Kbuild: CPU_MIGHT_SUPPORT_CLFLUSH ksymbol is hidden.
This commit sets the default value to n and hides the edition
of the Kconfig symbol CPU_MIGHT_SUPPORT_CLFLUSH.
This symbols is not used at the moment in the original build system
nor Kbuild.
We preserve the symbol if needed for a future use.

Change-Id: I0b1d0413cc479e27cea0e9f04929b1792d6e3200
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:06 -05:00
Juan Manuel Cruz
95d71c50c4 Kbuild: New default x86 standard BSP.
This commit adds the pentium BSP as the new x86 standard BSP
at the configuration menu.

Change-Id: I8bc337df90fe527a557f68a3712f5d3d00837081
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
721b9df9d1 Kbuild: Fix board.h include issue on pentium BSP.
This commit fixes an issue with the inclusion path for the
board.h file for the pentium BSP.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I28172f8071b907aa61660ec8b8009e83cb2aa5ea
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
4ca3a4a515 Kbuild: Adaptation to the location change of driver headers.
This commit adaptes the Kbuild system to the change of location of
the header files for drivers.
Old location: driver/
New location: include/driver/

Change-Id: Ic49d373149ee44d781419c5c68e59408c8ef1c11
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
622e273d08 Kbuild: Sysgen support for NUM_TASK_PRIORITIES
This commit add support to the Kbuild system for the
NUM_TASK_PRIORITIES Kconfig symbol and the corresponding sysgen
parameter.

Change-Id: I6b035437c86d62f72c25d696d18182a7b0448e8f
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
808e5c4ba0 Fixes to Kbuild to build on ARM architecture.
This commit fixes issues to allow build on ARM architecture.
- It fixes the include paths in Makefiles.
- It fixes the include path for the offsets.c compilation.
- It fixes the linker command. This changes is needed because gcc
  ARM cross-compiler does not accept an AT() command without
  specifing an address explicitly. This corner case appears
  on ARM architectures when XIP is disabled.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: Ief8b53c4cc154abba7b7827121ec5a56f62b7b26
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
2e3e28c3ed Kconfig KERNEL_DIR symbol removal.
This commit removes the Kconfig symbol KERNEL_DIR.
The symbols was no longer needed because sysgen is only
used on microkernel architectures and the value of
KERNEL_DIR is always "ukernel", therefore it is redundant.

Change-Id: I5e38dd431c5b6f7586e8b25aea330632e96f581f
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
73c4417ac9 Kbuild defconfig files.
This commit adds the defconfig files that define the standard
configurations for x86 and arm architecture and the standard
configurations for the following BSPs for microkernel and
nanokernel:

- x86 generic pc
- x86 quark
- arm fsl_frdm_k64f
- arm ti_lm3s6965

They can be applied using the make target defconfig.
This target will generate the corresponding .config
file that will be consumed by the build system.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I128ad52f792eeb61cc80578be5fc3bd427447aaa
2016-02-05 20:14:05 -05:00
Juan Manuel Cruz
1c233a0377 Creation of Makefiles for arch directory.
This commit creates all the Makefiles that describe the object-
bundles for the arch directory and  every sub-directory below.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: Icb4ebcfc430a132e514507149ad5ab6878eeed64
2016-02-05 20:14:04 -05:00
Juan Manuel Cruz
132649f2cc Kconfig symbols for arch directory.
This commit adds the Kconfig files that describe the CONFIG
    symbols that belongs to the arch directory and subdirectories.

Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Change-Id: I744225ddaa5e2b45113ca049457a8f9925ebe4c2
2016-02-05 20:14:04 -05:00
Tomasz Bursztyka
ea4c3d1c0f bluetooth: UART based driver no longer needs to set regs and irq
Now that UART drivers are configured internally when it comes to
hardware specific information such as IRQ and registers (or mmaped
registers), bluetooth UART driver no longer needs to do it by itself. It
only requires to select the port it wants to use.

Change-Id: I5a30500f4b6f4155292609d0ed4a758f91930817
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:14:01 -05:00
Tomasz Bursztyka
088e0a980f arm: Refactor how UART is configured
UART is configured statically into the driver directly and not anymore
in the board's system.c. Thus limiting the information to be scattered
into 2 files instead of 3. Then in future, it will also be possible to
remove driver specific informations from the generic UART API structure.

Change-Id: I001f2a6834df9a41ab395a80e4e39b347d545db3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:14:01 -05:00
Tomasz Bursztyka
4eb6aab3ad x86: Refactor how UART is configured
Now for x86 platforms, UART is configured statically or dynamically into
the driver and not anymore in the board's system.c. Thus limiting the
information to be scattered into 2 files instead of 3. Then in future,
it will also be possible to remove driver specific informations from the
generic UART API structure.

Change-Id: I7b7fa37f10f88316a4d375c99de3bbacf152a3e3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:14:01 -05:00
Tomasz Bursztyka
68a58ca587 kconf: Add an option to select PCI on x86 architecture
By default it is set to 'n'. This will be useful to enable the PCI layer
code if required. On quark boark, it is selected by default as UART
driver needs it currently.

Change-Id: I7aa38e73c431c66ebbd8092aff0a14d5fb9268d5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:14:01 -05:00
Tomasz Bursztyka
d3a4177d92 pci: Provide a simpler yet powerful PCI enumeration API
This fixes many issues around PCI enumeration from old API:
- a static internal table was fed with scanning results, thus eating
  memory, and worse: due to the limit of its size, scanning for new
  classes was impossible unless growing statically the size of this
  table --> more memory eaten! Not to mention PCI enumeration is done
  once at boot time for driver initialization and that's all, so this
  table is hanging around for nothing afterwards.
- one needs first to scan a class, then maybe he will be able to find
  his device via pci_dev_find. Where all could be done at once.
- pci_dev_find was not trustworthy due again to the internal table. Now
  if the device is not found, one will know it really went through all
  the possbilities.
- still let the possibility for hard-coded BARs value on driver side
  (thus no PCI scan required). However this is greatly advised not to do
  so as BARs might change over a firmware/BIOS update.

Comparison:

old pci_dev_scan: could only filter out via class mask.
new pci_dev_scan: can filter out via a class, a vendor and device ID
(it could easily do the same for Function and BAR index as these are
usually fixed and informed through datasheet)

old pci_dev_scan: was limited in its findings by the size of the
internal result table.
new pci_dev_scan: can proceed through all the buses and devices every
time (there are optimizations to avoid useless work of course)

old results did not tell about the function or BAR index.
new one tells, and the structure has not bloated.

old internal code: was storing a big table of results
new internal code: is only storing a small lookup structure and an
array of Bus:Dev pairs for each PCI class for optimizations purpose.
(though, if needed, we could disable this through some #ifdef)

Usage:

- Have a local struct dev_info
- Fill it with what you want to look for, currently: only class and
  vendor_id/device_id. Function and BAR index could be added if needed.
- Call pci_bus_scan_init(): this will reset the internal lookup
  structure.
- Call pci_dev_scan(<a pointer to your dev_info>): at first call, the
  internal lookup structure will pick up the informations from dev_info
  and will try to find out what has been requested. It will return 1 on
  success, or 0. On 1, your dev_info structure will be updated with the
  found informations. If more devices can be found against the same
  lookup informations, just call again pci_dev_scan(<a pointer to your
  dev_info>) as long as it returns 1. When 0 is hit, it will mean you
  found all.

Change-Id: Ibc2a16c4485ee3fed7ef4946af0ece032ae406e4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:14:01 -05:00
Peter Mitsis
18d53f7c97 Always use __start as the entry point
Not only is __start is a neutral label, but using a common entry point for all
architectures allows the entry point to be hoisted out of the linker script and
specified by the build system.

Change-Id: Ibcbb11a40ff964e0fc3c90afcfe231746071b040
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:00 -05:00
Peter Mitsis
cd4c6e1068 Correct file locations referenced in comments
Past tree restructuring efforts missed updating a few comments that referenced
file locations.

Change-Id: I19a732c77b160acf5a819b4993e4f3d55cef2d1c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:00 -05:00
Peter Mitsis
1c313b6f89 Remove references to ICC
Keys off variations of "ICC" to remove references to the Intel C Compiler as
it is not supported.

Change-Id: I09f67880b39839982ed1c450e564c274440628a5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:14:00 -05:00
Allan Stephens
a02396098d Eliminate exposure of non-public microkernel structures
Renames the include file defining non-public microkernel structures
from k_struct.h to kernel_structures.h, and relocates it to the
microkernel's non-public include file directory. This means that
applications and drivers including the microkernel's public APIs,
using microkernel.h, can no longer access non-public information.

Note: This change also eliminates some redundant #includes by the
microkernel's own subsystems, since the inclusion of minik.h brings
in the vast majority of public and non-public APIs.

Change-Id: Ic7d9ec1ebb8a124ccd0aaad98b50e16c197ffa00
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:14:00 -05:00
Dirk Brandewie
1a159cb3f5 loapic: Expose APIC LVT mask definition
When the local APIC timer driver is configured into the system it needs to
ability to enable/disable the local APIC timer. The definition of the
LVT mask bit was moved into the APIC interrupt driver as part of the
driver reroganization effort. Move the definition to the public header
file.

Change-Id: I8e7f8eab9f39aa17b96079836c182bde6f7b4fd1
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:00 -05:00
Juan Manuel Cruz
19f4eccb4a x86 lo-apic timer _sys_clock_tick_announce call.
This commit fixes the calling of the function
_sys_clock_tick_announce from the x86 lo-apic timer.
This call was used wrongly, using the old convention:
__sys_clock_tick_announce

Change-Id: I5417efe1efcb94925bd4bebbb3b91b491349c26e
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:13:59 -05:00
Yonattan Louise
dbada63eee Fix coding style issues.
Some checkpatch issues were solved by scripts leaving other problems
such as alignment and indentation issues.  In order to comply with the
defined coding style the following fixes were made:

- Fixed the function declaration moving the parameters' comments above
  the function in accordance to the doxygen format.
- Fixed functions' opening and closing brackets. These brackets should
  not be indented.
- Fixed the 'if', 'for' and 'while' statements adding the brackets
  around the sentence.
- Fixed comments' alignment.
- Fixed indentation.

The work was done manually and submitted as one commit. I didn't
separate these changes in different commits because they were fixed all
at once. Basically, all errors were fixed in every file at once.

Change-Id: Icc94a10bfd2cff82007ce60df23b2ccd4c30268d
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:59 -05:00
Benjamin Walsh
da26208623 timer: use _sys_clock_tick_announce() in drivers
Replace duplicate code and will allow for further cleanup by possibly
consolidating micro/nano code that is currently guarded by preprocessor
conditionals.

Change-Id: I9aa9966c581244646b6ea317ef8b51fef9054dd4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:13:59 -05:00
Benjamin Walsh
0c798772cc timer: fix incorrect nano_fiber_lifo_put in ISR
The correct call is nano_isr_lifo_put, but they are aliases of each
other, so that never caused an issue at runtime.

Change-Id: Ibec8e6d3377133e5e67589c5a3ad1b8fb3cc652c
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:13:59 -05:00
Benjamin Walsh
f166d84220 arm: fix tabs-vs-space issues in isr_wrapper.s
Change-Id: I4a87fe44e2a9444a460e7b0629d41a845ad2e7ed
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:13:59 -05:00
Yonattan Louise
323e0a133e Rename _I8259SpuriousIntCount to _i8259_spurious_interrupt_count
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ifadb978e31770eb9f4987a3205483aad9a525b86
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
639aa532e4 Rename _i8253IntStub to _i8253_interrupt_stub
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ie0770bd9ff872a9ed2b567baca1514d15fe6c90a
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
c43a34b312 Rename _TimerMode to timer_mode
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I1f95ae3c2fd44ae3bd366cd33208551cf5ea6d10
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
643223da28 Rename _VectorsAllocated to interrupt_vectors_allocated
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Iecde4bd6aed6ac9520f9f19533f044dff5f402b7
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
86da08984e Rename __DummyExcEnt to _dummy_exception_vector_stub
Updating global variable's name to follow a consistent naming convention.
Explicitly moved from __ to _ by direction of Ben Walsh

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I5cad8464d5f268383b2e0e63cfce144dc2602cf9
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
71c2628416 Rename __DummySpur to _dummy_spurious_interrupt
Updating global variable's name to follow a consistent naming convention.
Explicitly moved from __ to _ by direction of Ben Walsh

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ibd3615b830ab3a1f326517ec0f045bc3a437f1fd
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
4724f2bf7f Rename _Mxcsr to _sse_mxcsr_default_value
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I5d0f757899e3a148c155ed8d68774fcabbb3995c
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
2ac4a04b92 Rename __defaultEsf to _default_esf
Updating global variable's name to follow a consistent naming convention.
Explicitly moved from __ to _ by direction of Ben Walsh

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Idd6f7c3c2fdd818f0a794985f3689705cac3c0a2
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
3534dbf91f Rename _GdtEntries to _gdt_entries
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ife3cee8b615d66178386458d2d30a1841bf72a53
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
3d97587691 Rename _IdtBaseAddress to _idt_base_address
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I5c4719458d7bb90af2ba21594deed6885f958d34
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
04d87ce58f Rename _TimerIdleSkew to timer_idle_skew
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I5681dc0c33cc42ee48270eab418c99cc923f96b1
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
23f1b6f4ca Rename _MaxLoadValue to max_load_value
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Id7391e40bb709f03c58f552d6b783cad834bbdcc
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
5d861d51bb Rename _IdleOrigTicks to idle_original_ticks
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I28cbf0d02600d31548393870e712e6da062048da
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
d6b04be694 Rename _MaxSysTicks to max_system_ticks
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ic28658f68d473b3a163fe5d97f611bfd572f140e
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
e111f30cec Rename _IdleOrigCount to idle_original_count
Updating local variable's name to follow a consistent naming convention.
The prefix underscore is removed due to it's a local variable.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I31e267c1479dfaeeb0fba8c6ba0da45a3c011c0f
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
2d9c726c7b Rename _loApicTimerIntStub to _loapic_timer_irq_stub
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I8d54b60a2300421bf4c19ff4f64769606d4e9966
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
02de5f9d3a Rename staleIntCheck to stale_irq_check
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: If601942d8a2fbda68ae6e1070a492ee91a5f5107
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
114b8204a2 Rename programmedTicks to programmed_ticks
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ide6e66dc808bd2b271e246eacfa697ef37342006
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
29ca387f6f Rename counterLastValue to counter_last_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I92617172c8aafb0f1597d6d9f26d755a68b65252
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
0aeaa43158 Rename counterLoadValue to counter_load_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ia9fcbd72de260f20cdda7f2754c02deb5b1dffba
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:54 -05:00
Yonattan Louise
34a27b9a75 Rename expectedMainCountValue to main_count_expected_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ib7185917b253fc5470e702b682b1bc206a153d26
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
410f46d7e2 Rename firstIntMainCountValue to main_count_first_irq_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I43b2a20b0f250e60b7b295710a7eac4cf4cc3d03
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
5b6469b1de Rename _Gdt to _gdt
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I752fc813d33d4965b8d764347870dc51273c9634
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
084f2ce4ae Rename _GdbStubIrqVectorTableEntry to _irq_vector_table_entry_with_gdb_stub
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I4f0c65fb93cfac7d91d89c034a4bccd46d33a2f0
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
2fae92685c Rename _GdbStubIrqVectorTable to _irq_vector_table_with_gdb_stub
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I42d80495508656c8476b5538fbd4af7a7569e8d6
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
0db750f266 Rename cmdpacket to cmd_packet
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ie65865c480be5b6a678ef4716dade3ee745bd88f
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
84bb42daed Rename idleMode to idle_mode
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Icb3f7d66e94bcf1aa8dec5cc76257b6095c19d56
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
5222b8b6c6 Rename timerMode to timer_mode
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ie5ecf994d2e7e16a0e223fa64355274f6f0ad42e
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
0514636b5a Rename timerIdleSkew to timer_idle_skew
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I247a19e520307d90a5742c85bf3cf6f04cb28c3b
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
3701c19d6a Rename maxLoadValue to max_load_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I6737b01f427d83b4bf1bc486ef0706fac0db0a31
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
0b4193987a Rename idleOrigTicks to idle_original_ticks
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ide570aba204fdb7098bbe0f57ee7bbeaa436951d
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
fb11aaf72a Rename maxSysTicks to max_system_ticks
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ie986b037f03264f4447b2bb4375ddcff91668633
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
c93c58b7ee Rename idleOrigCount to idle_original_count
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ia4f7d944464225d6ff1977a559637a5a0d61c0d5
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
98999a8f73 Rename defaultLoadVal to default_load_value
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I8f886c03823f071edb90b297c290cc6f432a4565
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
817e2b275f Rename _IrqVectorTable to _irq_vector_table
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Id3f9096f28a1bf98035c6a531cd8d2dc66e6448a
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
092f1132fe Rename _IsrTable to _sw_isr_table
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I7fc572f869c5f104538cfb3f84b1b36071e54dde
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
4d19693b33 Rename _NanoKernel to _nanokernel
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Icf5900c057f3412d3c7725c07176fe125c374958
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Yonattan Louise
7770ec2db1 Rename accumulatedCount to clock_accumulated_count
Updating local variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" -o -name "*.arch" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I80ccb884f1ffd8f3740cd9298787462485b08024
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:53 -05:00
Dmitriy Korovkin
e82a2a36c7 Compiler specific configuration
If a source code file depends on a configuration option,
that, in turn, depends on a compiler, this file has to
include toolchain.h.

toolchain.h includes a compiler specific header file that
sets the proper configuration option.

Change-Id: I7c9002522a8c6d6fd945e27a450ebe46ba9d4892
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:13:52 -05:00
Dmitriy Korovkin
d33ad051ac Consolidate inline assembler code in a set of header files
In order to have a better compiler support consolidate
inline assembler code in a set of header files.
If another compiler is used, that supports a different
inline assembler format, asm_inline_<compiler name>.h
heder files have to be provided.

Change-Id: Iecc7d96419efd767a8463933badd4db4a557de5b
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:13:52 -05:00
Allan Stephens
73f9775c01 Eliminate kernel/common sub-directory
Moves all files in this sub-directory to kernel/nanokernel, then
deletes the sub-directory itself. Both of the relocated files are
associated with fundamental nanokernel capabilities, which makes
their inclusion in the main nanokernel source directory logical.

Change-Id: Ifae46a50c60f67e9226d3a33cd0086b644b291ba
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:51 -05:00
Allan Stephens
2fd8964a71 Eliminate kernel/common/bsp sub-directory
Moves all files in this sub-directory to kernel/nanokernel, then
deletes the sub-directory itself. Both of the relocated files are
used during nanokernel initialization, which makes their inclusion
in the main nanokernel source directory logical.

Change-Id: I1cac0561317f808eab2de74ece9868c62c70b6d8
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:51 -05:00
Allan Stephens
661ba14943 Eliminate nanokernel/core sub-directory
Moves all files in this sub-directory up one level, to the main
nanokernel source directory, then deletes the sub-directory itself.

This change  means that all nanokernel source files (with the
excecption of its include files) are now in the main nanokernel
source directory, which is a more intuitive arrangement.

Change-Id: I6bd4b1bb6fdd9be13d57b320947f520a5bc73914
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:51 -05:00
Allan Stephens
3c8fb4ac7a Eliminate nanokernel/task sub-directory
Relocates start_task() so that it appears in the main microkernel
directory, alongside its complementary routine abort_task();
this corrects a long-standing anomaly in which this microkernel-
specific routine appeared in the nanokernel portion of the tree.

With this move, the start_task.c file and its parent nanokernel/task
sub-directory no longer serve any purpose and are removed. (Note that
no changes are required for ARC architecture support, which does not
support microkernel capabilities and doesn't use this sub-directory.)

Change-Id: I973e1c32c9a8ddcacdc08159069ae7cdfea0f107
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
10d27dcaa2 fsl_frdm_k64f: Add Bluetooth support for fsl_frdm_k64f target
This allows to build Bluetooth for the target.

Change-Id: I89b1c369d698ee20d0b190614d7f3a9f686f7a5e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
30199fae03 fsl_frdm_k64f: Register isr for Bluetooth UART driver
Support following configurations:

- With SW ISR table (CONFIG_SW_ISR_TABLE=y)
  - static (CONFIG_SW_ISR_TABLE_DYNAMIC=n)
  - dynamic (CONFIG_SW_ISR_TABLE_DYNAMIC=y)

- Installed directly in the vector table
  (CONFIG_SW_ISR_TABLE=n)

Change-Id: I8562504366295c63202a387c12a2f99f4f1b3dde
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
4603624589 fsl_frdm_k64f: Add Bluetooth UART definitions for fsl_frdm_k64f
For fsl_frdm_k64f target add definitions for Bluetooth UART.

Change-Id: Ib1f036aa29ae8709a67016180639d7130a352777
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
04fc7b4184 ti_lm3s6965: Register isr for Bluetooth UART driver
Support following configurations:

- With SW ISR table (CONFIG_SW_ISR_TABLE=y)
  - static (CONFIG_SW_ISR_TABLE_DYNAMIC=n)
  - dynamic (CONFIG_SW_ISR_TABLE_DYNAMIC=y)

- Installed directly in the vector table
  (CONFIG_SW_ISR_TABLE=n)

Change-Id: Icbaf710fcd8ed8dba409c144cf25849985270a64
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
cef0f4bca7 ti_lm3s6965: Include Bluetooth build targets for ti_lm3s6965
Add Bluetooth UART driver to build targets.

Change-Id: Ia79b69a996bf79b24672bf1e0350e3de171ac409
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
cc19fbb873 ti_lm3s6965: Add Bluetooth initialization to system.c
Add Bluetooth initialization for target ti_lm3s6965.

Change-Id: I7c7e392d2bb8671098e54b1305051a5882fd3bef
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Andrei Emeltchenko
be2135d75e ti_lm3s6965: Add Bluetooth UART definitions for ti_lm3s6965
Add definitions for UART for ti_lm3s6965.

Change-Id: If7b3d6f0cabd69eaad962b5e73429b66d1f0ef0e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:51 -05:00
Peter Mitsis
bf2e1d3017 Remove remaining references to NLI
NLI files are not supported.

Change-Id: Id9bb1b083051e8ed65b854b4293f2848a46b1589
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:13:48 -05:00
Tomasz Bursztyka
e2eff8fafc quark: Avoid duplicate definition
No need to duplicate PCI class definition since it's alread defined in
drivers/pci/pci_mgr.h.

Change-Id: I834b99c300487d7c51e406555de87d2484222213
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:13:48 -05:00
Tomasz Bursztyka
ae09a48a7e console: Put the public API header in the right location
Only moving the header from drivers/console/uart_console.h to
include/drivers/console/uart_console.h so source file did not need to be
changed, only the defs.objs files to look into include/drivers/console.

Change-Id: I585e16b50d9ffecf01ca9225e80f0e101f62ee4c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:13:48 -05:00
Peter Mitsis
d13eca21a5 Remove references to Simics in crt0.s comments
Simics is not supported.

Change-Id: I2a1c7a3c6f19962f86a056b7628cd0d0fff6be1d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:13:48 -05:00
Peter Mitsis
f6e34618a8 Remove POMS memory model comment
The POMS memory model is not supported.

Change-Id: I9af7798be2e234c8a4adfde200187ffceacf89df
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:13:48 -05:00
Dan Kalowsky
c05d780c96 Renaming _SysPowerSaveIdleExit to _sys_power_save_idle_exit
Updating micro kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Searching for ${1} to replace with ${2}"

echo "Checking C, CPP, H, HPP, and s files..."
find . -type f \( -iname \*.[ch] -o -iname \*.[ch]pp -o -iname \*.s \) \
       -not \( -path host/src/genIdt -prune \) \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

echo "Checking KCONF, LST, and PY files..."
find . -type f \( -iname \*.lst -o -iname \*.kconf -o -iname \*.py \) \
       -not \( -path host/src/genIdt -prune \) \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Change-Id: Ife7e4fcd5a3f550d3da28d0c13f83c4adabe48a9
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:13:47 -05:00
Dan Kalowsky
bae67b2b58 Renaming _SysPowerSaveIdle to _sys_power_save_idle
Updating micro kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Checking C, CPP, H, HPP, and s files..."
find . -type f \( -iname \*.[ch] -o -iname \*.[ch]pp -o -iname \*.s \) \
       -not \( -path host/src/genIdt -prune \) \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"


echo "Checking KCONF, LST, and PY files..."
find . -type f \( -iname \*.lst -o -iname \*.kconf -o -iname \*.py \) \
       -not \( -path host/src/genIdt -prune \) \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Change-Id: I2cf754540cdca1b107898241d8016613711f677b
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:13:47 -05:00
Andrei Emeltchenko
fbb1526d1a Rename _IsrWrapper camelCase to _isr_wrapper
Change-Id: I217eced3965fbf313a7e0fbef38db9dd876fcf80
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
2e0f3845f7 Rename _SpuriousIRQ to _irq_spurious
Renaming camelCase _SpuriousIRQ makes code more readable and
consistent.

Change-Id: I2bda4d107091384811d9f9187f3529960842631e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
c6a72c2f81 serial_console: Use static wrappers with right _IntExit()
Instead of calling directly isr call static wrapper with right
_IntExit() at the end.

Change-Id: Ic5ca74200be6477837bf6a25803540990e9e8889
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
c121074115 ti_lm3s6965: Reformat comment block making it readable
Change-Id: Id88b6201aaf7d8565f627cb2c6f1c5523167351f
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
4be01c91cf fsl_frdm_k64f: Support SW_ISR_TABLE for serial console
Add support for fsl_frdm_k64f configuration with
CONFIG_SW_ISR_TABLE_DYNAMIC and CONFIG_SW_ISR_TABLE. Entry for serial
irq is removed from vector table to be handled is ISR SW table.

Change-Id: I03b2a6f71aab09660587a290a0e69bdac67ef66c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
20ce390664 ti_lm3s6965: Support SW_ISR_TABLE for serial console
Add support for ti_lm3s6965 configuration with
CONFIG_SW_ISR_TABLE_DYNAMIC and CONFIG_SW_ISR_TABLE. Entry for serial
irq is removed from vector table to be handled is ISR SW table.

Change-Id: I6bda7a541aad979e4a50beb9154bbeb3758b48ee
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
f1e1897ade console: Replace uartConsoleInit with uart_console_init
Rename camelCase uartConsoleInit function for consistency with the
rest of the code in serial console.

Change-Id: I519737070538e9c0f52a8d110a3eff68e0185ce2
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:45 -05:00
Andrei Emeltchenko
dfa5f2371b serial_console: Rename console_uart_isr to uart_console_isr
Following comments received during review rename console_uart_isr to
uart_console_isr for consistency reason.

Change-Id: Ibee1dec40ee19a9095f78969a07ffb73518fffbb
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:13:45 -05:00
Allan Stephens
e4b70a95fb Eliminate GEN_OFFSET_SYM_HOST() macro
Gets rid of code that creates absolute symbols for data structures
that are no longer referenced by external tools, as well as the
macro that was used to generate them.

The code that creates absolute symbols for context monitoring-related
symbols is retained, but is now directly tied to the CONTEXT_MONITORING
configuration option upon which those symbols depend.

Change-Id: I6b2ce46d9ab9592a478f591cb074c4c163e9ba0f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:45 -05:00
Allan Stephens
b32f81dbe4 Rename "activeLink" field of CCS to "next_context"
Modifies the name of this field to make its purpose clearer,
and to align with coding conventions.

Change-Id: I8de78df1a0459122067d650130e01078afb5af8a
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:45 -05:00
Allan Stephens
ab03ec2a62 Adapt tools support code to reflect its context monitoring nature
Revises code that was previously conditional on HOST_TOOLS_SUPPORT
but is now conditional on CONTEXT_MONITOR.

Change-Id: I78a9126c5a66128f5aafe6b4220b3c7c68e01335
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:45 -05:00
Allan Stephens
c7661eb981 Transform HOST_TOOLS_SUPPORT config option to CONTEXT_MONITOR
Revises this option to make its purpose clearer, and to align it
with other experimantal monitoring-type configuration options.

Change-Id: I593bb7560b5a0544eb05affaa07b59dd78ea907e
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:45 -05:00
Allan Stephens
5765af636f Remove unnecessary conditional comments
Eliminates conditional comments that don't really serve a useful
purpose.

Change-Id: I4f26cae67971d1d80bd06075da89e5573b0780d4
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-02-05 20:13:45 -05:00
Johan Hedberg
2581ad9313 Bluetooth: Add HCI UART (H4) driver
This patch adds a simple HCI UART (H4) driver that currently maps to
the second UART in the system. The main intention is to use this
together with qemu for accessing the Bluetooth controller available on
the host OS side.

The H4 HCI transport protocol is perhaps the simplest of the standard
HCI transports. It consists of a single byte in the beginning of each
packet which indicates the type of the packet: HCI event, HCI command,
ACL data, or SCO data (which we don't use at the moment).

Change-Id: I225a2a2361fbd7cd4ba82ea1f81ddc1271e9e7c2
Co-authored-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-02-05 20:13:44 -05:00
Johan Hedberg
ac63429177 Bluetooth: Add skeleton for HCI core
To introduce the Bluetooth stack to the tree we need some additions to
the configuration options, as well as the very basic header files. The
patch also adds a skeleton for a bt_init() function that applications
will need to call to initialize Bluetooth functionality.

Change-Id: Ideb24dfea584b71f514e05eb47654b659776133e
Co-authored-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-02-05 20:13:44 -05:00
Yonattan Louise
ab9c05ac2a Rename _SysIdleElapsedTicks to _sys_idle_elapsed_ticks
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I4e5c9419fe0ccbc4b2990b96fc95c697decc18e0
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:44 -05:00
Yonattan Louise
d7af5727e8 Rename _SysPowerSaveFlag to _sys_power_save_flag
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ide44a5957321a1dd2971a341da2d35dfb1e0d0ac
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:44 -05:00
Yonattan Louise
93a1d7ca89 Rename K_Args to _k_command_stack
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I5e249e34ee9666666e31db6b9f71fe2abcc22400
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:43 -05:00
Yonattan Louise
9bbb6e1e7b Rename K_Task to _k_current_task
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ic81b4ad7edf476da61ae62df627866e0446714d7
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:43 -05:00
Yonattan Louise
c4bd9cc6ab Rename nanoTimerList to _nano_timer_list
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I2e501394b7fa4264d9854659e2dd008e5c94b540
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:43 -05:00
Yonattan Louise
cf0b28d243 Rename nanoTicks to _nano_ticks
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Iebefec0e02cbb838564dd71fd4424c1adbff31f5
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:43 -05:00
Yonattan Louise
e7c1f2c20b Rename _InterruptStack to _interrupt_stack
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: I36709c9833279f05a186a5c00b996d242c843d4c
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:42 -05:00
Yonattan Louise
a17eac73c3 Rename _HwIntToCHandlerLatency to _hw_irq_to_c_handler_latency
Updating global variable's name to follow a consistent naming convention.

Change accomplished with the following script:

   #!/bin/bash
   echo "Searching for ${1} to replace with ${2}"
   find ./ \( -name "*.[chs]" -o -name "sysgen.py" -o -name "*.kconf" \) \
            ! -path "./host/src/genIdt/*" \
            ! -path "*/outdir/*" | xargs sed -i 's/\b'${1}'\b/'${2}'/g';

Change-Id: Ia8a93e07c88bbc559e7bbf0f14815e5e76110fb6
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:42 -05:00
Andrei Emeltchenko
139c856403 Add serial console input handler
Serial console handler when registered allows to interact with serial
line. It can either execute callback from ISR or defer execution to
fiber or task. This will be used in Bluetooth development for tests and
simple interaction with Bluetooth stack.

Change-Id: Ia960b456a75062d614baea324608058d979aa11b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2016-02-05 20:13:41 -05:00
Peter Mitsis
101d486834 Rename k_args 'Srce' field to 'alloc'
Since multi-node systems are not supported, the 'Srce' field now only serves
one purpose--to indicate whether the packet was allocated from the command
packet pool.  As such, a better name (and type) for it is 'alloc' (of type
'bool') since 'Srce' (of type 'knode_t') suggest multi-node support.

Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change-Id: I47a935af13fd55dbca23c879841d68caf895eae4
2016-02-05 20:13:41 -05:00
Dmitriy Korovkin
7a3ee5e95e Rename driver header files according to naming standard
Change-Id: Ib384fd93c3d35abab1754b37d6464ff7dfe4a893
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
2016-02-05 20:13:40 -05:00
Peter Mitsis
b5d65fa442 Remove VIRT_ADDR_xxx macros
The VIRT_ADDR_xxx macros are no longer used.

Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:13:39 -05:00
Yonattan Louise
5b5f4eb948 Fix checkpatch issue - WARNING:LINE_SPACING
Adding a line after variable declaration in order to comply with
the defined coding style.

Change-Id: Id41af88404bd37227bfd59a2d71ce08d0d6ce005
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
2016-02-05 20:13:39 -05:00
Yonattan Louise
b5e560fa81 Fix checkpatch issue - WARNING:FUNCTION_ARGUMENTS
This commit modifies the function declaration to have the arguments
in the same line to the identifier of the function.

Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@linux.intel.com>
Change-Id: Ic7a2f19e353e4f3fa42dded09fa1c8f23bde2b2b
2016-02-05 20:13:39 -05:00
Yonattan Louise
f7df273f8c Fix spaces around parentheses
This commit deletes spaces after open parentheses '(' and spaces before
close paratheses ')'.

This modification were done with the following script:

checkpatch_script="$VXMICRO_BASE/scripts/checkpatch.pl --mailback --no-tree -f --emacs --summary-file --show-types --ignore BRACES,PRINTK_WITHOUT_KERN_LEVEL,SPLIT_STRING --max-line-length=100 "

cd $VXMICRO_BASE;
for file in $(find ./ -name "*.[ch]" ! -path "./scripts/*" ! -path "./host/src/wrsconfig/*");
do
	# fixing spaces after open parethesis
	for line in $(eval $checkpatch_script $file | grep "ERROR:SPACING: space prohibited after that open parenthesis '('" | cut -d":" -f2)
	do
		sed -i -r -e ''$line' { s/\([ \t]*/\(/g }' $file;
	done;

	# fixing spaces before close parethesis
	for line in $(eval $checkpatch_script $file | grep "ERROR:SPACING: space prohibited before that close parenthesis ')'" | cut -d":" -f2)
	do
		sed -i -r -e ''$line' { s/[ \t]*\)/\)/g }' $file;
	done;
done;

Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
Change-Id: I4482fc50ec45542afa2e60c5f2fef4e75fb24dd3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:13:22 -05:00
Dan Kalowsky
31e11d6316 Replacing _NanoInit with _nano_init
Updating nano kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Searching for ${1} to replace with ${2}"
find . -type f \( -iname \*.c -o -iname \*.h -o -iname \*.s -o -iname \*.kconf \) \
       -not \( -path host/src/genIdt -prune \) \   \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 19:45:35 -05:00
Dan Kalowsky
18c8d41bcc Rename _NanoFiberSwap to _nano_fiber_swap
Updating nano kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Searching for ${1} to replace with ${2}"
find . -type f \( -iname \*.c -o -iname \*.h -o -iname \*.s -o -iname \*.kconf \) \
       -not \( -path host/src/genIdt -prune \) \   \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 19:45:35 -05:00
Dan Kalowsky
ff8c2c0487 Rename _FiberStart to _fiber_start
Updating nano kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Searching for ${1} to replace with ${2}"
find . -type f \( -iname \*.c -o -iname \*.h -o -iname \*.s -o -iname \*.kconf \) \
       -not \( -path host/src/genIdt -prune \) \   \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 19:45:35 -05:00
Dan Kalowsky
bcddb11e8c Rename _InsertCCS to _insert_ccs
Updating nano kernel functions to follow a consistent naming convention.
Part of that process is the removal of camelCase naming conventions for the
preferred_underscore_method.

Change accomplished with the following script:

#!/bin/bash
echo "Searching for ${1} to replace with ${2}"
find . -type f \( -iname \*.c -o -iname \*.h -o -iname \*.s -o -iname \*.kconf \) \
       -not \( -path host/src/genIdt -prune \) \   \
       -not \( -path host/src/gen_tables -prune \) \
       -print | xargs sed -i "s/"${1}"/"${2}"/g"

Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 19:45:35 -05:00