Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Make `struct arch_esf` compulsory for all architectures by
declaring it in the `arch_interface.h` header.
After this commit, the named struct `z_arch_esf_t` is only used
internally to generate offsets, and is slated to be removed
from the `arch_interface.h` header in the future.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
The irq_offload mechanism was using the same entry of the IDT vector for
all CPUs on SMP systems. This caused race conditions when two CPUs were
doing irq_offload() calls.
This patch addresses that by adding one indirection layer: the
irq_offload() now sets a per CPU entry with the routine and parameter to
be run. Then a software interrupt is generated, and a default handler
will do the appropriate dispatching.
Finally, test "kernel/smp_abort" is enabled for x86 as it should work
now.
Fixes#72172.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Fix the dependencies of `CONFIG_EXCEPTION_STACK_TRACE`:
- Architecture-specific Kconfig, i.e.
`X86_EXCEPTION_STACK_TRACE`, will be enabled automatically
when all the dependencies are met.
- `EXCEPTION_STACK_TRACE` depends on architecture-specific
Kconfig to be enabled.
- The stack trace implementations should be compiled only if
user enables `CONFIG_EXCEPTION_STACK_TRACE`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Currently, the stack trace in ARM64 implementation depends on
frame pointer Kconfigs combo to be enabled. Create a dedicated
Kconfig for that instead, so that it is consistent with x86 and
riscv, and update the source accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `DEBUG_INFO` in the `EXCEPTION_STACK_TRACE` is only
required by x86. Move that to `X86_EXCEPTION_STACK_TRACE`
instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
In some cases, the `fp` will never be `NULL` and the stack
unwinding can go on and on forever, limit the max depth so that
this will not happen.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
For SoC with `CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET`,
it should be taken into consideration when disconnecting IRQ.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Change the type of `cpu_id` to `uint8_t` since that is the type
of `arch_curr_cpu()->id`.
Instead of using precompiler switch (`#ifdef CONFIG_SMP`), use
if-else shorthand instead (`IS_ENABLED(CONFIG_SMP)`).
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Make sure that esf is not NULL before calling
z_riscv_unwind_stack to prevent NULL pointer dereferencing.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Regarding recent changes in general MPU configuration
(https://github.com/zephyrproject-rtos/zephyr/pull/71969), add
appropriate configs for isolating thread stacks into ARC MPU.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Use the multi-level interrupt APIs that accepts `level` as an
argument for the code where the level of the interrupt is not
known at build time.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously the multi-level irq lookup table is generated by
looping through the devicetree nodes using macros & Kconfig,
which is hard to read and flimsy.
This PR shifts the heavy lifting to devicetree & DT macros such
that an interrupt controller driver, which has its info in the
devicetree, can register itself directly with the multi-level
interrupt architecture, which is more straightforward.
The previous auto-generated look up table with macros is now
moved in a file of its own. A new compatibility Kconfig:
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and
enabled by default to compile the legacy look up table for
interrupt controller drivers that aren't updated to support the
new architecture yet.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Current on x86 & risc-v that implement stack trace, the
maximum depth of the stack trace is defined by a macro.
Introduce a new Kconfig:EXCEPTION_STACK_TRACE_MAX_FRAMES
so that this is configurable in software.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Selecting `CONFIG_SYMTAB` will
enable the symtab generation which will be used in the
stack trace to print the function name of the return
address.
Added `arm64` to the `arch.common.stack_unwind.symtab` test.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The mepc register is the address of the instruction that was
interrupted, it will make debugging easier if we know the
name of the symbol, so print it if `CONFIG_SYMTAB` is enabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Selecting `CONFIG_EXCEPTION_STACK_TRACE_SYMTAB` will
enable the symtab generation which will be used in the
stack trace to print the function name of the return
address.
Updated the `stack_unwind` test to test the symbols in a
stack trace.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Existing solutions for linking the Xtensa vector table are a
cut-and-paste mess of inherited code, with more than a dozen special
sections that need to be linked into many special MEMORY{} regions.
Accept the existing convention used by C/asm code, but automatically
detect the needed offsets for the platform from core-isa.h (it can
share the preprocessing with gen_zsr.py) and emit a file that can be
included in lieu of all the existing boilerplate.
Signed-off-by: Andy Ross <andyross@google.com>
RISC-V PMP implementation supports isolating thread stacks
within the same memory domain, and also is the only
supported operating mode. So select the corresponding
kconfig by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
ARM MPU implementation supports isolating thread stacks
within the same memory domain, and also is the only
supported operating mode. So select the corresponding
kconfig by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Declutter `fatal.c` by moving the stack unwinding logic into
`stacktrace.c` and guard its compilation with `CMakeLists.txt`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The original code would (unsurprisingly) only emit handler functions
for interrupt levels with interrupts associated with them. But it
turns out that it's possible to configure an xtensa device with an
empty-but-otherwise-real interrupt level (specifically mt8195 has a
"Level 3" interrupt not associated with any input IRQS, it's one level
above EXCM_LEVEL and one level below the DEBUG exception).
This script is old, and not set up to parse the full core-isa.h
directly, so modifying it to detect this condition is difficult.
Instead, just emit all 15 possible interrupt handlers, even empty
ones. The extra stubs are harmless as they'll be dropped if uncalled.
Signed-off-by: Andy Ross <andyross@google.com>
Some oddballs cores can be generated without an "NMI" interrupt, in
which case core-isa.h will not define XCHAL_NMILEVEL. This code is
trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the
pedantically correct choice anyway (NMI's by definition, cannot be
masked).
Signed-off-by: Andy Ross <andyross@google.com>
The script to generate the _soc_inthandlers.h header has been run
manually for years, only because I was a cmake novice at the time and
unsure how to integrate it into the build. So every new platform has
to find the script and template file and figure out how to generate
the file. And in a few cases it looks like we've tried to EDIT the
resulting files in the tree.
Let's finally do this right. The file is now dropped (for every
xtensa platform) as a "xtensa_handlers.h" file, and there is a Kconfig
to control whether the original/manual file or the new one is used by
the platform code. We can migrate the other platforms slowly as
people have time to validate.
Signed-off-by: Andy Ross <andyross@google.com>
s2ram procedure used RAM magic word for marking suspend-to-RAM. This
method may not work in some cases, e.g. when global reset does not
reset RAM content. In that case resuming from s2ram is detected when
global reset occurred.
RAM magic word method is the default but with
CONFIG_PM_S2RAM_CUSTOM_MARKING a custom implementation can be provided.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
In order to support Linux rproc loading, some SOCs require
the boot-vector and irq-vectors to be placed into a defined
memory area for the mcu to boot.
This is necessary for NXP's IMX SOCs for instance but
can be leveraged by other SOCs that have multiple
zephyr,flash choices.
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
The only page table duplicated is the kernel page table. This function
does not need a parameter.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We can use some extra bits available for SW implementation to
save original permissions and avoid duplicating the kernel page tables
for the default memory domain.
Whe duplicating the page table to a new domain we just ensure
to restore the original map.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Simplify the logic around the shared attribute. Checks if a memory
region should be shared only in the function that actually maps the
memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove the limitation of number of cpu support in x86 arch.
Also add support for retrieve cpu informations such as for
hybird cores.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Change the GCC toolchain configuration to make use of the Cortex-R82
target. When Cortex-R82 was added as a GCC toolchain option, the GCC
version of the Zephyr SDK did not support Cortex-R82 tuning. Zephyr was
therefore compiled compiled for the Armv8.4-A architecture. Since Zephyr
SDK 0.15.0 (which updated GCC from 10.3.0 to 12.1.0) coupled with Zephyr
3.2, the Cortex-R82 target is supported.
The Armv8-R AArch64 architecture does not support the EL3 exception level.
EL3 support is therefore made conditional on Armv8-R vs Armv8-A.
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
Use `z_riscv_fatal_error_csf` that expects the
callee-saved-registers pointer only if `CONFIG_EXCEPTION_DEBUG`
is enabled, otherwise use `z_riscv_fatal_error`, as there can
be garbage in the `a2`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Change the character used to indicate immediate operands from '$' to '#'
to resolve an "invalid instruction" error when building with clang.
For arm, binutils allows either '#' or '$' to indicate immediate operands.
clang seems to accept '$' for arm in other instances
(my build accepts 'subs r0, r0, $0x02', for example), but in this case it
produces an error that this is an invalid instruction due to the "$0x02"
operand.
Given clang's inconsistent behavior, I'm guessing this is a bug in clang
somewhere, but:
1. '#' for immediate operands seems to be more standard for arm in
general and seems to be what is used throughout the rest of Zephyr's
arm asm code.
2. Switching out '$' for '#' shouldn't negatively impact other
toolchains.
As such, switch out the character used to unblock clang builds until this
can be fixed in clang.
Signed-off-by: Jonathon Penix <jpenix@quicinc.com>
LOG which IRQn line is triggering on spurious IRQs as this makes it
much easier to debug spurious IRQs.
The new logs with this patch looks like:
<err> os: Unhandled IRQn: 227
<err> os: >>> ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0
<err> os: Current thread: 0x20032c20 (unknown)
<err> os: Halting system
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Move the kconfig options used to configure the interrupt
and wait time to the sample which uses them instead of
having them in the architecture code.
This options are very particular for this sample and not
really an API.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This option can be used now also with native_sim
and seems to work fine with both 32 and 64 bit targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Move the LLVM fuzzing specific code out of the board main
file and into the sample.
That way we avoid needing to duplicate it for native_sim and
avoid having a very adhoc interface between the fuzzer test
and runner code.
Also ensure it works for native_sim and not just native_posix
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Compilers predefine system-specific macros which carry information about
compiler, target architecture and operating system. It provides basic
compiler-dependent information like size of types, their maximal and
minimal values, etc. It allows to write common libc headers for multiple
architectures and operating systems.
These macros allow code to always determine what is the target operating
system. This is a problem when compiling code of modules that supports
multiple operating systems (e.g. cryptography libraries).
To avoid confusion we shouldn't leak host operating system macros (e.g.
__linux__, __linux, linux, etc.) when compiling for native_sim board.
Unfortunately, there is no single universal switch that disables all
operating system macros:
- '-undef' removes also architecture-related macros
- '--target' is only available for Clang compiler
This patch uses '-include' option to include file that undefines all
well-known operating system macros.
Run 'gcc -dM -E - < /dev/null | sort' to get full list of predefined
macros.
Signed-off-by: Patryk Duda <patrykd@google.com>
Found via static analysis. In fault path when checking for stack
overflows, if CONFIG_MULTITHREADING is not set, `guard_end` is left
uninitialized and is subsequently used in a comparison.
The solution is to simply return `false` in this configuration as stack
guards are not configured in the first place.
Signed-off-by: François Baldassari <francois@memfault.com>
When duplicating a page table, we don't need to copy
the mapping to the kernel l1 page table virtual address.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
`CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` shoud be taken into
account in `arch_irq_connect_dynamic`, same as it is done in
`ARCH_IRQ_CONNECT` macro.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This also fixes a typo in `z_arm_switch_to_main_no_multithreading` making
it unlock irq instead of locking them when main returns.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Replace the global CSTD property with the CSTD kconfig option to select
at least C11 standard.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Influenced heavily by the RISCV64 stack unwinding
implementation in the Linux kernel.
`CONFIG_RISCV_EXCEPTION_STACK_TRACE` can be enabled by
configuring the following Kconfigs:
```prj.conf
CONFIG_DEBUG_INFO=y
CONFIG_EXCEPTION_STACK_TRACE=y
CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT=y
CONFIG_OMIT_FRAME_POINTER=n
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This mistake was introduced when converting from ASM to C.
This change also restores the associated comment from the ASM source.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This is a fix for #61761 where a cooperative task is switched from at the
end of an exception. A cooperative thread should only be switched from if
the thread exists the ready state.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change significantly enhances the maintainability & portability of the
code at the expanse of an indirection (1 outlined function).
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation and
unifies irq locking code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
# Conflicts:
# soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This is a first step in reducing the amount of ASM in arch/arm/cortex_m
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
v* register aliases are uncommon and it can be surprising to find them.
This change makes use of r* register names for a more consistent
experience of reading assembly.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This method has special ABI requirement that requires the use of ASM.
This change documents why this is required & adds reference to the
related specification.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").
This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Only request the linker to link ASAN in the final stage, not
during the partial linking stage.
This fixes a link issue when building with llvm.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
If the CONFIG_ASAN_RECOVER option is set, also pass
-fsanitize-recover=all to the build of the native simulator
built files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Currently LLEXT on Xtensa supports relocatable extensions, linked for
a specific address range, while relocation itself takes place in a
temporary buffer. For this section addresses have to be set correctly
by the linker for their target locations.
This commit adds support for relocatable extensions, built without
using specific memory addresses and run at the same addresses, where
they are loaded.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Adds support for all relocation type produced by GCC
on ARM platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).
Signed-off-by: Cedric Lescop <cedric.lescop@se.com>
This adds the necessary bits to enable memory mapping thread
stacks on both x86 and x86_64. Note that currently these do
not support multi level mappings (e.g. demand paging and
running in virtual address space: qemu_x86/atom/virt board)
as the mapped stacks require actual physical addresses.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This introduces support for memory mapped thread stacks,
where each thread stack is mapped into virtual memory
address space with two guard pages to catch
under-/over-flowing the stack. This is just on the kernel
side. Additional architecture code is required to fully
support this feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Previous commit changed the privileged stack size to be using
kconfig CONFIG_PRIVILEGED_STACK_SIZE instead of simply
CONFIG_MMU_PAGE_SIZE. However, the stack bound check function
was still using the MMU page size, so fix that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most places use CONFIG_X86_STACK_PROTECTION, but there are some
places using CONFIG_HW_STACK_PROTECTION. So synchronize all
to use CONFIG_X86_STACK_PROTECTION instead.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some toolchains cannot create shared objects for Xtensa, with them we
have to use relocatable objects. Add support for them to llext.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
When thread stack is defined as an array, K_THREAD_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone thread stack has its size calculated by
Z_THREAD_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_THREAD_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When kernel stack is defined as an array, K_KERNEL_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone kernel stack has its size calculated by
Z_KERNEL_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_KERNEL_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
