The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
During conversion in #16815 a few device tree instance macro aliases
where missed (probably due to them existing to support future SoCs
and so not currently compiled), this fixes their usage.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Save few RAM bytes by declaring exti_irq_table as const.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some code in stm32 exti driver was considering exti lines number
for which no IRQ_CONNECT was available. To be clear, this code
was not functional and since no one complained it was not used.
Besides, code to take into account these "high" irq lines was
complex hard to read and review.
Simplify state of things by removing completely this part of code.
It could be put back again piece by piece when required.
This change allows to get rid of EXTI_LINES definition.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Function stm32_exti_enable is complex and makes it hard to extend
to new stm32 series.
When MP1 support was added, table exti_irq_table was introduced
to simplify stm32_exti_enable function.
This change extends usage of this table to other series, without
adding or removing any functionality.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When CONFIG_X2APIC is enabled, twiddle the appropriate MSR during
initialization to enable x2APIC mode.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
More clearly differentiate MVIC vs. APIC timer code, and use new APIC
accessors in include/drivers/loapic.h. Remove extraneous comments, and
other light cleanup work.
This driver is in need of a serious overhaul -- despite appearing to
have support for TICKLESS_KERNEL and DEVICE_POWER_MANAGEMENT, bitrot
has taken its toll and the driver will not build with these enabled.
These should be removed or made to work... but not in this patch.
Old x2APIC-related accessors in kernel_arch_func.h are eliminated.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Use new x2APIC-aware accessor functions in loapic.h instead of
locally-defined ones. Remove bitrot #defines (no longer used)
and extraneous comments with information from old data sheets.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Simple renaming and Kconfig reorganization. Choice of local APIC
access method isn't specific to the Jailhouse hypervisor.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
drivers/interrupt_controller/i8259.c is not a driver; it exists
solely to disable the i8259s when the configuration calls for it.
The six-byte sequence to mask the controllers is moved to crt0.S
and the pseudo-driver is removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The compiler and linker was generating errors after
disabling `CONFIG_EXTI_STM32` due to inconsistency
in `interrupt_controller/CMakeLists.txt`
and not considering this option in gpio implementation.
Signed-off-by: Maciej Zagrabski <maciej.zagrabski@grinn-global.com>
Add LiteX interrupt controller driver and bindings for this device.
Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Hygiene: We don't query MPtables (anymore?), so the related definitions
in the local APIC driver are unused. Removed.
Signed-off-by: Charles Youse <charles.youse@intel.com>
This adds interrupt support to the SAM0 GPIO driver. This is heavily
inspired by @nzmichaelh work in #5715. The primary difference
from that implementation is that here the External Interrupt
Controller (EIC) is separated out into an interrupt controller driver
that is less tightly coupled to the GPIO API. Instead it implements
more of a conversion from the EIC's own odd multiplexing to a more
traditional port and pin mask IRQ-like callback. Unfortunately,
through the EIC on the SAMD2x are relatively well behaved
in terms of pin to EIC line mappings, other chips that share the
peripheral interface are not. So the EIC driver implements a
per-line lookup to the pin and port pair using definitions extracted
from the ASF headers.
The EIC driver still makes some assumptions about how it will be used:
mostly it assumes exactly one callback per port. This should be fine
as the only intended user is the GPIO driver itself.
This has been tested with some simple programs and with
tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an
adafruit_trinket_m0 board.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Use the RV32M1 SoC intmux driver initialization priority set by
Kconfig. Change the default to match the default value of 40 used
before.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
The existing device_set_power_state() API works only in synchronous
mode and this is not desirable for devices(ex: Gyro) which take
longer time (few 100 mSec) to suspend/resume.
To support async mode, a new callback argument is added to the API.
The device drivers can asynchronously suspend/resume and call the
callback function upon completion of the async request.
This commit adds the missing callback parameter to all the drivers
to make it compliant with the new API.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Converts the rv32m1 interrupt controller driver to use 'DT_' prefixed
defines instead of deprecated non-prefixed defines.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
RTC_Alarm IRQ is mentioned as an exti interrupt in documentation,
so it was available in exti handler.
Though, in Zephyr it is used driectly in RTC driver.
Having it in exti generates and issue when activating RTC driver,
so remove its handling from exti driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
IRQ lines definition in function __stm32_exti_connect_irqs ifdefery
does not match __stm32_exti_isr_x_y functions definitions.
Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This allows the shared_irq driver to be configured by device tree.
With previous implementation, only the board configuration can
override the IRQ trigger, as the trigger config is a "choice" rather
than "config". With this patch, the driver can be fully configued at
the SoC level.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
exti driver implementation does not fit all SoCs because
some EXTI ip does not match stm32_exti register map provided.
Instead of providing exti register map for all SoCs, use LL API
which abstracts IP variations and enable uniform use of the drivers
on all STM32SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Some extensions to the multi-level interrupt controller are required
to support SoCs with more than four level 2 interrupt "aggregators".
Extend existing support to allow at most 8 level 2 or level 3
aggregators. Use Kconfig macro templates to cut down on boilerplate.
Try to clarify some aspects of the Kconfig help while we're at it, and
change the type of options which count things or are table offsets
from "hex" to "int", so that the generated .config is easier to read.
Finally, make some improvements to gen_isr_tables.py while we are
here. In particular, move some assignments around to cut down on
duplicated work, don't check for symbols we know must exist, and
improve the debug logging output's readability.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Complete code factorization in stm32 exti drivers.
Add return value in case line is not implemented.
Except returned error code, refactor has been done iso-feature
compared to previous code. Hence error is reported only when
support was not available on previous series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Modified drivers to use DEVICE_AND_API_INIT() instead of DEVICE_INIT()
This will make sure driver_api,is populated at build time and is exposed
to user space
Signed-off-by: Varun Sharma <varun.sharma@intel.com>
GPIO pin interrupts share common EXTI resources.
Return an error when attempt to configure a line already in use.
Fixes#10611
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.
The only directory excluded directory was ext/* since it contains
only imported code.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.
In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Consistently use
config FOO
bool/int/hex/string "Prompt text"
instead of
config FOO
bool/int/hex/string
prompt "Prompt text"
(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).
The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.
Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
If IOREGSEL register is not accessed with 32 bits, it may not be
intercepted by type 1 hypervisor correctly.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though, and is
inconsistent.
This will make the auto-generated Kconfig documentation have "No
defaults. Implicitly defaults to n." as well, which is clearer than
'default n if ...'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
RISC-V qemu does not use PLIC controller, so plic.c file fails to
compile with qemu target. This change disables plic if qemu is
chosen.
signed-off-by: Karol Gugala <kgugala@antmicro.com>
stm32cube SDK provides defines for IRQ line numbers.
It was not possible to use them, since enum where not supported
by IRQ_CONNECT macro.
Use them in order to get rid of zephyr manually coded IRQ lines.
They will later be replaced by device tree definitions when
made available
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
CAVS_ICTL_0_IRQ_PRI to CAVS_ICTL_3_IRQ_PRI and DW_ICTL_IRQ_PRI
are now defined in Kconfig. This addresses the issue #7811.
This was not throwing up any compilation error earlier as the IRQ
priorities are all hardwired in Xtensa and hence are unconfigurable.
They are dummy for Xtensa arch but may be applicable if used in some
other arch.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.
Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This interrupt controller is a designware IP that combines several
sources of interrupt into one line that is then routed to the parent
controller.
This implementation supports only the regular irqs with no support
for priority filtering and vectored interrupts. Firqs are also not
supported.
Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CAVS interrupt logic is an intel IP that combines several sources of
interrupt into one line that is then routed to the parent controller.
CAVS stands for "connected Audio, Voice and Speech". This IP supports
4 lines which can have a max of 32 interrupts each.
Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The interrupt line number is an unsigned integer; it makes no sense to
compare if it is greater than or equal to 0.
Coverity-CID: 182602
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
In a scenario where a platform harbours multiple interrupts to the
extent the core cannot support it, an interrupt controller is added
as an additional level of interrupt. It typically combines several
sources of interrupt into one line that is then routed to the parent
controller.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
The shared irq support doesn't really require its own dir, lets merge it
into drivers/interrupt_controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:
* different irq stack frame. so need to change the definition of
_irq_stack_frame, assembly code.
* new aux regs, e.g, secure status(SEC_STAT), secure vector base
(VECT_BASE_S)
* interrupts and exceptions, secure mode has its own vector base;
interrupt can be configured as secure or normal through the
interrupt priority aux reg.
* secure timers. Two secure timers (secure timer 0 and timer 1) are
added.Here, for simplicity and backwards compatibility original
internal timers (timer 0 and timer1) are used as sys clock of zephyr
* on reset, the processor is in secure mode and secure vector base is
used.
Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.
By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.
When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.
Here are some outputs of the the command line
$ sudo ./tools/jailhouse cell stats tiny-demo
on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:
Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 7 0
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_xapic 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_msr 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:
- hello_world
- philosophers
- synchronization
The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.
Testing it is just a matter of:
$ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
$ sudo insmod <path to jailhouse.ko>
$ sudo jailhouse enable <path to configs/qemu-x86.cell>
$ sudo jailhouse cell create <path to configs/tiny-demo.cell>
$ sudo mount -t 9p -o trans/virtio host /mnt
$ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
$ sudo jailhouse cell start tiny-demo
$ sudo jailhouse cell destroy tiny-demo
$ sudo jailhouse disable
$ sudo rmmod jailhouse
For the hello_world demo case, one should then get QEMU's serial port
output similar to:
"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""
Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.
As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).
Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.
You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.
Other config differences from pristine QEMU defaults worth of mention
are:
- there is no HPET when running as Jailhouse guest. We use the LOAPIC
timer, instead
- there is no PIC_DISABLE, because there is no 8259A PIC when running
as a Jailhouse guest
- XIP makes no sense also when running as Jailhouse guest, and both
PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
config is set to
This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.
[1] https://github.com/siemens/jailhouse
Reference to Jailhouse's booting preamble code:
Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This will accomodate newer access models later, with variations of those
functions' contents.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
Some our Zephyr tools don't like seeing UTF-8 characters, as reported in
issue #4131) so a quick scan and replace for UTF-8 characters in .rst,
.h, and Kconfig files using "file --mime-encoding" (excluding the /ext
folders) finds these files to tweak.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
* add nested interrupt support for interrupts
+ use a varibale exc_nest_count to trace nest interrupt and exception
+ regular interrupts can be nested by regular interrupts and fast
interrupts
+ fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
+ remove the coressponding kconfig option
+ all interrupts (normal and fast) and exceptions will be handled
in the same stack (_interrupt stack)
+ the pros are, smaller memory footprint (no firq stack), simpler
stack management, simpler codes, etc.. The cons are, possible
10-15 instructions overhead for the case where fast irq nests
regular irq
* add the case of ARC in test/kernel/gen_isr_table
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix doxygen comment typos used to generate API docs
Change-Id: I6fd5051c99bdcc731740c92001e525349c254d85
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows
the riscv PLIC specification as defined in the riscv privilege
architecture specification.
It provides implementation for the riscv PLIC APIs as
required by the riscv-privilege SOC Family for SOCs providing
support for the RISCV_HAS_PLIC config.
Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Current users of sys_bitfield*() are bending over backwards to cast
what is most of the times a pointer into an integer.
Bitfields can be better described with an void *, so
uint{8,16,32,64}_t or any other container can be used. Most
sys_bitfield*() operations, by extension, can do the same. Note void *
has byte arithmetic, like char *.
This change will also make it implicit, for any future split of the
address space between virtual (what the SW is seeing) and physical
(what the HW is seeing) way clearer, as the functions dealing with
physical, non directly referentiable/mappeable addreses to use an
integer type, like mem_addr_t.
- include/arch/ARCH/*asm_inline*:
- sys_bitfield*() all modified to take 'void *'
Note 'void *' arihtmethic is byte based, which makes some things
easier.
- include/sys_io.h:
- introduces DEFINE_BITFIELD
- update docs
- tests/kernel/bitfield: remove all the cast contortions, use DEFINE_BITFIELD
PENDING: update other TCs
- include/arch/nios/nios2.h, drivers/interrupt_controller/ioapic_intr.c:
remove cast contortions
Change-Id: I901e62c76af46f26ff0d29cdc37099597f884511
Jira: ZEP-1347
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to resume the ARC from deep sleep,
the interrupts need to be restored.
The FIRQ stack needs to be saved and restored
when performing sleep operations.
During early initialization, the sp in the 2nd register bank
is made to refer to _firq_stack.
This allows for the FIRQ handler to use its own stack.
Fast Interrupts cannot be used after sleep if this information
is not restored.
This patch adds the suspend and resume functions.
Jira: ZEP-1223
Change-Id: Ic81980f05aee6c1f7b8c46c743f2648c65b29486
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Move interrupt initialization for the ARC to its own
device. The init function for the arc will be only
doing platform specific operations
Jira: ZEP-1288
Change-Id: Icb04c3622890021c65cd24cecf6cafee6c37caf9
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Add EXTI support for the STM32l4XX family.
Change-Id: Ia92f26eaf49899ea23fae05dd3a7357007c9db20
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.
Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.
The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.
The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.
Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.
Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.
States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled
Jira: ZEP-994
Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Some STM32 have more than 32 EXTI lines. Add support for them.
Change-Id: I9a2561664d0d81664acf268bb2257dd99b596a44
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds support for the STMicroelectronics STM32F4x family in the
STM32 MCU line. Configuration is included for the STM32F401RE MCU.
Acknowledgements to Pawel Wodnicki's earlier submission from February that
was used as a starting point for this port. In the end, we rewrote all of it.
Change-Id: I9797c282ac3c0cc66a63b9d34821de95df537ef6
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Move to utilizing an inline function for getting the base addr of the
external interrupt register region. This is in prep for support more
than 32 external interrupts.
Change-Id: Ifdaad67703068395a7749543ef68435435e7c9ba
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Pending bit gets cleared by writing 1 into it, so don't use the previous
value and just write the line bit offset instead.
Change-Id: I4c88016bf53327b2670a144d3b994945f26fc002
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>¬
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Since dd5e90ec the device_get_binding call returns NULL unless the
driver_api is set by the driver. Since the exti driver only uses an
internal struct to store the callbacks, remove the need for the device
binding call from other drivers (e.g. gpio).
Change-Id: If0b733c27754108118d87ef02640311f0535ab57
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
In some cases we can either assume they are already masked
at boot and save some cycles, or the IOAPIC has configuration
from a prior boot stage that needs to be preserved.
Change-Id: I0c71ff0f01a6ee13a3b9c9e239d5a933d6cb6542
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Update the power sample and drivers with the new device driver power
management API using the existing logic
Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
This is a better choice of default; on Mint Valley using IRQ 0
for the timer collides with the DMA Error IRQ line.
Issue: ZEP-849
Change-Id: I14cb60fbe548488198813b2351e0ed1f07c2d07d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
You can't query the LOAPIC for every kind of interrupt that fires,
it has no idea about IRQs that were generated by an 'int' instruction
for example. Extend the semantics of _irq_controller_isr_vector_get()
to return -1 if the vector can't be identified.
Issue: ZEP-602
Change-Id: I1174aa62fbedffdcd329d60da8ef14fabb042dc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments state that higher-numbered vectors have priority,
but the function was doing the opposite. The code now agrees
with the comments.
Change-Id: I1a689fc22c8355458bdd734d95ff637da0655533
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The code was setting the interrupt priority to 1 for each
vector to start. But I think it might be more appropriate
to set it to the LOWEST priority. Some ARCs will have
upwards to 15 priorities.
Change-Id: I9330ec8df323fe04ba0751faaafa39694f012364
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Provide functions of saving and restoring LOAPIC
states to support deep sleep.
Jira: ZEP-223
Change-Id: I1fb427989b021ec8e3a4f6dd0f4766a214360621
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Save and restore IOAPIC flags and irq to vector translation
info for supporting deep sleep.
Jira: ZEP-223
Change-Id: Ifc50a5a72699ff6782ad194d8e96b18fac34da18
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
In scenarios where device PM is enabled and dynamic irqs are
used, move the irq to vector table to RAM and keep it updated,
so that we can use this to restore IOAPIC/LOAPIC vector entries.
Jira: ZEP-224
Change-Id: I0d4350d4e30f8ca337a2a1d4f012748c3cb450f4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Some ARC targets can have a data-cache. Although there is no special
instruction to clear exceptions during early init, it is necessary to
invalidate the d-cache BEFORE any data is fetched. The ARC on arduino 101
doesn't have d-cache, and will thus skip this d-cache invalidate.
Also, it is important to set the vector table base register to point to
the interrupt vector table EARLY, so that if an exception is encountered,
the correct vector table is found. Set this base only if it is found to be
different from the one compiled in to the code.
These initialization steps assure that proper exception handling
is in place during early init.
Change-Id: Ie8b5928e5813e104680a6d6510c85d32dc8ed8f3
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.
Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use CONFIG_SOC_FAMILY for the top level SoC family. A family
will have different SoCs or different SoC series with multiple
SoCs.
Adding the Family string to the config variable to avoid confusion
between actual SoCs and families and to prevent name collisions.
Change-Id: Ic99a2c1df7850dee3a45641027af82464dd6fadb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introcuce a driver for External Interrupt/Event Controller (EXTI) found
on STM32 MCUs.
Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Make this explicit to conform to the abstraction layer
defined in include/irq.h
This only worked before because the preprocessor was
substituting the function prototypes.
Change-Id: Id4d46b01f1c53c3a942772640023e23796eeb43b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.
Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.
It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.
In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
generate_interrupt_vector_bitmap() also ensures that there are
sufficient free vectors within a priority level.
Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Use a real board name that can run this kernel instead of a generic
name. Basic functionality exits on this board with Zephyr.
Setup of the board is mostly similar to what we have in galileo (EFI
based)
Change-Id: Ic8554f26dcac0dbbbb6d35d863482f6207dc63c5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
MVIC has only one local interrupt: the timer IRQ. What IRQ line
to use is not fixed, instead it is programmed into the LVTTIMER
register. This is unlike LOAPIC which has a fixed IRQ for the timer
and instead the *vector* to use for it is programmed into LVTTIMER.
We don't want _loapic_int_vec_set() to do anything as the relationship
between IRQ lines and vectors is fixed and we do not want to be
programming vector numbers into bits 0-3 of LVTTIMER.
The IRQ line to use for timer interrupts is programmed into LVTTIMER
when the MVIC is initialized.
Change-Id: Icba0429f65ece7541fa8542814a8fdc39ad43936
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE Lakemont core has a hardware bug where the LOAPIC does
not properly notify the IOAPIC to clear the IRR bit for level-
triggered interrupts.
This patch introduces a workaround where the vector ID of the
in-service interrupt is manually written to the IOAPIC_EOI
register, resulting in the bit being cleared.
Unfortunately, in the context where EOI happens it's very difficult
to identify which IRQ line is being serviced, so this is done
unconditionally for all interrupts vectors whether they are registered
in the IOAPIC RTE table or not.
Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A special situation may occur when a processor raises its task
priority to be greater than or equal to the level of the
interrupt for which the processor INTR signal is currently
being asserted. If at the time the INTA cycle is issued, the
interrupt that was to be dispensed has become masked (programmed
by software), the local APIC will deliver a spurious-interrupt
vector. Dispensing the spurious-interrupt vector does not affect
the ISR, so the handler for this vector should return without an EOI.
Change-Id: I4cf4744bd6efd68b72e2c380269de4181dc80bd9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was only needed for an older implementation of software interrupts,
now superseded by the irq_offload() API (which doesn't interact with
the interrupt controller at all)
Change-Id: I8aa696d370ae1799872f6d70de69f3cb5b47456a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Those empty C files are there because the current Kbuild
requires Makefile to be present at those directories,
(due to arch/x86/Kbuild), which requires building some object
files. So the empty source files are there to produce empty
object files to satisfy this.
Change-Id: I14056347ea14cff227d9e8960192e8673c0019b8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1d379068f64855d5d4595838040ec50f97f638a0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1af8b2888779b2b58367feaff9ee1a6d97b4873c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The kernel event logger requires this function to obtain
the irq that is being processed, but this was not implemented
for mvic. This patch add this function to mvic.
Change-Id: I5e1b4a6e2758b69ec713c18ac9f78aebad18a93f
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This module is based on the standard Local APIC and IO APIC source modules.
This modules combines these modules into one source module that exports the
same APIs defined by the Local APIC and IO APIC header modules. These
routine have been adapted for the Quark D2000 Interrupt Controller which has
a cutdown implementation of the Local APIC & IO APIC register sets.
Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
