A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Currently all IO APIC interrupts are configured at fixed delivery mode,
which is good for HEPT timer interrupt but it imposes burdens to
device drivers to properly handle the repeated interrupt sent to all
processors.
This patch makes it more flexible so that device drivers can specify
the delivery mode it desires in the IRQ connect APIs.
- Don't hard code IOAPIC_FIXED in z_ioapic_irq_set(), meaning the
IRQ delivery mode is passed in from the 'flags' argument and
individual device driver needs to choose delivery mode for its own
IO APIC interrupt.
- To support different delivery mode in different IO APIC interrupts,
need to save and restore RTE[10:8] during IOAPIC suspend and resume.
If device driver doesn't pass either IOAPIC_FIXED or IOAPIC_LOWEST
in IRQ_CONNECT()/irq_connect_dynamic() alike APIs, the delivery mode
bit fields in the target RTE register are '0' which implies fixed mode.
If the device driver wants the interrupt to be delivered to one CPU
only, it needs to explicitly specify IOAPIC_LOWEST in one of the IRQ
connect APIs.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Currently IO APIC is working in physical destination mode, which
doesn't support interrupt to be delivered to multiple local APICs.
By definition only 4 bits [59:63] in IO APIC IOREDTBL register are
available for destination addresses and it contains an APIC ID only.
This patch changes it to logical destination mode so that IOREDTBL
can potentially define a set of processors and it's posible to deliver
interrupts to multiple APICs.
Signed-off-by: Zide Chen <zide.chen@intel.com>
The '_' is not necessary, plus it makes the sys init object name
aligning with all others.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Currently IO APIC is working in physical destination mode, which
doesn't support interrupt to be delivered to multiple local APICs.
By definition only 4 bits [59:63] in IO APIC IOREDTBL register are
available for destination addresses and it contains an APIC ID only.
This patch changes it to logical destination mode so that IOREDTBL
can potentially define a set of processors and it's posible to deliver
interrupts to multiple APICs.
Also it changes delivery mode from fixed to lowest priority. The reason
being in fixed mode, the interrupt could be delivered to all CPUs
which put burden in software to handle repeated interrupts. While in
lowest priority mode, interrupt is delivered to one local APIC only.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Pattern being <domain>_<model>.<c/h>.
Here interrupt_controller as a domain would be far too long so
shortening it to "intc", as DTS does actually.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-12-18 21:49:46 +01:00
Renamed from drivers/interrupt_controller/ioapic_intr.c (Browse further)
