Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occur.
A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the
previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
