The lr and sr instructions cause a pipeline bubble. There is an efficiency
to be gained if pairs of lr or sr instructions are done right next to
each other. This can avoid some stall cycles.
Also, r14 and r15 can be used with isa-16 instructions.
Change-Id: I4165365b49da910db31e0699a1a6e47114962942
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Some ARC SOC implementations will need CONFIG_HARVARD so as to
select a different initial stack pointer (one at the top of DCCM memory),
and also to select a different linker command file that uses
ICCM and DCCM. Quark_se_ss will have HARVARD equal to n.
Change-Id: Idb7c4126866c9604e1924200ad5fdd2bc9d28269
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The timer implementation for ARC currently requires timer0 to be present.
I've added a comment that this is an assumption and to encourage developers
to build the ARC CPU with Timer0, when it is to be used with Zephyr.
There is also an optional provision for a Timer1. In future, this
code could be conditional to use either timer.
Change-Id: I4eb3aec59ba4e85f8b70d5531b21bdaab00b93bb
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
By using isa-16 instructions, a bit of code-size can be saved,
and code can be a little faster.
Change-Id: I0567d8274372748f579610e2bd4236ce52c5d6c8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The ARC CPUs have several other features controlled by aux registers.
Specifically, I will be needing ones for i-cache, d-cache and various
BUILD registers that indicate which features are present.
Change-Id: If15a330f4ea5aa519655f88526fbb5f600d7cc0b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Nios II has no special instructions for testing bits, ffs, etc.
However, when poking memory-mapped peripherals, special *io variants
of ld and st instructions must be used to avoid issues with the
caches.
find_msb_set / find_lsb_set are implemented using universal GCC
compiler built-ins. It's not clear why this approach was not taken
on other arches.
The sys_in/sys_out/sys_io functions are completely removed as there
is no concept of these on Nios II.
sys_read/sys_write functions implemented using special GCC builtins
for the Nios II so that we don't have to use inline assembly.
Rest of the operations implemented in C, there is no requirement that
they be atomic.
Change-Id: Ic251fc7d7f342543dace4ccb3e429937b303215e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Although it's unclear why x86 has a different naming convention,
this scales better.
Change-Id: I939b9d4d04b1833391304700a7c12c9c8607192f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Now matches kernel/nanokernel/include/nano_internal.h.
Change-Id: I4dbbf50aa05c55de42100a6896fe0fa3b26955ec
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This file is taken verbatim from the Altera Nios II HAL
source and includes various useful processor defines
and macros.
Change-Id: Idbf0b49bebe33bb5a53f5155d927bafadda9a2fe
Origin: nios2.h Altera Nios II HAL
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.
Include these files from <arch/cpu.h>.
Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Got lost in the .gitignore when these files had .cmd
extension.
Change-Id: I8a8d51014b621026b739525f3f9a3e8a20cb5ad0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ZEP-252 will handle implementation of the code here.
Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.
vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.
Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When pairing procedure ends regardless of the status, reset flags
strictly related to pairing phase and reset security level.
Thanks that next authentication will get known initial pairing 'context'.
Change-Id: Ie3108c6e28e136ea929e564a6820675cc770cb95
Signed-off-by: Arkadiusz Lichwa <arkadiusz.lichwa@tieto.com>
Fixes using uninitialized structure nble_gattc_write_param in
nble_gattc_write_req().
Change-Id: I476a3b833994c422691bf96dc0b2174368c47fa6
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Since RPC to the Nordic BLE module has no flow control increase
receive buffer pool to handle events from the module. Without this
NBLE stack is not capable of handling all events and we get "No
buffers" error message.
Change-Id: I0566b30a95ef0a027d4533c83c3c2915018a650a
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
on_nble_gap_connect_evt() gets called in a case of incoming connection
but also with outcoming one. In this case connection is already
created so we should use conn_get() instead of conn_new().
Change-Id: I2ed2d0a1844f653000a12eb0f54f52533856bf0d
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Using send_sync lets us return an immediate error to the application
if the HCI command fails. This also reduces the pressure on available
buffers since we don't allocate multiple command buffers before
starting to process the command queue.
Change-Id: I5613e4e9dd8dcc0db45bad051d7c4980b49e428d
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There is no need to open code this as we have helper for this.
Change-Id: I77ab39206d0c5b10f30624e90e864192b9519d0c
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
If adapter is using Static Random address as Identity Address and
privacy is disabled we need to restore correct random address (ID)
before creating connection. Otherwise NRPA used for active scan
could be used resulting in SMP confirmation failed due to invalid
initiator address being used.
Change-Id: I7201890ab9475ade3a825f9ea791a30af6b657a5
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
Update RPC following major RPC update in firmware.
Change-Id: I4094b94319359a59164ac69394937ac1472b8cbe
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Code size can be reduced by replacing ld and st
with ld_s and st_s (if target registers are r0-r3).
Change-Id: Ia70f0aff07fe41a0cfeff2d59dcdadf7c88e1ae8
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
code-size optimization to use small-variant loads/stores with %r13w
Change-Id: Ic9b2b7744f7d465bccb1e59f64e621985ae7d04d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
This test has been broken since we've moved from object IDs being
small integers to pointers. The problem was two-fold:
- The semaphores are not put in a an array anymore, and are thus not
necessarily referenced. The linker drops them in that case.
- The semaphores are not necessarily allocated in memory in the order
they are defined in the mdef file. On x86 actually, they are
allocated in the reverse order.
There was no need anyway of having all those semaphores: the microkernel
semaphore is a counting semaphore. It can thus simply be given a number
of times anre taken the same number of times to operate on it a
reasonable amount of time to take a measurement.
Change-Id: I67c82cb7eb03d28906f8c63717db8f951818be5e
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
There is a BUG here in that the alias for __start was
aliased to the start of the vector table. Yet, on ARC CPUs,
the vector table CANNOT be the entry point, because there
is no code in a vector table. Only addresses appear in each vector.
Thus, the reset vector, at offset 0 in this table, is a raw address.
The top Makefile in zephyr sets the lable __start to be the entry point
like this: -e __start. Debuggers, for example, use this entry point
to know where the first line of code is.
Also, in KConfig, there were duplicate NSIM blocks. One has been
removed.
Change-Id: I480be7d338a8b45b8ea6ef3f55ac2e6c43829452
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Looks like this snuck in with the GPIO API migration.
Change-Id: Ib58142e134a779431bacf9ca75a66541bf63d5b0
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
A recent issue due to a change to ARC was not caught because we
do not build on ARC. Now that we have libc with ARC toolchain,
built for all arches.
Change-Id: I8c9b7d37802cb582dcb50e6c61d040078d8ecd26
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The RAM config symbols need to be updated as they were named by the
commit:
1a1f7fd arc: make SRAM/DCCM values configurable
Change-Id: Ieeb06de2f77b4c9e10a0bc32d8318834ce150f5e
Signed-off-by: Bogdan Davidoaia <bogdan.m.davidoaia@intel.com>
Both initiator and responder addresses are already set during
connection creation so there is no need to set responder address
again.
Change-Id: Id477a9e6dd2244c57126d1f985aa41cd1b04650b
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
New connection needs to be added only for slave role. For master
connection object is created when LE Create Connection is send.
Change-Id: I24dbfc4b3a647ea230b199fbec09940f486b983f
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
set_ad() already checks for length==0 so there is no need for
checking if sd is valid.
Change-Id: Idc0ce9135eca56a1e8057f3a2129adb0b5e5ddd7
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
It is useful to have the shell emit the zephyr version number.
Output looks like this:
Zephyr version 1.3.0
shell>
Change-Id: I2608272564a5d2fe39f263c420a897d845457a98
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
There seems to be no way to configure it, so I've just removed the code.
Change-Id: I35341e8afc0bdfa8b953b833cfb0eecf05b81c16
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
In order to build test/kernel/test_stackprot/microkernel for the ARC,
the _MOVE_INSTR needs to define what the move instruction is for this
target.
Change-Id: I087cc5baa4c41297ce52323556e94aab424aa891
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The filter specification now matches the code. We can run on any x86,
or those ARM boards where the test's timestamp.c has _Timestamp*
implementations.
Change-Id: Ib81e5379f892beb3783dd3c345cd536c883a74de
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The old 'config_whitelist' directive in testcase.ini has been removed.
We use the new expr_parser module to parse a 'filter' directive which
is a boolean expression. This gives a great deal more flexibility
in how tests can be filtered.
To keep the tree bisectable, use of config_whitelist in testcase.ini
converted to the new expression language.
Change-Id: I0617319818c5559c0f0569d2fa73d09b681cac51
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
