Add device tree bindings for the Semtech SX1261 and SX1262
radios. These will be used by Zephyr's LoRa drivers.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Use '0xa0' as default priority to be consistent with the V1/V2 and
V3 drivers default priority init.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit removes API functions and macros which were deprecated in
2.2 release. GPIO drivers are updated accordingly.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
- Support PLL for Higher Frequencies 80,160,240 MHz
- Support XTAL Frequencies 26MHz, 40MHz
- Clock Driver can't be disabled, because all of the other drivers
will depend on it to get their operating Frequency based on chosen
clock source (XTAL/PLL).
- Add needed references to BBPLL i2c bus ROM functions.
- Add `rtc` node to Device Tree.
- Since All Peripherals Frequency is depending on CPU_CLK Source,
`clock-source` property added to CPU node
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
This defines the configuration for the DMA client
as specifed in the ./dts/bindings/dma/st,stm32-dma.yaml
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When configuring the I2S peripheral as a master, the DMA channel
direction must be configured to transfer data from memory to the
peripheral.
Currently the configuration of channel direction is always set for
peripheral to memory regardless of whether it is the TX or the RX
channel.
Signed-off-by: Abe Kohandel <abe@electronshepherds.com>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
GPIO_DIR_OUT is deprecated but allowed in devicetree bindings because
some in-tree bindings provided it in the past. GPIO_DIR_IN was the
former explicit way of representing the default direction. Put it
back so symmetry is maintained.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Extend the physical level GPIO_OUTPUT_{HIGH,LOW} configuration with
GPIO_OUTPUT_{ACTIVE,INACTIVE} for logic level initialization.
This enables use of device-tree configuration flags in calls to
gpio_pin_configure() to set the logic level without having to
determine the corresponding physical level.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
gpio_pin_interrupt_configure() is invoked from within
gpio_pin_configure() to support legacy code that combines pin and
interrupt configuration. Expressing a disabled interrupt by a zero
value for interrupt flags causes this invocation to disable interrupts
when the intent is to change only a pin configuration, such as pull
direction.
Support a distinction between explicitly disabling interrupts and
leaving the interrupt configuration unchanged.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit makes following changes to GPIO dt-bindings flags:
- Added GPIO_ACTIVE_LOW, GPIO_ACTIVE_HIGH to indicate pin active state.
- Added GPIO_OPEN_DRAIN, GPIO_OPEN_SOURCE to configure single ended pin
driving mode.
- Added GPIO_PULL_UP, GPIO_PULL_DOWN flags.
- GPIO_INPUT, GPIO_OUTPUT to configure pin as input or output.
- Added GPIO_OUTPUT_LOW, GPIO_OUTPUT_HIGH flags to initialize output
in low or high state.
- reworked GPIO_INT_* flags to configure pin interrupts.
- following flags were deprecated: GPIO_DIR_*, GPIO_DS_DISCONNECT_*,
GPIO_PUD_*, GPIO_INT_ACTIVE_*, GPIO_INT_DOUBLE_EDGE, GPIO_POL_*.
To be aligned with Linux DTS standard any GPIO flags that should not be
used in DTS files are moved from include/dt-bindings/gpio/gpio.h file to
include/drivers/gpio.h with an exception of several old flags which
removal would cause DTS compilation errors. Those remaining old flags
will be removed from include/dt-bindings/gpio/gpio.h at a later stage.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This patch introduces the periph to/from memory dma transfer
define new values for dma cells on client side
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for requesting an inverted PWM pulse (active-low) when
setting up the period and pulse width of a PWM pin. This is useful
when driving external, active-low circuitry (e.g. an LED) with a PWM
signal.
All in-tree PWM drivers is updated to match the new API signature, but
no driver support for inverted PWM signals is added yet.
All in-tree PWM consumers are updated to pass a flags value of 0
(0 meaning default, which is normal PWM polarity).
Fixes#21384.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To work efficiently, SPI_NSS pins require pull-up configuration.
Fix this for whole STM32 series.
Fixes#17998
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The GIC400 is a common interrupt controller that can be used with the
Cortex A and R series processors. This patch adds basic interrupt
handling for the GIC, but does not handle multiple routing or
priorities.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Add enum to list what values of maximum-speed are exceptable since
enum's get represented as strings in DT. This also allows us to
generate a code enum to correspond to the string.
We also introduce include/dt-bindings/usb/usb.h which is a hand coded
definition of the enum. We don't have a great way to generate this
right now, however it would be better if we did.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If a UART is configured with IRQ == PCIE_IRQ_DETECT, then use the
pcie_wired_irq() to determine the IRQ at runtime, and install the
handler using the dynamic interrupt mechanism.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.
As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).
This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.
The settings are defined at devicetree level and applied in the soc.c.
A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
The mcux sim clock control driver was originally designed to pass
through the clock subsystem value from dts to the mcux CLOCK_GetFreq()
function. This assumed that the values in
include/dt-bindings/clock/kinetis_sim.h matched the enumeration in
fsl_clock.h, which is true for the coresys, platform, and bus clocks.
However, the low-power oscillator (LPO) clock has a different values in
k64 vs. kw2xd, therefore we must update the clock_control driver to
parse the value from dts and convert it to the fsl_clock.h enumeration.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Create a dt-bindings/gpio.h file.
Bindings definitions are extracted from existing gpio.h.
gpio dt-bindings file is required because existing gpio.h file could
not be parsed by dts parser.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds device tree bindings for the Kinetis System Integration Module
(SIM), and defines peripheral source clocks (e.g., system clock or bus
clock) and clock gates for all Kinetis SoCs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Clarify that the clock-frequency is the bitrate at boot and introduce
defines that .dts files can use to set the clock-frequency.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32 pin configuration comments where offset by 4 bits.
Fix this issue and make pin configuration settings
easier to read.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
