In some hardware, e.g. ARC HS Development kit,the peripheral
space of DesignWare SPI only allowes WORD access,
byte acess will raise bus error.
This commit adds support for this case
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Consistently place C++ use of extern "C" after all include directives,
within the negative branch of _ASMLANGUAGE if used.
Only updated in headers that already had support for drivers built with
a C++ compiler.
The spi_dw.h file defines macros to declare functions, then uses them
within a file that may have out-of-tree overrides. In this case we
leave the including file extern "C" active for backward compatibility.
Background from issue #17997:
Declarations that use C linkage should be placed within extern "C"
so the language linkage is correct when the header is included by
a C++ compiler.
Similarly #include directives should be outside the extern "C" to
ensure the language-specific default linkage is applied to any
declarations provided by the included header.
See: https://en.cppreference.com/w/cpp/language/language_linkage
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
move spi.h to drivers/spi.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Logical or is unsufficent for setting up new tmod: it's required to
remove previous one first. Indeed, 0 as tmod is valid (tx-rx mode), but
previous tmod could be 10 or 01, so a logical or will keep the previous
tmod leading to a bogus transaction.
Fixing also a rebase issue visible when debug mode is enabled. Slave
callback is a left over from a test on spi slave.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It involves a minor change on which register is configured.
Most of the change is with threshold handling.
Handling the Kconfig based supported mode per-port.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As for RX only, computing the NDF will be used for EEPROM mode.
Only a way to determine EEPROM mode is missing.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removing internal boolean in order to use the proper error code hold in
spi_context which was relevantly added in commit 6c717095b8.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All SPI drivers have this same way to handle synchronous call, thus
let's generalize it in struct spi_context, with a relevant API and apply
the change into SPI DW driver.
spi_context API will prove to be useful once asynchronous call will be
handled as well, through the same completion functions used now only for
synchronous call. It will be transparent for the driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introducing as well a generic driver helper for CS gpio control and
buffer management.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Device sync APIs are actually wrappers for semaphores.
Let's replace them with semaphores.
Jira: ZEP-1411
Change-Id: I02c7cba21d21ff9288e452121e3b7ebb7d251bb4
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
The TX fifo threshold is pretty arbitrary.
Set this too big and too many interrupts will occur
for no good reason. Set it too small, and latency
in the SPI transactions is introduced. User's will probably
have to tune this per their application and SPI frequency, etc.
I think setting this to 50% is a good guess for now.
Change-Id: Ib325d40bc7ee10473d99443b3b3cd00fd6e4b95f
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
I've found many problems with the SPI driver and this repairs many of them.
The baud rate divisor was being derived from the CPU clock. But, some
targets may have a seperate clock attached to SPI. If the soc.h file
defines the symbol SPI_DW_SPI_CLOCK, it will use this instead
of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for the baud rate calculation.
completed() had a mistake where it would terminate the SPI transaction
too early, well before the tx data has cleared the FIFO. I found I couldn't
drive an OLED display correctly because completed() was wrong.
The repair is to now consider a new flag called spi->last_tx,
which will be set after the TX interrupt occurs with nothing to send any
longer. There is also a while loop added to SPIN until BUSY drops.
Another improvement is that push_data will NOT consider RX fifo size
if there is no RX going on. The calculation here when RX is going on
could go negative. I've added a check for that and prevent TX handling
if RX buffer is full. I think that is the intention -- to deal with RX first
if its fifos are more full.
In spi_dw_transceive, if we are only doing spi_write w/o reading,
don't enable RX interrupts at all. The OLED I'm working with failed
to have a pull-up on MISO SPI signal. As a result, a huge number of
garbage RX events arrive, and the interrupt handler finds there is
no rx buffer, so it tosses the data. But this is a waist of realtime.
It seems WRONG to enable RX interrupts if its something your not using,
so software can GATE these spurious events in this way.
With these changes, SPI can be used much more reliably, with FIFOs
that are deeper, and SPI devices that only require TX.
Change-Id: I0fe0745f2381c61c8a19ce086496b422a32a30a5
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
When using the Synopsys DesignWare Synchronous Serial Interface (SSI),
the FIFO depth can vary from 2-256, depending upon how this module is built.
For quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be
32. Adding this now as a configurable option. A larger FIFO really helps
reduce SPI interrupts.
Change-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
There's no reason to require callers to cast their data to uint8_t *
when the data might e.g. originate in a packed struct or some other
data type. Instead, be nice to callers and let them use any pointer
they want. Additionally, declare the TX buffer as a const pointer so
unnecessary typecasts aren't needed for that either (if the data
originates in a const location).
Change-Id: I1482ca4e350b5a7fbda6871ed9f54f255af3aa9e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Though it's an ARC core, Quark SE SS does not follow the same registers
mapping as the official DesignWare document. Some parts are common, some
not.
Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole
new driver though the logic is 99% the same, it's then better to:
- centralize common macros and definitions into spi_dw.h
- have a specific spi_dw_quark_se_ss_reg.h for register map, clock
gating and register helpers dedicated to Quark SE SS.
- have a spi_dw_regs.h for the common case, i.e. not Quark SE SS.
GPIO CS emulation and interrupt masking ends up then in spi_dw.h.
Clock gating is specific thus found in respective *_regs.h header.
Adding proper interrupt masks to quark_se_ss soc.h file as well.
One of the main difference is also the interrupt management: through one
line or multiple lines (one for each interrupt: rx, tx and error). On
Quark SE Sensor Sub-System it has been set to use multiple lines, thus
introducing relevant Kconfig options and managing those when configuring
the IRQs.
Quark SE SS SPI controller is also working on a lower level, i.e. it
requires a tiny bit more logic from the driver. Main example is the data
register which needs to be told what is happening from the driver.
Taking the opportunity to fix minor logic issues:
- ICR register should be cleared by reading, only on error in the ISR
handler, but it does not harm doing it anyway and because Quark SE SS
requires to clear up interrupt as soon as they have been handled,
introducing a clear_interrupts() function called at the and of the ISR
handler.
- TXFTLR should be set after each spi_transceive() since last pull_data
might set it to 0.
- Enable the clock (i.e. open the clock gate) at initialization.
- No need to mask interrupts at spi_configure() since these are already
masked at initialization and at the end of a transaction.
- Let's use BIT() macro when relevant.
Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
It might be necessary to emulate CS through a GPIO pin depending on
these 2 conditions:
- the controller's CS pin is not wired, and thus a GPIO pin is the only
option
- The controller is unstable at a certain frequency and cannot set/unset
CS reliably. This is actually a possible issue on DesignWare's SPI
controller in Quark SE or Quarks D2000 where it has been found
unstable at 1Mhz and above.
Change-Id: Ib6a06577906c005ddd347070d476a367a9c3da8a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Refine how DFS is calulated now that it is strictely used to
manipulate buffer lengths.
- Fix threshold limit
- Tune RX threshold relevantly (reduce it if rx_len is lower than actual)
- Don't push more than available left space in FIFO
- Tune the private structure to lower memory space occupation
Change-Id: I65b1b48b996b2104cebcb24cc366fb4dcbf7d53b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IMR and ISR bits are same, but it stil better to differentiate them
properly. Also fixing naming where all ISR ends with an 'S'.
Change-Id: I2fc1e1d8d2743c3d98f5da40a5f4720a85c4f9a7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Registers offsets are hopefully all the same, but size differs.
On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w.
And DFS on 32 bits support is placed differently as well.
Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Only 8 bit frames were supported. Added support for bigger data frames
which can go up to 32 bits (on 32bits version of the controller, 16 bits
otherwise). Store the frame size in bytes during configure, and use it
during pull/push to read/write correct frame size.
Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
