Commit graph

3813 commits

Author SHA1 Message Date
Marti Bolivar
7425195a25 arch: riscv32: fix INCLUDE_RESET_VECTOR Kconfig help
The generated stub doesn't actually initialize the CPU or jump to
__start. All it does is set up the interrupt stack and jump to
_PrepC. Fix the help.

Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-12-04 22:54:23 -05:00
Marti Bolivar
0b234f2518 arch: riscv32: fix fatal.c build without printk
If CONFIG_PRINTK=n, cause_str will not be defined, and _Fault() will
fail to build. Fix that by ifdeffing out the printk call in that case.

Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-12-04 22:54:23 -05:00
Patrik Flykt
494ef1cfe2 arch: Add 'U' to unsigned variable assignments
Add 'U' to a value when assigning it to an unsigned variable.
MISRA-C rule 7.2

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-12-04 22:51:56 -05:00
Aurelien Jarno
d941df7ea7 arch: ARM: set -mabi and -march in linker flags
Some toolchains are built with multilib enabled in order to provide
multiple versions of the same library, optimized for different ABI
or architecture. They require the -march= and -mabi= options to be
passed at link time. This is important for example when linking with
newlib.

We do that by passing zephyr_ld_options the same arguments than
zephyr_compile_options. The -mabi option is passed directly while the
-march option, if defined, is passed through ${ARCH_FLAG}.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-12-04 19:40:39 -05:00
Aurelien Jarno
6fd1691b94 kernel: Add a "nocache" read-write memory section
Add a "nocache" read-write memory section that is configured to
not be cached. This memory section can be used to perform DMA
transfers when cache coherence issues are not optimal or can not
be solved using cache maintenance operations.

This is currently only supported on ARM Cortex M7 with MPU.

Fixes #2927

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-12-03 09:54:31 -08:00
Flavio Ceolin
6e1f6e5d5d arch: x86: Make if statement evaluate a boolean expression
MISRA-C rule 14.4

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-30 08:05:11 -08:00
Ioannis Glaropoulos
80d38788fc arch: arm: utilize Kconfig option for min ARM MPU region size
The commit enforces the use of ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
in include/arch/arm/arch.h, instead of using 32 as a hard-coded
value. The symbol is also used in arm/thread.c to truncate the
thread stack size to satisfy MPU granularity. The commit does
not introduce behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-11-30 15:22:58 +01:00
Ioannis Glaropoulos
6bbb8273d2 arch: arm: Kconfig option for minimum MPU region size and alignment
The commit introduces a Kconfig option to define the minimum MPU
region size and alignment for ARM Cortex-M MCU architecture. The
hidden option is used by the linker to properly align linker
sections respecting the MPU requirements. Additionally, it is
used to define MPU Guard size and minimum stack alignment for
ARM Cortex-M MCUs in include/arch/arm/arch.h .

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-11-30 15:22:58 +01:00
Flavio Ceolin
001ad8b6c2 arch: Making body of selection statement a compound statement
MISRA-C rule 15.6

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-29 14:21:29 -08:00
Flavio Ceolin
46715faa5c kernel: Remove _IntLibInit function
There were many platforms where this function was doing nothing. Just
merging its functionality with _PrepC function.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-28 14:59:10 -08:00
Marti Bolivar
5ec7ed8bbf arch: suspend CONFIG_SOC's doomsday
This option is useful to have for a flatter hierarchy for one-off SoCs
that aren't split into family and series from the silicon vendor
perspective.

The commit saying it was going to go away is from 2 years ago; it
hasn't happened and it doesn't seem to need to happen. Just delete it.

Signed-off-by: Marti Bolivar <marti@foundries.io>
2018-11-21 18:37:46 -05:00
Ioannis Glaropoulos
8204ecbead arch: arm: mpu: declare and define arm_mpu_config as const
Declare and define arm_mpu_config and arm_mpu_regions
structs as const, as they are not modified in run-time.

Fixes #10320

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-11-21 09:44:21 -05:00
Kumar Gala
41e43111dc cmake: Remove global include of board dir
Remove having ${BOARD_DIR} in the global include path for Zephyr builds.
Needed to add this to the arch/posix because of how posix "boards"
define various things like interrupt handling.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-20 14:08:01 -05:00
Patrik Flykt
f8cbf7f92a arch/arm: Avoid C++ comments inside C comments
Avoid nested C++ comments inside the C comment block due to MISRA-C
rule 3.1. Keep the variables documenting possible caller saved
registers.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-11-15 17:38:25 -05:00
Patrik Flykt
66a4a11836 arch/xtensa: Use C style comments
Update comments to follow C style.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-11-15 17:38:25 -05:00
Patrik Flykt
8d769d5533 arch/xtensa: Remove identifier looking as mixed C/C++ comments
The identifier looks like a mixed C/C++ comment, which is against
MISRA-C rule 3.1. As the identifier is not used, remove it altogether.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-11-15 17:38:25 -05:00
Michael Scott
36b93e121f gen_isr_tables: remove hard-coded max IRQ value of 32
In the MULTI_LEVEL_INTERRUPTS Kconfig we have a symbol for defining
the maximum IRQ per aggregator: MAX_IRQ_PER_AGGREGATOR

Instead of using a hard-coded value of 32 max irq per level,
let's use the value of MAX_IRQ_PER_AGGREGATOR

Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-14 21:14:14 -05:00
Michael Scott
28fe29dd36 gen_isr_tables: fix check for CONFIG_3RD_LEVEL_INTERRUPTS
If CONFIG_3RD_LEVEL_INTERRUPTS is not enabled then we see the following
error during sw_isr_table generation:
Traceback (most recent call last):
  File "zephyr/arch/common/gen_isr_tables.py", line 291, in <module>
    main()
  File "zephyr/arch/common/gen_isr_tables.py", line 199, in main
    if syms["CONFIG_3RD_LEVEL_INTERRUPTS"]:
KeyError: 'CONFIG_3RD_LEVEL_INTERRUPTS'
ninja: build stopped: subcommand failed.

Fix the logic to look for the symbol instead of referencing it.

Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-14 21:14:14 -05:00
Andy Ross
23159cedec xtensa legacy: Fix stale use of removed kconfigs
The old xtensa layer had an unused/untested facility where it would
apparently try to slave a timer tick to an arbitrary interrupt.  The
legacy headers were still checking the kconfigs used to enable that
even though nothing wants it and the new driver has removed them,
breaking builds on platforms like S1000 that still use the older
layer.

Don't try to finess this as these files are going away.  Just make
them local preprocessor symbols and set them to the default values
they always had.

(Note: the feature doesn't sound like it would have been so bad,
actually.  We should probably crib that idea of having an
"external_tick" driver, but there's no reason for it to have been
arch-specific.)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-14 19:08:27 -05:00
Andy Ross
d411514a5f xtensa: Don't call ISRs for disabled interrupts
Xtensa interrupts are handled generically, by testing a set of flagged
interrupts in the INTERRUPT register.  It's not possible to know
exactly which device "caused" an interrupt.

The entry code was dispatching correctly, but it was failing to test
the enable state in INTENABLE.  Such an interrupt will never "fire",
but it might still be flagged, and if we happen to end up handling an
interrupt of the same priority (due to some other device) the entry
handler would incorrectly invoke the disabled interrupt.

Found by dumb luck and a comedy of errors: the recent timer driver
change swapped the counter in use, which changed the interrupt number
to one shared with the I2C driver, whose early interrupts (odd that
this device is interrupting on boot when not in use, but whatever)
would then discover the OTHER timer counter had been flagged and try
to invoke an ISR for that other counter, which was the _irq_spurious()
spurious interrupt handler.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-14 19:08:27 -05:00
Andrzej Głąbek
20202902f2 dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig
These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Andy Ross
0670ba6c92 xtensa: Disable interrupts on entry to _Cstart
Zephyr isn't ready to handle interrupts yet, until the
threading/scheduler are set up and we make our first context switch.
This was a semi-hidden bug: only the timer interrupt would actually
get unmasked before the system was ready, and obviously would never
have time to fire a tick before the system completed initialization.
But a combination of system load and a new version of Qemu (which
seems to be more sensitive to non-deterministic timing glitchery) has
made this visible.  About 2-3% of the time when run under a full
sanitycheck, the qemu process will get swapped away for long enough
that the tick timer expires before _Cstart() has reached
enable_multithreading().

It looks like the original code was cut and pasted from another
implementation, which was expected to call into an "application"
main() routine that wanted interrupts ready.

Fixes #11182

(Note also that this code is not used for ESP-32, which has its own
startup path)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-12 13:51:20 -05:00
Aurelien Jarno
828ae6b8bc arch: arm: mpu: force outstanding transactions before MPU disabling
The ARMv8-M Memory Protection Unit document indicates that a DMB
instruction must be used before disabling the MPU in order to force
outstanding memory transactions.

The ARMv7-M documentation is less clear about that, and only specifies
that a DSB instruction followed by a ISB instruction must be used
before enabling the MPU, which is already the case. The ARMv7-M and
ARMv8-M MPU are relatively similar to believe the same sequence should
be used for disabling it.

This patch therefore adds a DMB instruction before disabling the MPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-12 08:02:13 -05:00
Aurelien Jarno
1397269335 arch: armv7-m: mpu: disable shareable bit in _get_mpu_ram_region_attr()
In Zephyr on Cortex-M SoCs with both the ARM MPU and the cache enabled,
there are 3 possible states and associated configuration for the RAM
cache attributes:

- MPU disabled                        WBWA non-shareable
- MPU enabled, background RAM region  WBWA non-shareable
- MPU enabled, thread RAM region      WBWA shareable

In practice this means than the thread RAM region toggles from
shareable to non-shareable on each context change.

However the Cortex-M7 SoC does not support the WBWA shareable
configuration and fallback to simpler caching configuration. The
Technical Reference Manual states:

  "By default, only Normal, Non-shareable memory regions can be cached
  in the RAMs. Caching only takes place if the appropriate cache is
  enabled and the memory type is cacheable. Shared cacheable memory
  regions can be cached if CACR.SIWT is set to 1."

Similar indications can be found in the documentation from various
vendors: ST (AN4838), NXP (AN12042) and Atmel (AN15679).

It means that the thread RAM regions are either not cached (CACR.SIWT=0,
default) or WBWT cached (CACR.SIWT=1). This causes a performance issue.
In addition before switching a region from cached to non-cached and
vice-versa, the existing MPU code does not perform cache clean and/or
invalidate operations. This might cause data loss or corruption.

We should therefore change the RAM cache attributes to make them always
consistent. This patches change the thread/application RAM region from
WBWA shareable to WBWA non-shareable. This is done for all ARMv7-M SoCs
with an ARM MPU, however other SoCs (M0+, M3, M4) do not have cache, so
their behaviour should be unchanged.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-12 08:02:13 -05:00
Andrew Boie
140863f6a7 interrupts: use weak linkage instead of linkonce
.gnu.linkonce is an internal undocumented ld feature.
Just use __weak, which does the same thing we want.

This is only done for _sw_isr_table. _irq_vector_table
is left alone due to unwanted interactions between
__weak and the ld KEEP() directive.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
47d30d087b xtensa: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
383c451214 riscv32: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
b3c398fd8d nios2: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
51ca352c20 arm: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
f6b3741ffd arc: add _arch_irq_connect_dynamic()
Implements dynamic interrupts.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
539d3011d3 arch: common: add function for updating IRQ table
This will be called by arch-specific implementations of
_arch_irq_connect_dynamic()

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
7bac15f2ff x86: add dynamic interrupt support
If dynamic interrupts are enabled, a set of trampoline stubs
are generated which transfer control to a common dynamic
interrupt handler function, which then looks up the proper
handler and parameter and then executes the interrupt.

Based on the prior x86 dynamic interrupt implementation which
was removed from the kernel some time ago, and adapted to
changes in the common interrupt handling code, build system,
and IDT generation tools.

An alternative approach could be to read the currently executing
vector out of the APIC, but this is a much slower operation.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Andrew Boie
ff6cce6fc0 kernel: add dynamic interrupt API
In the past the capability to install interrupts at runtime was
removed due to lack of use-cases for Zephyr's intended targets.

Now we want to support hypervisor applications like ACRN where
virtual devices are presented to the kernel using PCI enumeration,
and the interrupt configuration is not known at build time.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Sebastian Bøe
005ff29c0d isr_wrapper: Use 'bx' instead of 'b' to jump to _IntExit
'b' can't jump very far on Cortex-M0 and will cause linker issues when
isr_wrapper and _IntExit are placed far away from each other.

To resolve this we use the 'bx' instruction, as it can jump much
further. Using 'bx' is not dangerous because we are jumping to thumb
mode code.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-11-08 17:07:06 -05:00
Kumar Gala
37f911375a Kconfig: dts: Move HAS_DTS to arch level
Remove either duplicate settings between arch & board, or just set
HAS_DTS at the arch level since all the boards for a given arch support
DTS now.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-06 18:35:39 -05:00
Ioannis Glaropoulos
4fdcb193de arch: arm: mpu: move the early return higher in the execution process
This commit moves the block of the early return before
the derivation of the stack size, to avoid unnecessary
operations if this is not a user thread.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-11-06 22:55:16 +01:00
Ioannis Glaropoulos
929da0feac arch: arm: mpu: fix thread user stack region size
In user mode a thread stack will include the optional
stack guard area (present if MPU_STACK_GUARD is defined.
The guard area has been originally take out of the thread
stack size calculation. For MPUs with no power-of-two size
requirement, we need to increase the size of the MPU region
for user-mode, to account for the additional guard region.
MPUs with power-of-two size requirement will, anyway, round
up the region size to the next power of two.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-11-06 22:55:16 +01:00
Marek Pieta
c99fd5c807 subsys: debug: tracing: Fix interrupt hooks
Change fixes interrupt hooks.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2018-11-06 16:15:29 -05:00
Wayne Ren
a82ca0bb47 arc: fix the coverity issuse in thread.c
fix coverity CID: 187905

issue fixes #9765

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-11-06 08:37:36 -08:00
Daniel Leung
5a47c60dbf arch: xtensa: include soc.h to fix build errors
There are places where soc.h must be included. So include it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-11-03 12:40:33 -04:00
Kumar Gala
8ded3fb1e2 riscv: Move DTS Kconfig enablement to arch level
Now that all supported riscv boards support dts, move the Kconfig option
to the arch level.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 06:58:23 -04:00
Kumar Gala
ec43725562 arch: Remove board.h include from arch files
The arch code doesn't need anything from board.h so lets remove the
include.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-01 13:15:18 +01:00
Flavio Ceolin
61a1057ea5 kernel: Remove redundant type name
struct k_thread already has a pointer type k_tid_t, there is no need for
this definition to tcs.

Less symbols/names make the code cleaner and more readable.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-10-31 19:43:47 -04:00
Marek Pieta
e87193896a subsys: debug: tracing: Fix thread tracing
Change fixes issue with thread execution tracing.

Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
2018-10-29 22:09:12 -04:00
Ioannis Glaropoulos
c5da2e08c6 arch: increase priv stack with built-in stack-overflow checking
This commit increases the privilege stack size to 512 bytes,
when building with support for built-in stack-overflow checking.
This is in alignment with #10729, which increases the privilege
stack size when MPU-based stack guarding is enabled.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-27 21:54:05 -04:00
Ioannis Glaropoulos
dbbed1d1db arch: arm: API to allow Non-Secure FPU Access
This commit introduces and implements an internal ARM
TrustZone-M API to allow the Non-Secure firmware to use
the Floating Point Unit (FPU).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-27 21:39:51 -04:00
Leandro Pereira
aa442d13e7 arch: xtensa: Do not generate unused handle_irq label unless needed
This was causing a `label handle_irq defined but not used` warning
during build.

Fixes #10801.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-27 21:25:57 -04:00
Ioannis Glaropoulos
1cc66cf800 arch: high-level Kconfig symbol structure for Trusted Execution
This commit contributes a Kconfig symbol hierarchy which allows
the user to build Zephyr Secure and Non-Secure images on ARMv8-M
MCUs with support for Trusted Execution. However, the high-level
configuration structure is generic, thus, can be potentially
used for any platform that supports Trusted Execution.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-24 16:38:33 +01:00
Ioannis Glaropoulos
53db00046a arch: arm: typos and style fixes in userspace.S
Some minor typo fixes in inline comments within
arch/arm/core/userspace.S.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-23 09:37:29 -07:00
Ioannis Glaropoulos
d04cec97d5 arch: arm: support built-in stack protection in user mode for ARMv8m
This commit extends the support of built-in thread stack
protection (i.e. based on the stack pointer limit registers)
in ARMv8-M, so that it works with user mode. The commit
does the following:
- enables and disables the stack limit checking on the
privileged stack, inside thread system calls, and upon
entering user mode,
- does not enable stack limit checking in context switch,
if the thread is in user mode.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-23 09:37:29 -07:00
Leandro Pereira
a71c365180 arch: xtensa: Reduce size of interrupt handling routines
This patch reduces the size of ISRs by changing the script to generate
the dispatcher per level to, instead of generating an indirect call per
mask match, do that just once at the function end.

For ESP32, this provides ~380bytes of savings in a (very) hot path
(text, just for the matcher functions generated by xtensa_intgen.py,
drop from 2197 bytes to 1817 bytes).

The generated code also uses the BIT() macro, which shifts 1UL instead
of 1.  Shifting a signed integer is UB in C.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-22 13:38:29 -07:00
Daniel Leung
ecfc1b4ec1 xtensa: specify which SR to store pointer to _kernel.cpu struct
This allows Kconfig to specify which special register is being
used to store the pointer to the _kernel.cpu struct.
Since the SoC itself is highly configurable, sometimes MISC0 is not
available. So this adds the ability to use other special registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 17:52:45 -04:00
Anas Nashif
005f6c7a04 arch: increase privileged stack with mpu stack guard
After commit 3fb6ea21 the stack is not enough and a few tests have been
failing.

Fixes #10632

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-19 16:09:50 -04:00
Adithya Baglody
e9cb0ae72a arch: kernel_arch_func.h: Fix MISRA violation
Always compare unsigned interger type with another unsigned
integer type. Currently in nios2, posix, riscv32, x86 and xtensa
we were comparing the _kernel.nested variable with a signed
interger type. Fixed this violation.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-10-17 12:17:58 -04:00
Adithya Baglody
2d0ba50396 arch: arm: exc.h: MISRA C violation fix in _IsInIsr
The function _IsInIsr computes a Boolean value but the function
returns a integer value. Fix the return type of the function.

This makes the zephyr api _is_in_isr() return a boolean type.
Thereby making it consistent across all the architectures.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-10-17 12:17:58 -04:00
Andy Ross
9098a45c84 kernel: New timeslicing implementation
Instead of checking every time we hit the low-level context switch
path to see if the new thread has a "partner" with which it needs to
share time, just run the slice timer always and reset it from the
scheduler at the points where it has already decided a switch needs to
happen.  In TICKLESS_KERNEL situations, we pay the cost of extra timer
interrupts at ~10Hz or whatever, which is low (note also that this
kind of regular wakeup architecture is required on SMP anyway so the
scheduler can "notice" threads scheduled by other CPUs).  Advantages:

1. Much simpler logic.  Significantly smaller code.  No variance or
   dependence on tickless modes or timer driver (beyond setting a
   simple timeout).

2. No arch-specific assembly integration with _Swap() needed

3. Better performance on many workloads, as the accounting now happens
   at most once per timer interrupt (~5 Hz) and true rescheduling and
   not on every unrelated context switch and interrupt return.

4. It's SMP-safe.  The previous scheme kept the slice ticks as a
   global variable, which was an unnoticed bug.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
Andy Ross
47644c2015 system_timer.h: Remove ASMLANGUAGE guard
This header isn't actually needed in the one assembly context where
it's included.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
Andy Ross
317178b88f sys_clock: Fix unsafe tick count usage
The system tick count is a 64 bit quantity that gets updated from
interrupt context, meaning that it's dangerously non-atomic and has to
be locked.  The core kernel clock code did this right.

But the value was also exposed to the rest of the universe as a global
variable, and virtually nothing else was doing this correctly.  Even
in the timer ISRs themselves, the interrupts may be themselves
preempted (most of our architectures support nested interrupts) by
code that wants to set timeouts and inspect system uptime.

Define a z_tick_{get,set}() API, eliminate the old variable, and make
sure everyone uses the right mechanism.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
Andy Ross
b2e4283555 sys_clock: Make sys_clock_hw_cycles_per_tick() a proper API
This was another "global variable" API.  Give it function syntax too.
Also add a warning, because on nRF devices (at least) the cycle clock
runs in kHz and is too slow to give a precise answer here.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-10-16 15:03:10 -04:00
Ioannis Glaropoulos
3fb6ea210a arch: arm: re-program MPU stack guard upon userspace enter
Before entering userspace, the MPU stack guard is
configured to guard the default (i.e. afterwards, the "user")
thread stack, as the privileged stack has not yet been set. Upon
entering userspace the MPU stack guard needs to be re-programmed
to the privileged stack, otherwise, there is a risk that the
first system call might be serviced without privileged stack
protection, if it occurs before any context-switch. This commit
fixes this issue, by calling configure_mpu_stack_guard(..) upon
userspace entering.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-15 12:19:09 -05:00
Yasushi SHOJI
6fc0d77432 arch: add big endian support
This patch adds Big Endian architecture support.  Even if a compiler
generating big endian object files is used, our linker script, or
include/linker/linker-tool-gcc.h to be precise, has default output
format as little endian.

This patch adds a hidden config CONFIG_BIG_ENDIAN, which should be set
by big endian architectures or a SoC's, and adds an condition to
switch OUTPUT_FORMAT in our linker.cmd.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2018-10-10 09:28:05 -04:00
Alberto Escolar Piedras
8eb51a309d POSIX arch: Add stub for sys_arch_reboot()
To allow apps to compile with CONFIG_REBOOT,
add a weak stub for sys_arch_reboot which does nothing
in the POSIX arch
POSIX boards may choose to provide a more sensible implementation
if relevant.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-10-09 16:15:45 -04:00
Anas Nashif
95d710ca41 arch: nxp_mpu: fix types in log macro
Fix format type in log message.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Anas Nashif
8e38670af3 arch: setup logging using new logger
Use the new logger framework for architecture code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Anas Nashif
eb29978a57 userspace: move KOBJECT/PRIVILEGED_STACK_TEXT_AREA to Kconfig
Instead of hardcoding in linker script, use a Kconfig and deal with
dependencies in Kconfig instead of directly in the linker file.

This patch moves both:
PRIVILEGED_STACK_TEXT_AREA
and
KOBJECT_TEXT_AREA

to arch/Kconfig.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 14:18:26 -04:00
Flavio Ceolin
78f27a81f5 kernel: Using the same paramenters names in a specific function
MISRA-C requires that all declarations of a specific function, or
object, use the same names and type qualifiers.

MISRA-C rule 8.3

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-28 07:58:19 +05:30
Mark Ruvald Pedersen
d67096da05 portability: Avoid void* arithmetics which is a GNU extension
Under GNU C, sizeof(void) = 1. This commit merely makes it explicit u8.

Pointer arithmetics over void types is:
 * A GNU C extension
 * Not supported by Clang
 * Illegal across all ISO C standards

See also: https://gcc.gnu.org/onlinedocs/gcc/Pointer-Arith.html

Signed-off-by: Mark Ruvald Pedersen <mped@oticon.com>
2018-09-28 07:57:28 +05:30
Alberto Escolar Piedras
013f279111 uart: Add driver for posix arch
Added a new UART driver for posix arch boards.
The driver can be configured to either attach to a new
pseudo-terminal, or to connect to the invoking shell
stdin-out.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-09-27 17:24:34 +02:00
Krzysztof Chruscinski
27459a13e4 arch: Add LOG_PANIC to fault handlers
Added LOG_PANIC to fault handlers to ensure that log is flush and
logger processes messages in a blocking way in fault handler.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2018-09-27 13:11:26 +05:30
Ioannis Glaropoulos
13a4d884f0 arch: arm: remove un-necessary inclusion of <string.h>
Remove the inclusion of <string.h>, if CONFIG_INIT_STACKS
is defined, because it is not required anywhere in thread.c.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-26 18:26:03 -05:00
Ioannis Glaropoulos
66192618a7 arch: arm: Minor style and typo fixes in inline comments
Several style and typo fixes in inline comments of arm kernel
files and thread.c.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:56:34 -07:00
Ioannis Glaropoulos
7d4339a920 arch: arm: add explanatory comment for SPLIM_NS set functions
This commit adds an inline explanatory comment in the API
for setting the non-secure stack-pointer limit registers, to
stress that the API is only applicable to Mainline ARMv8-M MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:55:41 -07:00
Ioannis Glaropoulos
98e38109c4 arch: arm: fix error reason intialization
This commit fixes a minor bug by setting the error reason
(to, default, _NANO_ERR_HW_EXCEPTION) for errors detected
during Secure/Non-Secure stack inspection. Applicable only
to Secure firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 04:55:41 -07:00
Ramakrishna Pallala
56117f9f91 arch: Kconfig: Add Kconfig options for Low Power States
Add Kconfig options for Low Power and Deep Sleep States which
need to be selected by the SoC's based on it's supported
Low Power States.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-20 10:20:23 -04:00
Piotr Zięcik
1c16cfcc30 arch: arm: Make ARM_MPU the sole option controlling MPU usage
This commit removes all MPU-related (ARM_CORE_MPU and NXP_MPU)
options exept ARM_MPU, which becomes master switch controlling
MPU support on ARM.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
d393186d51 arch: arm: Introduce CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options
This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options,
which indicate which flavour of MPU is supported by given SoC family.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Sebastian Bøe
1765276000 arch: arm: Use BL instead of B to jump to _PrepC
The __reset vector is using the 'b' instruction to jump to _PrepC. 'b'
can only jump 2KB on Cortex-M0 platforms so this causes build failures
when _PrepC happens to be too far away from __reset.

To resolve this we use 'bl' instead as it can jump two thousand times
further[0].

This can also be resolved by porting the reset vector to C or by
placing the _PrepC function in a dedicated section that the linker
places next to __reset.

[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0489e/Cihfddaf.html

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-09-19 09:13:50 -04:00
Alberto Escolar Piedras
ba5476a2a0 native_posix: Add control of traces color
For native_posix:
Added command line options to control if traces should have
or not colors.
+
Detect if we are connected to a tty or not, and if we are
set the defaults for that option appropriately

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-09-18 14:56:10 +02:00
Flavio Ceolin
4a211ec241 include: Add missing headers guard
Add missing headers guard

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Flavio Ceolin
67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Ioannis Glaropoulos
73e8454d17 arch: arm: remove power-of-two align and size requirement for ARMv8-m
The ARMv8-m Memory Protection Unit does not require MPU regions
to be power-of-two aligned and sized. This commit removes this
requirement when building for ARMv8-m MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-14 23:05:13 -04:00
Flavio Ceolin
da49f2e440 coccicnelle: Ignore return of memset
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.

The only directory excluded directory was ext/* since it contains
only imported code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Flavio Ceolin
5884c7f54b kernel: Explicitly ignoring _Swap return
Ignoring _Swap return where there is no treatment or nothing to do.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Flavio Ceolin
8a9ba10c2c kernel: swap: Fix __swap signature
__swap function was returning -EAGAIN in some case, though its return
value was declared as unsigned int.

This commit changes this function to return int since it can return a
negative value and its return was already been propagate as int.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Sebastian Bøe
d98e046a24 cmake: move ti_lm3s6965-specific code into the soc directory
As far as possible SoC-specific code should be contained to it's
directory and core systems should not be referencing specific
SoCs. This keeps the common code clean and makes it easier to maintain
out-of-tree SoCs.

To this end we move CONFIG_SOC_TI_LM3S6965_QEMU's soft-reset related
code out of arch/arm/core/cortex_m and into arch/arm/soc/ti_lm3s6965.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-14 10:22:20 -05:00
Anas Nashif
abcf2ad5a8 kconfig: move soc selection to ZEPHYR_BASE/soc/
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
563c161a80 posix: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
696aa869d5 nios2: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
279cc2e448 riscv32: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
f183444682 arc: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
70d819b405 arm: soc: move arm SoCs to top-dir
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
5744437d25 kconfig: adapt help messages for new location of SoC code
Point to the new location of the soc code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cff0005a87 x86: move soc/cpu to top-level under soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Paweł Zadrożniak
7c2197f2d8 boards: nrf: uart: Moved UART pin configuration to DTS (nRF boards)
UART pins (TX, RX, RTS, CTS) are now configured in DTS files.
RTS and CTS definitions are optional. If flow control is enabled
and RTS/CTS pins are not defined, then compiler will issue
an error message.

Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
2018-09-11 23:29:50 -05:00
Ulf Magnusson
d713033d5c Kconfig: Use new preprocessor syntax for env. variables
With the new Kconfig preprocessor (described in
https://github.com/torvalds/linux/blob/master/Documentation/kbuild/
kconfig-macro-language.txt), the syntax for expanding environment
variables is $(FOO) rather than $FOO.

$(FOO) is a general preprocessor variable expansion, which falls back to
environment variables if the variable isn't set (like in Make). It can
also be used in prompts, 'comment's, etc.

The old syntax will probably be supported forever in Kconfiglib for
backwards compatibility, but might as well make it consistent now that
people might start using the preprocessor more.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-09-11 19:17:25 -04:00
Ulf Magnusson
d0e8752a52 Kconfig: Rename $ENV_VAR_{ARCH,BOARD_DIR} to $ARCH/$BOARD_DIR
The prefixes might be a leftover from the old 'option env="..."' symbols
(which are no longer needed). Since environment variables can be
referenced directly now, there's no point in having a prefix.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-09-11 19:17:25 -04:00
David Brown
e0dda1b4b0 lib: posix: clock: Add gettimeofday() call
Provide an implementation of gettimeofday().  This uses clock_gettime()
with the CLOCK_REALTIME parameter, which is currently unimplemented, but
will allow clients to call this function once this functionality has
been implemented.

Signed-off-by: David Brown <david.brown@linaro.org>
2018-09-11 09:21:52 -04:00
Pawel Dunaj
c850ba8efa arch: arm: soc: nordic_nrf: nrf52: Add missing header
Add missing header required to use bool type.

Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
2018-09-11 08:43:53 -04:00
Maureen Helm
0439deeac6 arm: Clear primask and faultmask during startup
A bootloader may leave primask or faultmask set, so clear them during
startup when we enable interrupts and switch to the main thread.
Previously we only cleared primask for architecture variants which don't
support basepri, but now we do it for all architecture variants.

Fixes a failure on mimxrt1050_evk with the latency_measure test and
shell_module sample when using an nxp internal bootloader.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-11 08:36:57 -04:00
Filip Kubicz
990a0e8c71 dts: add SPI bindings for nRF family
This change adds DTS definition of SPI device for nRF chips.
It also removes SPI pin configuration from Kconfig and moves it to
chip DTS.

Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
2018-09-11 11:41:37 +02:00
Filip Kubicz
5c3992f34f dts: update I2C bindings for nRF chips
Change 'nRF5' family names to 'nRF' in I2C DTS.

Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
2018-09-11 11:41:37 +02:00
Daniel Leung
8708611fab adc: add native driver for Quark D2000
This adds a native ADC driver for Quark D2000.

Original: origin

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-05 18:38:57 -04:00
Sathish Kuttan
c5f04d7c24 arch: xtensa: remove extra #endif
Remove extra #endif that should have been removed when the
corresponding #ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP was
removed in commit a2248782a2

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-09-04 14:27:33 -04:00
Anas Nashif
3298905bfe xtensa: removed obsolete headers
Went in by mistake in a bad rebase, fixes #9753.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-01 13:58:46 -04:00
Punit Vara
c995c4b42b dts: arc: Use dts tree for designware driver
Get required data from dts tree.

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-08-29 13:46:57 -04:00
Punit Vara
ef83943387 drivers: Use Designware driver for sensor subsystem
Remove adc_qmsi_ss to use designware driver for sensor subsystem

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-08-29 13:46:57 -04:00
Justin Watson
4e551aabb6 sam: adc: Updated SAM ADC driver.
Updated to work with new ADC API.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-08-29 13:46:57 -04:00
Andrzej Głąbek
0a97b5bf35 dts: nrf: Add ADC nodes and bindings for nRF SoCs
This commit adds ADC nodes to DTS files for nRF SoCs and introduces
corresponding  bindings for these nodes.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-08-29 13:46:57 -04:00
Yannis Damigos
d2e713f9ef arch: stm32l4: Enable gpio interrupts correctly
Enable gpio interrupts correctly and don't
disable the already enabled interrupts.

Fixes #9630

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-08-29 08:53:09 -04:00
Yannis Damigos
32a6fa1c58 arch: st_stm32: Remove I2C and SPI instances from common defconfig
Remove I2C and SPI instances when enabling I2C_STM32 and
SPI_STM32 drivers.

It allows to enable the drivers if ports I2C_4, SPI_4,
SPI_5, SPI_6 are selected.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-08-29 07:04:32 -05:00
Kiril Zyapkov
64b130683c arch: arm: stm32l4: add missing I2C_3 to dts.fixup
One can enable I2C_3 in kconfig and set status = "ok" in dts, but
the driver expects to find the config as fixed up with this
addition.

Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
2018-08-28 13:18:44 -05:00
David B. Kinder
1c29bff055 doc: fix kconfig misspellings
Fix misspellings in kconfig files missed during regular reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-08-28 13:58:46 -04:00
Adithya Baglody
511edf0175 Revert "sam_e70: enable instruction and data caches on sam_e70"
This reverts commit c0907762f3.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-28 13:46:47 -04:00
Anas Nashif
c0907762f3 sam_e70: enable instruction and data caches on sam_e70
The Cortex-M7 CPU included in the SAM e70 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization.

Fixes #8138

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-27 10:09:19 -04:00
Sebastian Bøe
69d8c1c08c syscalls: Correct the type of _k_syscall_table
_k_syscall_table is an array of function pointers and is declared as
such in C sources, this makes it an STT_OBJECT[0] in the symbol
table. But when the same symbol is declared in assembly, it is
declared to be a function, which would make the symbol an STT_FUNC.

When linking with LTO this type inconsistency results in the warning:

real-ld: Warning: type of symbol `_k_syscall_table' changed from 2 to
1 in /tmp/cc84ofK0.ltrans8.ltrans.o

To fix this warning we declare the table with GDATA instead of GTEXT,
which will change the type from 'function' to 'object'.

[0]
https://docs.oracle.com/cd/E19455-01/816-0559/chapter6-79797/index.html

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-08-26 08:54:27 -07:00
Aurelien Jarno
069d409b29 arch: arm: stm32: enable instruction and data caches on STM32F7
The Cortex-M7 CPU included in the STM32F7 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization. Note that the D-cache should only be enabled if it
is disabled, to workaround CMSIS issue #331.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-08-25 07:15:33 -07:00
Wayne Ren
0be1875e42 boards: cleanup and update the default config of arc boards
apply to snps arc boards

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-24 09:31:24 -07:00
Piotr Mienkowski
f69199777f soc: efr32fg1p: correct clock initialization sequence
This patch changes clock initialization sequence to initialize external
cristal oscillators only if it was not done before. Initialization of
external cristal oscillators may be performed by the bootloader.

Tested on BRD4250B evaluation board.

Fixes #9471

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2018-08-22 11:06:58 -05:00
Ramakrishna Pallala
1301cc636b arch: arm: nordic_nrf: Add an API to check for valid PM state
Add an API _sys_soc_is_valid_power_state to check if a PM state
is valid or not.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-08-22 08:07:14 -07:00
Wayne Ren
506f21b631 arch: arc: small optimization in mpu driver
to avoid _get_num_regions to access the aux
reg each time in the for loop

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
eab5ff725d arch: arc: put the init context into privileged stack
as the thread is created in privileged mode, the init
context should also be in privileged stack.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
fa9fb831ed arch: arc: re-orgnize the code in _new_thread
re-orginize the code in _new_thread to make it
easier to understand and maintain

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
a1504c3c0d arch: arc: set the right init status for user space
The fake exception return is used to jump to user mode.
So the init status of user thread is in exception mode.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
d68c016793 arch: arc: enable stack check when arc is in secure mode
when arc is in secure mode, SSC bit of sec_stat,
not SC bit of status32,is used to enable stack check.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Wayne Ren
f3d2893344 arch: arc: stack check will be disabled in exception
stack check bit of status32/sec_stat will be cleared
automically in exception entry.

so remove the redundent codes

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-22 07:57:11 -07:00
Diego Sueiro
d1219f4e29 arch/mcimx7_m4: Add i.MX7 Solo Kconfig SoC partnumber define
Adds the proper Kconfig entries for the i.MX7S partnumber presented
on WaRP7 board.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-21 18:54:41 -05:00
Diego Sueiro
671cb652a1 arch/mcimx7_m4: Add pad, clock and gate config for GPIO7 and UART6
Adds the necessery configuration for using the GPIO7 and UART6 on
i.MX7 platforms.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-21 18:54:41 -05:00
Anas Nashif
483910ab4b systemview: add support natively using tracing hooks
Add needed hooks as a subsystem that can be enabled in any application.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
a2248782a2 kernel: event_logger: remove kernel_event_logger
Move to more generic tracing hooks that can be implemented in different
ways and do not interfere with the kernel.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
ac47070d10 tests: qmsi: remove soc watch sample
Remove this feature specific to QMSI and available through samples only
to allow for migration to tracing hooks.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Anas Nashif
b6304e66f6 tracing: support generic tracing hooks
Define generic interface and hooks for tracing to replace
kernel_event_logger and existing tracing facilities with something more
common.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-08-21 05:45:47 -07:00
Adithya Baglody
1d27b404a6 tests: benchmarks: timing_info: Enable benchmarks for riscv32.
This patch provides support needed to get timing related
information from riscv32 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
79f65d4db7 tests: benchmarks: timing_info: Enable benchmarks for nios2.
This patch provides support needed to get timing related
information from nios2 based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
bb918d85f8 tests: benchmarks: timing_info: Enable benchmarks for xtensa.
This patch provides support needed to get timing related
information from xtensa based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
022588e88d tests: benchmarks: timing_info: Enable benchmarks for ARC.
This patch provides support needed to get timing related
information from ARC based SOC.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
db0c5ca08b arch: arc: Added benchmark related hooks.
The benchmark application timing_info needs certain hooks to be
present in the kernel to get the accurate measurements. This
patch adds these hook at all the required locations.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Adithya Baglody
a8b0b0d5e8 benchmarks: timing_info: Add hooks in the kernel for userspace.
Added sampling hooks in the kernel needed for userspace benchmarks.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-08-20 06:51:25 -07:00
Ioannis Glaropoulos
6ee0ad2944 arch: arm: add ASSERT in _get_region_attr_by_type
This commit adds an __ASSERT line in _get_region_attr_by_type,
to signal an error if the supplied MPU region type is not valid.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
b956690520 arch: arm: mpu: explicitly add UL in numerical shift operations
This commit adds a UL suffix after numerical digits to ensure
the correctness of certain shift operations.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
2a1fe6e285 arch: arm: implement ARMv8-M MPU driver
This commit implements and integrates the ARMv8-M MPU driver
into the memory protection system for ARM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
2f0e722167 arch: arm: mpu: move ARMv7m-specific functions in internal header
This commit refactors arm_mpu.c by moving all internal function
implementation that is specific to ARMv7-M architecture to a
separate internal header file. This allows to easily extend
arm_mpu.c to support ARMv8-M by including all ARMv8-M-specific
implementation in a similar internal header.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
5a69648061 arch: arm: refactor _get_region_attr_by_conf(.) function
This commit refactors the _get_region_attr_by_conf(.) function,
so it does the following:
 - it is renamed to _get_ram_region_attr_by_conf(), to reflect
   that it is only used to configure RAM MPU regions.
 - it gets an arm_mpu_region_attr_t object structure pointer
   to fill-in with the derived region attributes.
 - it takes an additional argument (the region base address),
   which allows the function to have a common signature with the
   ARMv8-M version of it (where the attribute derivation needs
   the base address).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
829781d56e arch: arm: refactor _get_region_attr_by_type() function
This commit refactors the _get_region_attr_by_type(.) function,
so it does the following:
 - it takes an arm_mpu_region_attr_t object pointer and use it
   to fill-in the derived region attributes.
 - it performs only the distinguishing between the different MPU
    region types, hiding the actual MPU-specific implementation
	in internal functions.
 - it takes an additional argument (the region base address),
   which allows the function to have a common signature with the
   ARMv8-M version of it (where the attribute derivation needs
   the base address).
 - it returs 0 or succes and a negative non-zero integer
   to indicate an error.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Ioannis Glaropoulos
ff919d5fdb arch: arm: adapt region_init(.) to use arm_mpu_region_attr structure
This commit adapts the _region_init(.) function so it can use
the rasr field of the arm_mpu_region_attr structure, when it
configures the RASR register.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-19 11:18:14 -07:00
Sathish Kuttan
824bcaca52 xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000
Added routines for setting up resource ownership for
    DMA, I2S
Added routine to setup power gating and clock configuration

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-08-19 11:06:09 -07:00
Ulf Magnusson
21e63ed2ae arch: arm: kconfig: Remove redundant FLOAT dependencies
The choice that contains FP_HARDAPI and FP_SOFTAPI already depends on
FLOAT, so the choice symbols don't have to.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-18 07:54:20 -07:00
Daniel Leung
fc182430c0 kernel: userspace: reserve stack space to store local data
This enables reserving little space on the top of stack to store
data local to thread when CONFIG_USERSPACE. The first customer
of this is errno.

Note that ARC, due to how it lays out the user stack and
privilege stack, sets the pointer itself rather than
relying on the common way.

Fixes: #9067

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-08-17 09:40:52 -07:00
Mieszko Mierunski
4f6aac1a67 dts: nrf5: Changed GPIO and GPIOTE define names
Changed names using nrf5 to nrf for consistency with other drivers.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
15813d343c boards: nrf: Changed GPIO default driver to NRFX shim
I removed GPIO configuration from board files and enabled them
as default in driver Kconfig file. All boards had GPIO ports
enabled that is why I decided to enable it by default.

Power management example was changed to use new driver.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
6d8220d27f drivers: gpio: Add shim for nrfx GPIO and GPIOTE drivers
Added shim implementation gpio_nrfx.c which uses nrfx drivers
for GPIO and GPIOTE

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Mieszko Mierunski
e99e363cc0 dts: nrf: Added DTS support for nRF51
DTS for nRF51 was missing, I updated soc and board files to
support DTS properly.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-08-17 07:29:14 -07:00
Flavio Ceolin
8aec087268 kernel: Fix bitwise operators with unsigned operators
Bitwise operators should be used only with unsigned integer operands
because the result os bitwise operations on signed integers are
implementation-defined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-08-16 19:47:41 -07:00
Flavio Ceolin
0866d18d03 irq: Fix irq_lock api usage
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.

In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-08-16 19:47:41 -07:00
Olivier Martin
945ef745e0 dts/rtc: Introduce binding for STM32 RTC
This commit adds rtc fixup and dts blocks for RTC hardware
on STM32L4.

Signed-off-by: Olivier Martin <olivier.martin@proglove.de>
2018-08-16 13:38:43 -07:00
Kiril Zyapkov
0d47ae4fca drivers: rtc: add support for STM32 RTC
Add support for the STM32 Real-Time-Clock leveraging the LL APIs

Signed-off-by: Johannes Hutter <johannes@proglove.de>
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
2018-08-16 13:38:43 -07:00
Nathaniel Graff
218d7a0aa9 riscv: Rename the FE310 SoC to Sifive Freedom
FE310 is the name of one SoC out of a range of products in the SiFive
Freedom line. The FE310 SoC port in Zephyr is compatible with all of
these products, so rename the SoC to SiFive Freedom

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-16 06:23:01 -07:00
Istvan Bisz
ea9d4a79c9 drivers: usb: add support for USB OTG FS on STM32F2
Add support for usbotg_fs, by adding the DT fixup, pinmux macros,
and the DT entries in stm32f2.dtsi.

Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
2018-08-16 06:19:19 -07:00
Sebastian Bøe
1186f5bb29 cmake: Deprecate the 2 symbols _SYSCALL_{LIMIT,BAD}
There exist two symbols that became equivalent when PR #9383 was
merged; _SYSCALL_LIMIT and K_SYSCALL_LIMIT. This patch deprecates the
redundant _SYSCALL_LIMIT symbol.

_SYSCALL_LIMIT was initally introduced because before PR #9383 was
merged K_SYSCALL_LIMIT was an enum, which couldn't be included into
assembly files. PR #9383 converted it into a define, which can be
included into assembly files, making _SYSCALL_LIMIT redundant.

Likewise for _SYSCALL_BAD.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-08-15 11:46:51 -07:00
Nathaniel Graff
970cfdb88b arch: riscv32: Move MEPC increment in irq_wrapper
Move the MEPC increment logic in __irq_wrapper such that the saved MEPC
is only incremented on a syscall (ecall instruction).

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-08-15 08:07:41 -05:00
Ulf Magnusson
8cf8db3a73 Kconfig: Use a short, consistent style for prompts
Consistently use

    config FOO
            bool/int/hex/string "Prompt text"

instead of

    config FOO
            bool/int/hex/string
            prompt "Prompt text"

(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).

The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.

Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/
how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-15 04:10:10 -07:00
Ioannis Glaropoulos
bb0b66e15a arch: arm: clean-up "default n" entries in Kconfig option definitions
This commit removes the depreciated "default n" entries from
boolean K-config options in arch/arm.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-15 04:09:16 -07:00
Ulf Magnusson
17f1b0adec Kconfig: Switch to improved globbing statements
A design flaw of 'gsource' is that there's no way to require at least
one file to match the glob pattern. This could lead to silent errors.

Switch to a new design, where a plain 'source' is globbing and requires
at least one file to match. A separate 'osource' (optional source)
statement is available for cases where it's okay for a pattern (or plain
filename) to not match any files.

'orsource' combines 'osource' and 'rsource' (relative source).

This commit search-replaces 'gsource' with 'source', but backwards
compatibility with 'gsource' is still maintained by making it an alias
for 'osource' (and by making 'grsource' an alias for 'orsource').

The three Kconfig files arch/{nios2,posix,xtensa}/Kconfig source
arch/{nios2,posix,xtensa}/soc/*/Kconfig, which doesn't match any files.
Use 'osource' for those. The soc/*/Kconfig files seem to be for
additional SoC-specific symbols, only none exist yet on those ARCHes.

Also use 'osource' for the source of $ENV_VAR_BOARD_DIR/Kconfig in
boards/Kconfig, which doesn't exist for all boards.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-15 04:07:44 -07:00
David Lamparter
c4703661e6 arch: arm: soc: add STM32L433
The L433 chip is a superset of the L432, just grabbing a few additional
interfaces (LCD, I2C2, USART3, SPI2, SDMMC).  All the support/HAL files
are already there, so enabling these is just a matter of build system
setup.

Tested on an application specific board (builds correctly and I2C2
works.)  I unfortunately don't have a nucleo/discovery board to create a
reference board for.

Signed-off-by: David Lamparter <equinox@diac24.net>
2018-08-13 18:59:17 -07:00
Ioannis Glaropoulos
f2bdee356b arch: arm: export entry veneers
When building a Secure firmware image, instruct the linker to
generate a symbol table with the entry veneers, to allow a Non
Secure firmware image to access Secure Entry functions via the
entry veneers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
db3f6aab02 arch: arm: add option to define an NSC region
This commit adds K-config options that allow the user to
signify an ARM Secure Firmware that contains Secure Entry
functions and to define the starting address of the linker
section that will contain the Secure Entry functions. It
also instructs the linker to append the NSC section if
instructed so by the user.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
3b79b283f9 arch: arm: API & implementation of SAU region configuration
This commit contribute an internal ARM API that enables the
user to confgure an ARM Security Attribution Unit region. It
also defines ARM_SAU as a K-config option to indicate that
an MCU implements the ARM SAU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
6e93eea3a3 arch: arm: api to permit/block NS system reset requests
This commit contributes a simple API to allow the TrustZone
user to block or permit Non-Secure System Reset requests.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
d9cfbc280f arch: arm: macro API for defining non-secure entry functions
This commit introduces an internal ARM macro API to allow the
TrustZone user to define Non-Secure entry functions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
a05081804a arch: arm: API macros for CMSE non-secure function pointers
This commit defines and implements and internal ARM macro API
that allows the TrustZone user to declare, define, and evaluate
pointers of non-secure function type.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
f8b5046b13 arch: arm: include GCC -mcmse compile option for secure firmware
Make GCC compile with the -mcmse compile option, if we are
building a Secure firmware. The option will make Security
Extensions for secure executables available, and will set
the corresponding compile-time indicator flag, accordingly:
(i.e. __ARM_FEATURE_CMSE=3).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
ba02c6d91e arch: arm: api for reading MCU SAU regions
Define and implement a function to read the number of
SAU regions configued for the MCU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
5bb3d01580 arch: arm: API to configure Secure exception boost
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to select whether Secure exceptions will
have priority boosting over Non-Secure exceptions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
179b8d15f1 arch: arm: API to configure fault target state
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to configure the target state of fault
exceptions that are not banked between security states.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
28acaeadc9 arch: arm: add macro definition for vector key write permit value
This commit adds a macro definition for the Vector Key value of
AIRCR register that permits the accompanying writes. The macro
is then used instead of the hard-coded numerical value.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
97d5f60afb arch: arm: configure NS stack pointer limit registers
This commit adds and implements an ARM internal API function
to configure the Non-Secure instance of MSPLIM or PSPLIM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
de78430072 arch: arm: internal API to enable/disable SAU
This commit defines and implements the internal ARM TrustZone
API to enable or disable the Security Attribution Unit.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Ioannis Glaropoulos
034499af1a arch: arm: configure non-secure registers from secure firmware
Define and implement an API to configure the Non-Secure instances
of core registers in ARM Cortex-M23 and Cortex-M33.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 18:58:11 -07:00
Paul Sokolovsky
028aae1ec9 net: config: Rename Kconfig options to correspond to library name
This finishes refactor of splitting off net_config library name from
net_app library, started in c60df1311, c89a06dbc. This commit makes
sure that Kconfig options are prefixed with CONFIG_NET_CONFIG_
instead of CONFIG_NET_APP_, and propagates these changes thru the
app configs in the tree.

Also, minor dependency, etc. tweaks are made.

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2018-08-13 18:42:31 -07:00
Nathaniel Graff
45d5d5db48 boards: riscv: Convert HiFive1 to DTS
Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and
riscv,plic0.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-13 18:35:38 -05:00
Ioannis Glaropoulos
b996955e34 arch: arm: optimize _size_to_mpu_rasr_size function
This commit optimizes _size_to_mpu_rasr_size(.) in the ARMv7-M
MPU driver, so it makes use of a single _builtin_clz() function
call, instead of two.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-08-13 13:00:30 -07:00
Ulf Magnusson
ec3eff57e0 Kconfig: Use the first default with a satisfied condition
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.

There are at least three problems with the patch:

  1. It's inconsistent with how Kconfig works in other projects, which
     might confuse newcomers.

  2. Due to oversights, earlier 'range' properties are still preferred,
     as well as earlier 'default' properties on choices.

     In addition to being inconsistent, this makes it impossible to
     override 'range' properties and choice 'default' properties if the
     base definition of the symbol/choice already has 'range'/'default'
     properties.

     I've seen errors caused by the inconsistency, and I suspect there
     are more.

  3. A fork of Kconfiglib that adds the patch needs to be maintained.

Get rid of the patch and go back to standard Kconfig behavior, as
follows:

  1. Include the Kconfig.defconfig files first instead of last in
     Kconfig.zephyr.

  2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
     last in arch/Kconfig.

  3. Include arch/<arch>/soc/*/Kconfig first instead of last in
     arch/<arch>/Kconfig.

  4. Swap a few other 'source's to preserve behavior for some scattered
     symbols with multiple definitions.

     Swap 'source's in some no-op cases too, where it might match the
     intent.

  5. Reverse the defaults on symbol definitions that have more than one
     default.

     Skip defaults that are mutually exclusive, e.g. where each default
     has an 'if <some board>' condition. They are already safe.

  6. Remove the prefer-later-defaults patch from Kconfiglib.

Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions

As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).

This commit includes some default-related cleanups as well:

  - Simplify some symbol definitions, e.g. where a default has 'if FOO'
    when the symbol already has 'depends on FOO'.

  - Remove some redundant 'default ""' for string symbols. This is the
    implicit default.

Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).

Piggyback some fixes for style nits too, e.g. unindented help texts.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-10 12:38:28 -07:00
Diego Sueiro
9283ee7acc arch: i.MX add RDC peripheral permission setting for applications cores
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).

This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.

The settings are defined at devicetree level and applied in the soc.c.

A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-08-09 10:17:32 -05:00
Wayne Ren
37cc2ccc0f arch: arc: fix a bug in mpu driver
for mpu stack guard, after arc_core_mpu_configure,
it should return

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-08-06 09:40:56 -05:00
Michael Scott
65af15bcc2 boards: arm: nrf52840_pca10056: add settings for WNC-M14A2A modem
These settings enable use of the WNC-M14A2A LTE-M modem as the default
network interface for the nRF52840-DK board (nrf52840_pca10056).

They include the following settings when MODEM_WNCM14A2A is selected:
- UARTE1 pin setup
- DTS / DTS fixup additions for WNC-M14A2A
- Kconfig settings for modem driver

Signed-off-by: Michael Scott <mike@foundries.io>
2018-08-06 10:43:46 +03:00
qianfan Zhao
eab3f3f27f arm: _FaultShow: fix typo MMFSR -> UFSR
The right param should be SCB_UFSR not SCB_MMFSR

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-08-03 08:41:22 -05:00
Kumar Gala
4b22ba7e4b syscall: Move arch specific syscall code into its own header
Split out the arch specific syscall code to reduce include pollution
from other arch related headers.  For example on ARM its possible to get
errno.h included via SoC specific headers.  Which created an interesting
compile issue because of the order of syscall & errno/errno syscall
inclusion.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-08-02 22:06:49 -05:00
Alberto Escolar Piedras
11aa0b8006 posix arch: Do not disable warnings
Initially missing function prototypes warnings and undefined macro
warnings  were disabled to quickly prototype the posix arch and
native_posix board.
But there is no excuse anymore to have this warnings disabled.
=> enable them.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
4388cde90f arch posix: Allow including XOPEN extensions
The native_posix random driver uses random() and srandom()
whicha are old XOPEN POSIX extension (part of POSIX 2001).

To avoid compiler warnings due to the host libC headers
not including this prototypes otherwise, let's define
this 2 macros.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
00b07615fa native_posix: Add missing headers and function prototypes
A few function prototypes were missing in the native_posix
board and its drivers.
Let's add them.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Alberto Escolar Piedras
c0ea40cd74 posix arch: Add missing header
Add missing header in posix arch file

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-08-02 19:14:19 +02:00
Ulf Magnusson
d1684a83a4 Kconfig: Clean up some symbol definitions
- Remove redundant 'n' defaults. 'n' is the default value for bool
  symbols.

  This makes the auto-generated documentation clearer as well: You get
  "implicitly defaults to n" instead of
  "- n if <propagated dependencies>".

- Shorten

      <type>
      prompt "foo"

  to

      <type> "foo"

  This works for all types, not just bool.

- Various formatting nits.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-08-01 12:47:17 -04:00
Anas Nashif
9426a3cbf9 arch: x86: set output format/arch per arch
Instead of doing this per platform, set the output format and arch on
architecture level.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-31 20:30:33 -04:00
Andrew Boie
b1dec2992e arc: add z_arch_user_string_nlen
Safely measure the length of a potentially dubious string.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Andrew Boie
3cef6deb16 arm: add z_arch_user_string_nlen
Uses fixup infrastructure to safely abort if we get an MPU
fault when examining a string passed in from user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Andrew Boie
9d3cdb3568 x86: add z_arch_user_string_nlen
Uses fixup infrastructure to safely abort if we get a page
fault while measuring a string passed in from user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-31 07:47:15 -07:00
Alberto Escolar Piedras
550225b668 native: Generalize native tasks
Some drivers or tests need to execute some code before Zephyr is
booted, dynamically register command line arguments, etc.

For this purpose, we generalize the NATIVE_EXIT_TASK to also
provide hooks to run a function at a given point during the startup
of native_posix.

Also, test/boards/native_posix/exit_tasks is generalized to cover
this new functionality.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-30 22:13:46 -04:00
Daniel Leung
b3e68703b5 arch/x86: apollo_lake: add PCI related bits for UARTs/I2Cs
This adds PCI related configuration for UARTs and I2C controllers
to the Apollo Lake SoC configuration to support PCI devices.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Daniel Leung
88f4b68165 arch/x86: apollo_lake: add MMU regions for I2C controllers
The Apollo Lake SoC has 8 I2C controllers. The MMU regions are
added to allow access.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Daniel Leung
67b48ab2a8 drivers/i2c: i2c_dw: extends driver to support 8 controllers
This adds the necessary driver structs to support a total of 8
I2C controllers. This also allows each I2C controller to have
its own PCI vendor/device IDs.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-27 17:16:18 -04:00
Yannis Damigos
fe321f02fa arch: st_stm32: Fix IRQs number of various SoCs
It corrects the IRQs number of various SoCs.
IRQs number is in conformity with the IRQn_Type
enumeration in SoC header files of STM32Cube
HAL.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-26 08:24:04 -05:00
Andrew Boie
97c06a7ab3 arm: fix assembler offset errors on Cortex-M0
In some kernel configurations, the offset can be greater
than the maximum of 124 for ldr/str immediate offsets.

Fixes: #9113

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-25 20:04:29 -04:00
Shawn Mosley
573f32b6d2 userspace: compartmentalized app memory organization
Summary: revised attempt at addressing issue 6290.  The
following provides an alternative to using
CONFIG_APPLICATION_MEMORY by compartmentalizing data into
Memory Domains.  Dependent on MPU limitations, supports
compartmentalized Memory Domains for 1...N logical
applications.  This is considered an initial attempt at
designing flexible compartmentalized Memory Domains for
multiple logical applications and, with the provided python
script and edited CMakeLists.txt, provides support for power
of 2 aligned MPU architectures.

Overview: The current patch uses qualifiers to group data into
subsections.  The qualifier usage allows for dynamic subsection
creation and affords the developer a large amount of flexibility
in the grouping, naming, and size of the resulting partitions and
domains that are built on these subsections. By additional macro
calls, functions are created that help calculate the size,
address, and permissions for the subsections and enable the
developer to control application data in specified partitions and
memory domains.

Background: Initial attempts focused on creating a single
section in the linker script that then contained internally
grouped variables/data to allow MPU/MMU alignment and protection.
This did not provide additional functionality beyond
CONFIG_APPLICATION_MEMORY as we were unable to reliably group
data or determine their grouping via exported linker symbols.
Thus, the resulting decision was made to dynamically create
subsections using the current qualifier method. An attempt to
group the data by object file was tested, but found that this
broke applications such as ztest where two object files are
created: ztest and main.  This also creates an issue of grouping
the two object files together in the same memory domain while
also allowing for compartmenting other data among threads.

Because it is not possible to know a) the name of the partition
and thus the symbol in the linker, b) the size of all the data
in the subsection, nor c) the overall number of partitions
created by the developer, it was not feasible to align the
subsections at compile time without using dynamically generated
linker script for MPU architectures requiring power of 2
alignment.

In order to provide support for MPU architectures that require a
power of 2 alignment, a python script is run at build prior to
when linker_priv_stacks.cmd is generated.  This script scans the
built object files for all possible partitions and the names given
to them. It then generates a linker file (app_smem.ld) that is
included in the main linker.ld file.  This app_smem.ld allows the
compiler and linker to then create each subsection and align to
the next power of 2.

Usage:
 - Requires: app_memory/app_memdomain.h .
 - _app_dmem(id) marks a variable to be placed into a data
section for memory partition id.
 - _app_bmem(id) marks a variable to be placed into a bss
section for memory partition id.
 - These are seen in the linker.map as "data_smem_id" and
"data_smem_idb".
 - To create a k_mem_partition, call the macro
app_mem_partition(part0) where "part0" is the name then used to
refer to that partition. This macro only creates a function and
necessary data structures for the later "initialization".
 - To create a memory domain for the partition, the macro
app_mem_domain(dom0) is called where "dom0" is the name then
used for the memory domain.
 - To initialize the partition (effectively adding the partition
to a linked list), init_part_part0() is called. This is followed
by init_app_memory(), which walks all partitions in the linked
list and calculates the sizes for each partition.
 - Once the partition is initialized, the domain can be
initialized with init_domain_dom0(part0) which initializes the
domain with partition part0.
 - After the domain has been initialized, the current thread
can be added using add_thread_dom0(k_current_get()).
 - The code used in ztests ans kernel/init has been added under
a conditional #ifdef to isolate the code from other tests.
The userspace test CMakeLists.txt file has commands to insert
the CONFIG_APP_SHARED_MEM definition into the required build
targets.
  Example:
        /* create partition at top of file outside functions */
        app_mem_partition(part0);
        /* create domain */
        app_mem_domain(dom0);
        _app_dmem(dom0) int var1;
        _app_bmem(dom0) static volatile int var2;

        int main()
        {
                init_part_part0();
                init_app_memory();
                init_domain_dom0(part0);
                add_thread_dom0(k_current_get());
                ...
        }

 - If multiple partitions are being created, a variadic
preprocessor macro can be used as provided in
app_macro_support.h:

        FOR_EACH(app_mem_partition, part0, part1, part2);

or, for multiple domains, similarly:

        FOR_EACH(app_mem_domain, dom0, dom1);

Similarly, the init_part_* can also be used in the macro:

        FOR_EACH(init_part, part0, part1, part2);

Testing:
 - This has been successfully tested on qemu_x86 and the
ARM frdm_k64f board.  It compiles and builds power of 2
aligned subsections for the linker script on the 96b_carbon
boards.  These power of 2 alignments have been checked by
hand and are viewable in the zephyr.map file that is
produced during build. However, due to a shortage of
available MPU regions on the 96b_carbon board, we are unable
to test this.
 - When run on the 96b_carbon board, the test suite will
enter execution, but each individaul test will fail due to
an MPU FAULT.  This is expected as the required number of
MPU regions exceeds the number allowed due to the static
allocation. As the MPU driver does not detect this issue,
the fault occurs because the data being accessed has been
placed outside the active MPU region.
 - This now compiles successfully for the ARC boards
em_starterkit_em7d and em_starterkit_em7d_v22. However,
as we lack ARC hardware to run this build on, we are unable
to test this build.

Current known issues:
1) While the script and edited CMakeLists.txt creates the
ability to align to the next power of 2, this does not
address the shortage of available MPU regions on certain
devices (e.g. 96b_carbon).  In testing the APB and PPB
regions were commented out.
2) checkpatch.pl lists several issues regarding the
following:
a) Complex macros. The FOR_EACH macros as defined in
app_macro_support.h are listed as complex macros needing
parentheses.  Adding parentheses breaks their
functionality, and we have otherwise been unable to
resolve the reported error.
b) __aligned() preferred. The _app_dmem_pad() and
_app_bmem_pad() macros give warnings that __aligned()
is preferred. Prior iterations had this implementation,
which resulted in errors due to "complex macros".
c) Trailing semicolon. The macro init_part(name) has
a trailing semicolon as the semicolon is needed for the
inlined macro call that is generated when this macro
expands.

Update: updated to alternative CONFIG_APPLCATION_MEMORY.
Added config option CONFIG_APP_SHARED_MEM to enable a new section
app_smem to contain the shared memory component.  This commit
seperates the Kconfig definition from the definition used for the
conditional code.  The change is in response to changes in the
way the build system treats definitions.  The python script used
to generate a linker script for app_smem was also midified to
simplify the alignment directives.  A default linker script
app_smem.ld was added to remove the conditional includes dependency
on CONFIG_APP_SHARED_MEM.  By addining the default linker script
the prebuild stages link properly prior to the python script running

Signed-off-by: Joshua Domagalski <jedomag@tycho.nsa.gov>
Signed-off-by: Shawn Mosley <smmosle@tycho.nsa.gov>
2018-07-25 12:02:01 -07:00
Aurelien Jarno
97bc5abedf drivers: i2c: stm32: add support for STM32F7
The STM32F7 uses the V2 version of the STM32 I2C controller. Add the
corresponding Kconfig, DTS, DTS fixup and pinmux entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-25 07:19:12 -04:00
Yannis Damigos
302494d35a arch: stm32f4/f7: Add OTG HS defines to dts fixup file
Add OTG HS defines to dts fixup file for STM32 F4 and
F7 series

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-24 22:27:17 -04:00
Zide Chen
98775f34c3 kconfig: decouple realmode boot from CONFIG_JAIHOUSE
Add CONFIG_REALMODE item so that it's possible to configure other
x86 boards to boot from real mode.

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-07-24 15:37:09 -07:00
Ioannis Glaropoulos
90b64489e5 arch: arm: allow processor to ignore/recover from faults
This commit adds the implementation that allows the ARM CPU
to recover from (otherwise fatal) MPU faults. A new error
reason, _NANO_ERR_RECOVERABLE, is introduced. The error
reason is used to suppress fault dump information, if the
error is actually recoverable.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
f713fa5d52 arch: arm: re-organize arm fault handling
This commit does several things:
- It unifies the way the fault inspection is implemented,
  irrespective of the selected fault dumping level.
- It removes the dumping of the Thread ID and faulting
  instruction address, as these are now displayed by
  _NanoFatalErrorHandler.
- It introduces a new debug print directive, to be used
  for the highest dumping level (2).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
afef645279 arch: arm: Call NanoFatalErrorHandler and split out Secure stack dump
This commit implements two changes.
- It splits out the dumping of the Secure stack information to a
  separate function. Dumping will only occur if the highest dump
  level has been selected.
- Forces _Fault() to invoke _NanoFatalErrorHandler, instead of
  _SysFatalErrorHandler. In addition, early return statemets are
  implemented in _Fault(), so the fatal error handler is only
  invoked once.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Ioannis Glaropoulos
f4645561f9 arch: arm: improve documentation of _Fault(.)
This commit improves the documentation of function _Fault(.),
in order to better describe the actual implementation and the
use of the function arguments.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-23 10:50:30 -07:00
Andrew Boie
17282578a9 arc: fix update of ERET on exc return
This code path for returning from an exception wasn't
updating ERET with ESF->pc, resulting in any updates to
the PC by the fault handler being ignored.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-07-20 14:13:09 -04:00
Ramakrishna Pallala
fe48f743f3 arch: arc: Fix Deep Sleep hang issue on Quark SE(ARC)
Fixed the RTC interrupt masking issue on Deep Sleep entry by
explicitly unmasking it on Deep Sleep exit sequence.

Re-oredered the SoC power states such that SYS_POWER_STATE_CPU_LPS is
the lowest possible Low Power State(LPS) and SYS_POWER_STATE_CPU_LPS_2
is the highest possible Low Power State(LPS). This is need to maintain
the LPS state consistency across different architectures.

Also re-mapped the Low Power States and Deep Sleep States as per
Quark SE C1000 data sheet document under Power Management section.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-19 17:12:58 -04:00
Ramakrishna Pallala
2e615181f0 arch: x86: Reorder the SoC power states for Quark SE
Re-oredered the SoC power states such that SYS_POWER_STATE_CPU_LPS is
the lowest possible Low Power State(LPS) and SYS_POWER_STATE_CPU_LPS_2
is the highest possible Low Power State(LPS). This is need to maintain
the LPS state consistency across different architectures.

Also removed the redundant SYS_POWER_STATE_DEEP_SLEEP_2 state.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-19 17:12:58 -04:00
Niranjhana N
414c39fc94 posix: add pthread_key and pthread_once APIs
Added 4 new pthread_key APIs for thread-specific data
key creation, deletion, setting and getting the values.

Added a key list to the posix_struct for threads.

Added pthread_once API.

Signed-off-by: Niranjhana N <niranjhana.n@intel.com>
2018-07-19 08:46:33 -04:00
Alberto Escolar Piedras
15d847add8 native: Add NATIVE_EXIT_TASK hooks
Some of the native application components or drivers need to
do a proper cleanup before the executable exits.
So we provide a macro similar to SYS_INIT but which will be
called just before exiting.
This can be used for freeing up resources, closing descriptors,
or doing any neccessary signaling to any other host process.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-18 15:43:12 -04:00
Andrei Emeltchenko
8a86931e8a board: quark_se_c1000: Add default setting for cc2520 radio
Add default settings for cc2520 radio.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2018-07-18 08:23:00 -04:00
Diego Sueiro
d99f6ada84 arch: Add support for i.MX PWM
Adds definitions, devicetree entries and clock controller
configurations for PWM peripheral.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-17 16:08:22 -05:00
Diego Sueiro
c2454309de arch: Add i.MX7 PWM get clock frequency function
This patch adds the get_pwm_clock_freq function to be used by the
i.MX PWM driver.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-17 16:08:22 -05:00
Daniel Leung
26e83aab35 arch/x86/soc: add SoC configuration for Apollo Lake
This adds the SoC configuration for Apollo Lake. This is based
on the Atom configuration.

Origin: Original

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-07-17 16:27:52 -04:00
Ioannis Glaropoulos
6e41f9e181 arch: arm: enable/disable MPU using API functions
This commit forces arm_mpu_init() to use the provided API
functions to enable and disable the MPU. Besides the clean-up
the commit enforces the MPU driver to use data and instruction
synchronization barriers every time the MPU is enabled. This
is aligned with the programming recommendations by ARM.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-16 20:56:25 -04:00
Anas Nashif
942ab7ed35 esp32: include register headers in soc.h
This fixes a build issue on esp32 that was introduced recently with the
merge of an old PR.

Include the register headers in soc.h rather than soc.c and make them
available to other code via soc.h

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-16 19:00:32 -04:00
Ramakrishna Pallala
a20cc9e78b arch: arm: nrf52: Enable interrupts on wake up from sleep
Enable the interrupts on wake up from low power states

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-07-15 22:48:34 -04:00
Vitor Massaru Iha
f8718758e5 include: drivers: gpio: Turn functions generic - esp32
On 'drivers/i2c_esp32.c' there are functions useful for other
drivers. Functions and struct went moved to:

 * arch/xtensa/soc/esp32/peripheral.h
 * arch/xtensa/soc/esp32/soc.h
 * include/drivers/gpio/gpio_esp32.h

Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>
2018-07-15 16:13:36 -04:00
Jakub Rzeszutko
f0de6e06f8 drivers: serial: nrf: Serial driver modification to use DT
1. dts.fixup files updated with peripheral address and IRQ NUMBER.
2. Peripheral address is taken from DT.
3. IRQ number is taken from DT.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-07-13 11:08:03 +02:00
Ulf Magnusson
3cb9018e23 arch: x86: Kconfig: Fix CACHE_LINE_SIZE default for CPU_ATOM
With Zephyr's prefer-later-defaults behavior, the default value of
CACHE_LINE_SIZE was always 0, because 'default 0' acts like
'default 0 if y'.

Change the code to what was probably the intention (default to 0 unless
CPU_ATOM).

It looks like CACHE_LINE_SIZE is never used in the code when
CACHE_LINE_SIZE_DETECT is on, so maybe things could be simplified
further.

Piggy-back some prompt style consistency cleanups.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-07-12 23:08:43 -04:00
Ioannis Glaropoulos
8bfddb52e5 arch: arm: mpu: fix _get_region_ap(.) function
This commit fixes a bug in _get_region_ap(.) by adding
parentheses to enforce the correct operator precedence.

Fixes #8864.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-12 13:00:37 -05:00
Aurelien Jarno
9107e3dac8 drivers: usb: add support for USB OTG FS on STM32F7
The STM32F7 uses the same USB OTG FS controller than the STM32F4 series.
It is therefore trivial to add support for it, by adding the DT fixup
and pinmux macros, and the DT entries in stm32f7.dtsi. Keep it disabled,
it should be enabled at the board level.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-11 16:28:10 -05:00
Aurelien Jarno
8d1664c2f7 arch: arm: mpu: enable WBWA caching on per thread user RAM
Update _get_region_attr_by_type used to set up the user regions
on a per thread basis to match the REGION_USER_RAM_ATTR macro. Caching
attributes were set "Outer and inner write-through. No write allocate.",
this patch changes it to "Outer and inner write-back. Write and read
allocate.".

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-11 10:55:31 -04:00
Wayne Ren
d27aadf941 arch: arc: add nsim support in soc
add nsim soc support, two configs are contained

* em with arc MPUv2
* em with arc SecureShield and MPUv3

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-07-10 19:05:13 -04:00
Kumar Gala
d76e39f8d3 arch: atmel_sam0: Fix Kconfig warnings
We were missing a few SOC_PART_NUMBER.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 15:28:32 -05:00
Sean Nyekjaer
781a2f0275 arch: add support SAMD20 used in the SAMD20 Xplained Pro Board
This add basic support the SAMD20 inkl. SPI and UART

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
2018-07-10 12:56:44 -05:00
Sean Nyekjaer
31aaf07719 arch: atmel_sam0: move clk config options to common Kconfig
The SAMD0 Family have almost the same clock options.
The samd20 and samd21 only clocks is not implemented yet.

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 12:56:44 -05:00
Christian Taedcke
6d5206e7b0 arm: exx32: Add additional include to efm32wg soc.h
This keeps the efm32wg soc.h in sync with the efr32fg1p soc.h.
This include is currently not necessary, but will be for further
peripheral drivers.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-07-10 12:53:50 -05:00
Christian Taedcke
496b799474 arm: exx32: Add Silabs EFR32FG1P soc files
The Silicon Labs EFR32FG1 Flex Gecko MCU includes:
	* Cortex-M4F core at 40MHz
	* up to 256KB of flash and 32KB of RAM
	* integrated Sub-GHz and/or 2.4GHz radio
	* multiple low power peripherals

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-07-10 12:53:50 -05:00
Maureen Helm
530a71310e arm: nxp: mpu: Consolidate k64 mpu regions
Reduces the number of mpu regions statically reserved at boot time by
one, giving a total of five. We originally sought to reduce the total to
three: 1 background region with lowest precendence for supervisor r/w, 1
flash region, and 1 sram region. However, the nxp mpu hardware does not
give precedence to any region over another, and thus we cannot revoke
access from the background region with a higher priority region. This
means we cannot support hardware stack protection with a single
background region.

Instead, create two background regions that cover the entire address
space, except for sram.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-07-10 12:46:04 -04:00
Kumar Gala
b3d34d2e4c arch: arm: nrf52: Support UARTE defines in dts.fixup
If we select UART0 as UARTE we will get different defines from the
generation script.  Support both UART and UARTE for UART0.  Also fixup
UART1 defines since this will always be UARTE.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-10 08:54:30 -05:00
Diego Sueiro
970c4f9cf3 arch: Add imx7d_m4 i2c definitions
Adds all necessary i2c definitions and configurations for imx7d_m4 soc.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-07-06 15:55:57 -05:00
Yong Jin
8776835bd6 arch: arm: stm32: add basic support for STM32F769 SoC
The STM32F769 has more interrupts and features than the STM32F746,
but the basic support is similar with STM32F746

Signed-off-by: Yong Jin <jinyong.iot@foxmail.com>
2018-07-06 09:56:25 -05:00
Istvan Bisz
5aaf827a3e arch: arm: stm32f2: remove core zephyr header inclusions from soc.h
The stm32f2 version of soc.h misses the changes done in commit
aee97be ("arch: arm: soc: remove core zephyr header inclusions
from soc.h").

Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
2018-07-06 09:47:18 -05:00
Yannis Damigos
4e26f9c3a6 arch: stm32f0/f1/f3/l0: remove core zephyr header inclusions
Apply the changes done in commit aee97be to F0, F1, F3, L0 series.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-07-06 09:46:09 -05:00
Maureen Helm
41dd6622ce arm: Print NXP MPU error information in BusFault dump
The NXP MPU triggers a bus fault when a memory access error occurs. Add
support in the bus fault handler to dump error details from the NXP MPU,
including the port number, mode (supervisor or user), address, bus
master number, and regions.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-07-05 13:42:40 -05:00
Kumar Gala
889b290a98 arch: arm: beetle: Pull in CMSDK header for CMSIS support on Beetle
Pulled CMSDK_BEETLE.h from mbed-os as a starting point to enable CMSIS
support on Beetle.  Trimed the file down that what we need on Zephyr
(dropped Device Specific Peripheral Section and system_CMSDK_BEETLE.h).

This lets us drop soc_mpu.h which duplicates MPU info that is defined in
CMSIS headers.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-07-05 13:40:27 -05:00
qianfan Zhao
7e2f6ebc7b stm32f2: add stm32f207xe soc
Used and tested(blinky, hello_world) on out of tree custom board.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
bdeece01b8 driver: uart_stm32: add support for stm32f2 series
clear RXNE flag in fifo_read, remove TEACK and REACK
check when uart_stm32_init because stm32f2 doesn't
has those flags.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
dffac9ab74 driver: interrupt_controller: Add support for stm32f2
Add kconfig and c code for stm32f2 interrupt controller driver

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6fb7b04461 drivers: stm32-gpio: Provide GPIO driver for stm32f2
Add necessary GPIO defines for the stm32f2 series soc

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6091a7fd50 drivers: clock_control: Add support for stm32f2
Add clock control support for the stm32f2

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
85d2633af2 stm32f2: add stm32f207xg soc
Add stm32f207xg soc to make nucleo-f207zg work.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
qianfan Zhao
6511c4122d arm: stm32f2: Add support for stm32f2 series
Add necessary kconfig and DTS files for stm32f2 series

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-07-05 11:26:07 -05:00
Findlay Feng
a36bd915af arch: ARM: Change the march used by cortex-m0 and cortex-m0plus
Use -march=armv6s-m to ensure the svc directive exists

Signed-off-by: Findlay Feng <i@fengch.me>
2018-07-04 16:46:40 -04:00
Ioannis Glaropoulos
df41ed885a arch: arm: mpu: replace literals with CMSIS bitsets
This commit refactors internal functions in arm_mpu.c to use
bitsets and functions taken directly from ARM CMSIS instead of
hardcoded arithmetic literals. In several internal functions
some part of the implementation is abstracted further in inline
functions or convenience macros, to facilitate extending the
arm_mpu.c for ARMv8-M. In addition, the commit adds minor
improvements in internal function documentation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
d1944109a9 arch: arm: abstract MPU attribute generation in inline function
This commit abstracts the attribution generation for an MPU
region, determined based on a supplied configuration and the
given size, from the actual implementation, which is placed
in a separate inline function. This allows to have multiple
implementations of attribution generation for different ARM
MPU drivers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
2b79fceb84 arch: arm: refactor _region_init(..) function
This commit refactors the _region_init(..) internal MPU driver
function so it gets the region index and a struct arm_mpu_region
as aruments. The latter holds the MPU region configuration that
is to be applied to the region determined by the index argument.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:25:02 -04:00
Ioannis Glaropoulos
e202e04499 arch: arm: nrf: conditionally compile mpu_regions.c
This commit enforces conditional compilation of mpu_regions.c
in nrf52/CMakeLists.txt depending on whether ARM_MPU_NRF52X
K-option is defined.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-04 08:21:58 -04:00
Aurelien Jarno
5aa09c6baa drivers: entropy: stm32: add support for STM32F7
All the STM32F7 SoCs have a TRNG. Adding support for it is just a matter
of tweaking the #ifdef and including the right file from HAL.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-03 22:48:08 -04:00
Ioannis Glaropoulos
1ed37e77ce arch: arm: beetle: duplicate ARM MPU registers' definition
Duplicate the ARM MPU-related registers' definitions
specifically for Beetle SOC which is not compliant with
ARM CMSIS and does not include the ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 18:43:10 -04:00
Ioannis Glaropoulos
559249ee01 arch: arm: Remove redundant HAL definition for ARM MPU
This commit removes the redundant HAL definition for the ARM
Cortex-M MPU registers, and modifies the ARM MPU driver
implementation to directly use the provided HAL from CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 18:43:10 -04:00
Sebastian Bøe
347f9a0a2d cmake: LD: Specify the entry point in the linker scripts
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.

This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command

ENTRY(CONFIG_KERNEL_ENTRY)

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-07-03 17:18:14 -04:00
Ioannis Glaropoulos
d20dac8254 arch: arm: minor refactor in arm_core_mpu_configure_user_context
This commit refactors arm_core_mpu_configure_user_context() so
it can use directly arm_core_mpu_configure().

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 17:11:14 -04:00
Ioannis Glaropoulos
33d3f14b15 arch: arm: add compile-time guards for arm_mpu code
This commit places all the implementation in arm_mpu.c within
build-time guards, ensuring that it is compiled-in only if the
kernel features requiring MPU are present (i.e. USERSPACE,
APPLICATION_MEMORY, or MPU_STACK_GUARDS). An exception to that
is the code required for MPU initialization, which is left out,
as MPU initialization occurs always if MPU is present.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 17:11:14 -04:00
Leandro Pereira
91220ba640 boards: native_posix: Add option to build with Address Sanitizer
Address Sanitizer helps finding issues related to memory: buffer
overflows, usage of uninitialized memory, etc.  This is available in
both Clang and GCC for a while, and, since the POSIX port is only
meant for testing, this will help find issues.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-07-03 17:06:25 -04:00
Aurelien Jarno
6ee562b754 arch: arm: stm32: add basic support for STM32F723 SoC
The STM32F723 has more interrupts than the STM32F746 due to the
additional SDMMC controller. Besides that the changes are very
similar to the ones of the STM32F746.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-07-03 13:53:36 -05:00
Ioannis Glaropoulos
059952c8e1 arch: arm: update compile options for DSP
This commit updates the compile options in cmake to distinguish
between ARMv8-M Mainline MCUs with or withouth the optional DSP
extension. A new Kconfig option: ARMV8_M_DSP, is introduced, to
signify the use of an ARMv8-M MCU with DSP support.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-03 12:17:13 -05:00
Piotr Zięcik
97adff57f1 arch: arm: nrf: Enable SEGGER RTT on all Nordic SoCs
All chips from nRF51 and nRF52 series support Segger RTT,
so we can enable it if given series is used.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-07-03 17:51:50 +02:00
Ioannis Glaropoulos
e325510d59 arch: arm: nrf: minor header files' clean up in soc/nrfx
This commit cleans up source files in soc/nrf51 soc/nrf52
folders by removing unnecessary header inclusions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-02 16:50:10 +02:00
Ioannis Glaropoulos
0677812910 arch: arm: nrf: remove kernel_includes.h from nRF5x soc.h inclusions
This commit removes the inclusion of kernel_includes.h from
the nRF51 and nRF52 soc.h headers. This prevents from an
inclusion cycle formation on soc.h. In the wake of
kernel_includes.h removal, necessary header files have been
added in several source files to be able to compile Zephyr for
nRF5x SOCs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-07-02 16:50:10 +02:00
Anas Nashif
bebda565b5 clang: fix for x86 iamcu
Clang, build IAMCU with -miamcu.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-01 22:58:09 +02:00
Anas Nashif
72edc4e15f clang/llvm: add initial configuration file for clang
Add an LLVM backend and a clang toolchain variant to support building
with llvm coming with popular Linux distributions.

This has been tested with X86 boards:
- quark_d2000_crb
- quark_se_c1000_devboard/Arduino 101

Use:

export ZEPHYR_TOOLCHAIN_VARIANT=clang

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-07-01 22:58:09 +02:00
Ioannis Glaropoulos
7c9a1f0f76 arch: arm: soc: add explanatory comment for kernel headers' inclusion
This commit adds an explanatory comment in all soc.h headers,
where kernel_includes.h header has been included, to stress out
that this header must be included after SOC-specific headers are
brought in. The reason is the fact that kernel_includes.h needs
the ARM CMSIS definitions, which are brought in by the
SOC-specific header inclusions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-29 17:53:15 -05:00
Aurelien Jarno
fa83a4d131 arch: arm: stm32f7: remove core zephyr header inclusions from soc.h
The stm32f7 version of soc.h misses the changes done in commit
aee97be710 ("arch: arm: soc: remove core zephyr header inclusions
from soc.h") as it was not merged at that time. Fix that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-29 11:52:51 -05:00
Alberto Escolar Piedras
2889f5f02c native: Do not ignore format-truncation warnings
Reverting 5124711d87
as issue #5732 is no more.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-06-28 19:58:55 +02:00
Kumar Gala
e860775873 Revert "arch: arm: stm32: correct include issue"
This reverts commit 30529da0e4.

We should include SoC headers from HALs before we include
kernel_includes.h.  On ARM this is needed because we tend to get CMSIS
related defines setup by the HAL headers.

Fixes: #8593

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-06-28 10:54:38 -05:00
Yurii Hamann
1fdc790ca2 serial: stm32: STM32F7 UART support
The patch adds serial driver support for STM32F7 family
microcontrollers, includes pinmux definitions and DTS fixup file.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
a229500d23 drivers: gpio: stm32: STM32F7 GPIO support
This patch adds GPIO support for STM32F7 family microcontrollers.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
cfb25c74a0 drivers: flash: stm32: STM32F7 flash memory suport
Added flash memory support for STM32F7 family microcontrollers

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
4df673f3fc drivers: clock_control: STM32F7 family clock control
This patch adds clock control support for STM32F7 family
microcontrollers.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
Yurii Hamann
7d8d280db3 arch: arm: stm32: Basic STM32F7 family support
The patch includes support for STM32F746xG subfamily.
Related to issue #6981.

Signed-off-by: Yurii Hamann <yurii@hamann.site>
2018-06-28 08:29:32 -05:00
qianfan Zhao
e7205be03d arch: stm32: Enable HAS_SEGGER_RTT on all stm32 SoCs
Enable HAS_SEGGER_RTT to allow user to select use of SEGGER RTT
and SystemView solution.

SEGGER provide a firmware that can convent ST-Link to J-Link,
And RTT is supports all stm32 SoCs, so lets enable RTT default

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-06-27 15:48:38 -05:00
Andrew Boie
8bcffefb33 arch: arm: clean up MPU code for ARM and NXP
* We are now *much* better at not reserving unnecessary
system MPU regions based on configuration. The #defines
for intent are now an enumerated type. As a bonus, the
implementation of _get_region_index_by_type() is much
simpler. Previously we were wasting regions for stack guard
and application memory if they were not configured.

* NXP MPU doesn't reserve the last region if HW stack
protection isn't enabled.

* Certain parts of the MPU code are now properly ifdef'd
based on configuration.

* THREAD_STACK_REGION and THREAD_STACK_USER_REGION was a
confusing construction and has now been replaced with
just THREAD_STACK_REGION, which represents the MPU region
for a user mode thread stack. Supervisor mode stacks
do not require an MPU region.

* The bounds of CONFIG_APPLICATION_MEMORY never changes
and we just do it once during initialization instead of
every context switch.

* Assertions have been added to catch out-of-bounds cases.

Fixes: #7384

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-06-27 12:56:38 -07:00
Christophe Priouzeau
30529da0e4 arch: arm: stm32: correct include issue
This commit correct the issue introduce by aee97be which
changed the order of header inclusion that lead
to warning generation at compilation, that truend into errors
in CI.
This commit reinstantiate the initial header inclusion order.

Fixes #8563
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
2018-06-27 12:35:27 -05:00
Ulf Magnusson
f1f1fb41bd arch: arm: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Also simplify the definition of CC3220SF_DEBUG. 'default's can be other
symbols too, not just literal values. The condition for the symbol to be
visible (user-configurable) can be put directly on the prompt as well.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
f428d8dacf arch: arc: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Also fix the 'default' on XIP. Due to Zephyr's prefer-later-defaults
behavior, it was always set to 'y' (when the dependencies were
satisfied).

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
8cb6fb7223 arch: xtensa: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
b0156b2c48 arch: nios: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
81d61601a8 arch: riscv32: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
87ecbe7f48 arch: x86: Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Ulf Magnusson
aed5e360ee arch/Kconfig: Remove redundant 'default n' properties
Bool symbols implicitly default to 'n'.

A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-26 11:07:57 -05:00
Sebastian Bøe
a1e806bf44 gen_isr_tables: Delete the dead code accompanying .intList.num_isrs
intList has been populated with the number of isrs, aka interrupts,
but nothing has not been using this information so we drop it and
everything used to construct it.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-25 12:54:49 -07:00
Carles Cufi
0f6bd5c891 arch: arm: nrf: Add support for the nRF52810
The nRF52810 is a low-cost variant of the nRF52832, with a reduced set
of peripherals and memory. This commit adds basic support for it in the
arch SoC and dts folders.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
2018-06-25 19:34:33 +02:00
Maureen Helm
54d1a608ff imxrt1050: Disable low-power modes
The imxrt1050 is configured to use SYSTICK for the kernel timer, but
SYSTICK cannot wake up the soc from low-power modes. Disable low-power
modes on this soc until we have support for an alternative timer.

This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An
earlier version of the board (EVK, not EVKB), had A0 silicon which
by default did not enter low-power mode on a wfi.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-23 11:00:20 +02:00
Johann Fischer
c36e800e8e usb: remove all CONFIG_*_EP_ADDR options
Remove all CONFIG_*_EP_ADDR options but keep the default
values for it, as they are necessary to find ep_addr in
usb_ep_cfg_data associated with bEndpointAddress in
interface descriptor.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-06-22 12:30:55 -04:00
Ioannis Glaropoulos
aee97be710 arch: arm: soc: remove core zephyr header inclusions from soc.h
This commit removes the direct inclusions of device.h or gpio.h
from soc.h header files in ARM SOCs, to avoid soc.h include
kernel.h.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-21 22:28:00 +02:00
Bartosz Sokolski
92778e4438 arch: soc: nrf52: add UART1 to dts fixup
Current fixup supports only UART0 while there is also UART1

Signed-off-by: Bartosz Sokolski <bartosz.sokolski@nordicsemi.no>
2018-06-21 13:49:13 +02:00
Sebastian Bøe
aed0b6c4bd isr_tables: Simplify how the sw_irq_handler function is used
This is a migration from using code generation to using the C language
which we in the general case we should aways strive towards.

It is equivalent to the simplification that was done with
_irq_spurious here:
https://github.com/zephyrproject-rtos/zephyr/pull/7574

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-20 15:39:29 -04:00
Joakim Andersson
5204fd7061 arch: arm: Set Zero Latency IRQ to priority level zero:
Set Zero Latency IRQ to priority level zero and SVCs to priority level
one when Zero Latency IRQ is enabled.
This makes Zero Zatency truly zero latency when the kernel has been
configured with userspace enabled, or when IRQ offloading is used.

Exceptions can still delay Zero Latency IRQ, but this is considered
ok since exceptions indicate a serious error, and the system needs to
recover.

Fixes: #7869

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2018-06-20 18:05:02 +02:00
Karol Gugala
1765d75ff4 riscv32: riscv-privilege: Microsemi Mi-V support
This commit adds support for Microsemi Mi-V RISC-V softcore CPU
running on the M2GL025 IGLOO2 FPGA development board.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-20 11:57:07 -04:00
Karol Gugala
23a5b5d171 riscv32: riscv-privilege: integrate common code
This commit moves code from fe310 platform into RISC-V privilege common
folder. This way the code can be reused by other platforms in future.

signed-off-by: Karol Gugala <kgugala@antmicro.com>
2018-06-20 11:57:07 -04:00
Mieszko Mierunski
dc1c2742b6 boards: nrf: Moved SDA and SCL pin configuration to DTS for nRF boards
SDA and SCL pins can now be configured through DTS.
Pins on development kits have been assigned according to arduino
headers.

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2018-06-20 13:38:18 +02:00
Stanislav Poboril
631eedd334 arch: Add imx6sx m4 soc support
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one
Cortex A9 core and one Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A9 core (running Linux) via RPMsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A9 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A9 can perform these steps at bootloader level after the Linux
system has booted.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-06-19 17:08:51 -05:00
Sebastian Bøe
8f321b48ac isr_tables: Simplify how the spurious irq function address is found
Instead of finding the address of the spurious irq function in the
intList section we now rely on the linker to find the address in the
_irq_spurious symbol.

This is a migration from using code generation to using the C language
which we in the general case we should aways strive towards.

In this specific case it makes the generated code 'irq_tables.c'
easier to read as we replace magic numbers with the &_irq_spurious
token.

Also, the path through the build system that _irq_spurious makes is
much shorter, so it is much easier for a user to understand how it is
used.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-06-19 13:46:35 -07:00
Ioannis Glaropoulos
bf15988510 arch: arm: beetle: duplicate CMSIS MPU-related macros
Duplicate the CMSIS MPU-related macro definitions specifically
for Beetle SOC which is is not compliant with ARM CMSIS and
does not include the ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
1547abb57d arch: arm: use CMSIS defines for MPU_RASR register bit setting
This commit removes the macro definitions for MPU_RASR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
8d52c17166 arch: arm: use CMSIS defines for MPU_RBAR register bit setting
This commit removes the macro definitions for MPU_RBAR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Ioannis Glaropoulos
0a41e23ac0 arch: arm: use CMSIS macro defines for MPU_CTRL register bit setting
This commit removes the macro definitions for MPU_CTRL register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-19 15:18:58 -05:00
Jakub Rzeszutko
eb84eff27f arch: arm: nrf: modification of config parameter: SOC_SERIES_NRF52X
Configuration parameter SOC_SERIES_NRF52X is common for all NRF5X SoCs.
Due to that it cannot select: CPU_HAS_FPU because not all Nordic
microcontrollers supports that. Selection of this parameter was moved
to configuration of each SoC in Kconfig.soc file.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-19 20:02:51 +02:00
Jakub Rzeszutko
1fa9d84332 arch: arm: nrf: add hardware description for nrf Kconfig files
Created NRF5x peripheral list that can be used to describe each
NRF5x SoC. Basing on this description Kconfig file can display
and allow to configure only these drivers that are available
for particular SoC.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-19 20:02:51 +02:00
Andrzej Głąbek
687355c9af arch: arm: nrf: Use SystemInit() from MDK in SoC initialization
Replace code that handles erratas and performs other SoC-specific
initialization, that was actually copied from SystemInit() provided
in MDK for particular SoCs, with a call to SystemInit().

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-06-19 14:25:39 +02:00
Alex Tereschenko
3c1a78ea0d cmake: replace PROJECT_SOURCE_DIR with ZEPHYR_BASE
Both variables were used (with the same value) interchangeably
throughout CMake files and per the discussion in GH issue,
ZEPHYR_BASE is preferred.

Also add a comment with explanation of one vs. the other.

Tested by building hello_world for several boards ensuring no errors.

Fixes #7173.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-18 15:25:55 -04:00
Aurelien Jarno
7688f49065 drivers: usb_dc_stm32: change all endpoints to bidirectional
The various STM32 reference manuals sometimes define the USB endpoints
as IN or OUT only and sometimes as bidirectional, even in the same
manual. This is likely because the OTG implementation has one set of
registers for the IN endpoints and one other set for OUT endpoints.
However at the end a given endpoint address can both transmit and
receive data.

This causes some confusion how to declare the endpoints in the device
tree, and depending on the SoC, they are either the same number of IN
and OUT endpoints declared, or they are declared as bidirectional. At
the end it doesn't really matter given how the driver uses those values:

    #define NUM_IN_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
                       CONFIG_USB_NUM_IN_ENDPOINTS)

    #define NUM_OUT_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
                        CONFIG_USB_NUM_OUT_ENDPOINTS)

    #define NUM_BIDIR_EP NUM_OUT_EP

This patch therefore cleanup the driver, the DTS, and the DTS fixups to
only define the number of bidirectional endpoints.

In addition to the cleanup, that fixes a regression introduced by commit
52eacf16a2 ("driver: usb: add check for endpoint capabilities"), which
introduced a wrong check for SoC only defining the number of
bidirectional endpoints.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-18 15:24:15 -04:00
Alexander Wachter
c601f3be67 can: Add can support for STM32L432
This commit enables CAN on the STM32L432.
Tested on nucleo l432ck with external transceiver and loopback mode.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-06-18 15:23:29 -04:00
Alex Tereschenko
0824ec6409 dt: nrf52840: remove 0x from USBD address
The prepended 0x causes DTC warnings and shouldn't be there.

Tested by compiling hello_world for nrf52840_pca10056 before and after.

Fixes #8334.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-16 18:00:56 +02:00
Ioannis Glaropoulos
7a864bb79b arch: arm: define and implement ARM IRQ target state API
This commit contributes the definition and the implementation
of an API for ARM MCUs to configure and get the configuration
of the security state targeted by a given external IRQ line.
The API is only available in Secure ARM Firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 15:53:11 +02:00
Ioannis Glaropoulos
fe3cd4c8ff arch: arm: convenience wrappers for C variable Non-Secure permissions
Declare and implement convenience wrappers to evaluate Non-Secure
read and write permissions of C variables using the cmse address
range intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
879366120e arch: arm: implement cmse address range check (secure)
This commit contributes the implementation of the CMSE
address range permission checks based on the ARMv8-M
address range check intrinsics exlusicely for Secure state.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
d426adccaa arch: arm: refactor function to align with the adopted api
Refactor arm_cmse_mpu_region_get(.) function, so its signature,
documentation, and implementation align with the rest of functions
for obtaining MPU, SAU and IDAU region numbers via the TT instruction.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
f630559e81 arch: arm: Define and implement API for test target (Secure)
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Tests Target (TT, TTA)
instruction support (for Secure requests).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:14:27 +02:00
Ioannis Glaropoulos
0a2dcaaf8f arch: arm: introduce dependencies for CPU_CORTEX_M_HAS_SPLIM option
This commit introduces additional dependencies and selection
scheme for CPU_CORTEX_M_HAS_SPLIM, for Zephyr Non-Secure builds
on ARMv8-M MCUs with Security Extensions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
13dc376240 arch: arm: introduce ARMV8_M_SE option
This commit introduces the ARMV8_M_SE K-config option
to signify the use of an ARMv8-M MCU with support for
Security Extensions. It also introduces dependences of
ARM_(NON)SECURE_FIRMWARE on ARMV8_M_SE.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
dd640f143e arch: arm: introduce ARM_NONSECURE_FIRMWARE option
This commit introduces the K-config option
ARM_NONSECURE_FIRMWARE, to indicate a Zephyr firmware image
that is intended to execute in Non-Secure state.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Ioannis Glaropoulos
158ea44ed3 arch: arm: improve help text for ARM_SECURE_FIRMWARE
This commit improves the help text description for K-config
option: ARM_SECURE_FIRMWARE.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-15 13:03:25 +02:00
Yasushi SHOJI
2e0af08e55 build: remove unused CMakeLists.txt
lib/libc/minimal/source/CMakeLists.txt and
lib/libc/minimal/source/stdout/CMakeLists.txt was introduced in
12f8f7616 but it is not used by the build system.  CMakeLists.txt in
the parent dir lib/libc/minimal/CMakeLists.txt adds C files to the
target with the lines like:

    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/atoi.c
    ${CMAKE_CURRENT_SOURCE_DIR}/source/stdlib/strtol.c

To make other empty CMakeLists.txt explicit, this commit adds a
comment line to them.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
2018-06-14 15:02:02 -04:00
Aurelien Jarno
bb55155d5b arch: arm: core: cortex_m: add a barrier before the dummy FP instruction
On Cortex-M7 CPU (at least on STM32F723), the dummy move FPU instruction
is executed before the FPU lazy state preservation is disabled. Add an
instruction synchronization barrier before it to avoid that.

At the same time, remove the data synchronization barrier after the
dummy move as it does not have any effect on RAM or registers.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-06-14 19:09:34 +02:00
Marc Reilly
6c60abb03b drivers: gpio: add dts support for nrf52 gpio
This adds basic support for declaring gpio nodes in dts for nrf52.
The dts.fixup provides mapping for the generated defines to the config
defines currently used by the nrf gpio driver.

Existing boards that use nrf52 are updated.

Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
2018-06-14 15:56:39 +02:00
Tomasz Gorochowik
e86c53b48f arch: arm: atmel_sam: Map the whole RAM in MPU
The extra region is wrapped in an "ifdef" as two MPU regions are used
only if the total memory size is not a power of two.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2018-06-13 16:12:05 -07:00
Tomasz Gorochowik
31aa9b9ad1 arch: arm: atmel_sam: Use a single RAM region when possible
There is no need for two RAM regions when the total amount of memory is
a power of two. With this change it will be possible to map the whole
memory and save one MPU region for such cases.

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
2018-06-13 16:12:05 -07:00
Gautier Seidel
77643677a1 esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b
Recent ESP-IDF provides OS-agnostic wifi binary, needed by #3723

Closes #8240

Signed-off-by: Gautier Seidel <gautier.seidel@tado.com>
2018-06-13 18:53:43 -04:00
Ulf Magnusson
7f5203d370 kconfig: Remove UART_QMSI_{0,1}_NAME Kconfig reference
This symbol was removed by commit 17c6456678 ("drivers/uart: Use dts
to set uart priorities for QMSI driver"). The setting should come from
DTS now.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-13 13:35:56 -04:00
Ulf Magnusson
f177fb88a0 arch: arc: Fix reference to removed NSIM Kconfig symbol
The NSIM symbol was removed in commit 9bc69a46fa ("boards: Update arc
em_starterkit support from 2.2 to 2.3").

Guess that UART_NSIM should be used here now, similar to what was done
in commit 45221a9706 ("serial: nsim: Fix impossible-to-enable
CONFIG_UART_NSIM").

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-06-13 13:35:56 -04:00
Vinayak Kariappa Chettimada
070c1ae041 soc: nRF52x: Add Kconfig options to enable DC/DC converter
Added a hidden Kconfig option in arch/arm/soc/nordic_nrf
which is selected by selecting DC/DC circuitry being present
in the board.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
2018-06-13 18:56:54 +02:00
Savinay Dharmappa
b7c4c0302c dts: riscv32: riscv32-qemu: Add device tree support
add device tree support for riscv32-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-06-13 08:47:52 -04:00
Erwan Gouriou
2800729614 arch/stm32: remove irq definition files
Since they are not used anymore because can be replaced
by CMSIS definition or generated from device tree,
remove IRQ definition file soc_irq.h

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-06-13 11:43:56 +02:00
Ioannis Glaropoulos
8c53f2422c arch: arm: set VECTOR_ADDRESS to _vector_start
This commit sets VECTOR_ADDRESS in prep_c.c directly to the
value of _vector_start for XIP images for MCUs which have the
VTOR register.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-12 17:28:46 +02:00
Jakub Rzeszutko
3f99eefe5a drivers: uart: Rename nrf5 namings to nrfx
UART driver renamed to keep the same convention as SPI and TWI drivers.
All substrings: "UART_NRF5" in defines renamed to  "UART_NRFX_UART".

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-12 13:21:18 +02:00
Jakub Rzeszutko
e7252fbbfe drivers: uart: Refactor nrf uart shim
Replace all register defines and calls with Nordic nrfx HAL.
Simplification of uart shim - assumed only one uart instance.
Added parity bit to configuration options.

Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
2018-06-12 13:21:18 +02:00
Johann Fischer
2055b84f79 boards: frdm_kl25z: add USB support
Add USB support to FRDM_KL25Z board.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-06-12 04:09:50 -04:00
Florian Vaussard
653d75cfba pwm: stm32: Add PWM fixup for STM32* and remove Kconfig options
Add fixup info for PWM nodes on STM32F0/F1/F3/F4/L4 and remove the
conflicting Kconfig symbols to fully switch STM32 PWM to device tree.

Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
2018-06-12 03:54:26 -04:00
Andy Ross
41070c3b35 arch/arm: Fix locking in __pendsv
The PendSV handler sits below the priority of other OS interrupts, but
it was inspecting kernel state before masking those interrupts out!

Move the locking to the top.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-06-11 20:15:48 -04:00
Ioannis Glaropoulos
61439b01c2 arch: arm: remove redundant flag
This commit removes the arm_mpu_enabled status flag in the ARM
MPU driver. This flag is not needed, because the value of the
MPU_CTRL register stays the same while the MPU is enabled, and
is cleared to 0 when the MPU is disabled. Therefore, we do not
need to prevent from having the enable or the disable operation
to be called multiple times.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
dbede45dbe arch: arm: improve inline comment in _arm_mpu_config/enable
In _arm_mpu_config provide a more detailed description of the
effect of MPU PRIVDEFENA flag when enabling the ARM MPU.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
7b56b448f6 arch: arm: accelerate _get_num_regions() for Cortex-M0+, M3, and M4
ARM Cortex-M0+, M3, and M4 MCUs have a fixed number of 8 MPU
regions, if MPU support is implemented. Therefore, we can
implement _get_num_regions() to return a constant, if CPU
is one of the above Cortex variants. _get_num_regions() is
invoked often in the code, so this solution increases processing
efficiency. A sanity check is implemented in arm_mpu_init(), to
ASSERT if the number of regions provided by hardware does not
match the expected (default) value.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Ioannis Glaropoulos
ab81d2c7ab arch: arm: block ARM_MPU K-option in Cortex-M0
This commits adds a dependency for ARM_MPU on !CPU_CORTEX_M0,
so an accidental selection or ARM_MPU in ARM Cortex-M0 MCUs
will signal a K-config warning.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-06-11 17:44:18 -04:00
Rajavardhan Gundi
4ec773f276 DTS: intel_s1000: Clean up I2C and UART stuff from soc.h
Clean up some remnant stuff related to I2C and UART from soc.h
and put it in dts.fixup

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Rajavardhan Gundi
e5b0e9ac07 DTS: interrupt controller: Define IRQ priorities for CAVS & DW ICTL
IRQ priorities for CAVS and DW were previously defined in Kconfig.
They are now defined via DTS and removed from Kconfig.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-06-11 17:27:58 -04:00
Wayne Ren
d5bc9d7bee arch: arc: adjust privileged stack size of arc to 384 bytes
Considering the case of call of printk, interrupt and
other cases, adjust the privileged stack size of arc to
384 bytes to avoid the the overflow of privileged stack.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-11 09:05:15 -05:00
Wayne Ren
97d0436486 arch: arc: use top of isr stack as exception stack and bug fixes
* re-use top of isr stack as exception stack
* bug fixes in irq offload's implementation
* improve kernel oops implementation

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-11 09:05:15 -05:00
Anas Nashif
1c4fe3edc0 arch/arc: Set the right priority for ADC/AON on quark_se
ARC has only 2 priorities, 0 or 1. So let's set the right priority for
ADC and AON.

Fixes #8302

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-06-11 08:52:24 -05:00
Wayne Ren
c63298ea65 arch: arc: improve the reset code
This commit improves the reset of arc:
* make the processor in the correct status
* clear interrupt related regs

this may improve or fix #6515

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
fb3d2d3785 arch: arc: remove unused codes
base.user_options is already set in k_thread_
user_mode_enter

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
5dd552e66b arch: arc: STACK_CHECK_FAIL of STACK_CHECK not hang the system
Whether it should hang the system it not decided finally.
But remove it here to let some tests pass.

Fixes #8032

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Wayne Ren
5b6f860539 arch: arc: use a separate stack for exception handling
* use a separate stack for exception handling, this
will gurantee the exception handling always work, not
affected by some speical cases, e.g., stack check exception
or mem. protection exception at the exception entry.

* this commit can fix the second case of #8092

* note: the thread switch is still possible in exception
handling, e.g, caused by thread_abort. But the switched out
thread cannot be recovered, as the thread context is not
setup.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-08 16:37:22 -05:00
Andrew Boie
2dd91eca0e kernel: move thread monitor init to common code
The original implementation of CONFIG_THREAD_MONITOR would
try to leverage a thread's initial stack layout to provide
the entry function with arguments for any given thread.

This is problematic:

- Some arches do not have a initial stack layout suitable for
this
- Some arches never enabled this at all (riscv32, nios2)
- Some arches did not enable this properly
- Dropping to user mode would erase or provide incorrect
information.

Just spend a few extra bytes to store this stuff directly
in the k_thread struct and get rid of all the arch-specific
code for this.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-06-06 14:26:45 -04:00
Erwan Gouriou
7f7718a09a arch: stm32: remove .hex binary build by default
BUILD_OUTPUT_HEX was enabled by default for stm32 SoCs.
This should not be the default setting and besides it has no
effect because of 'default n' in misc/Kconfig that seems to
prevail.
Removing the 'default y' for  stm32 to avoid confusion.

Fixes #8193

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-06-06 09:37:05 -04:00
Andy Ross
718597fe32 arch/arm: Fix THREAD_MONITOR entry struct
On ARM, the __thread_entry struct pointer used when
CONFIG_THREAD_MONITOR is enabled was pointing to the initial exception
stack frame.  That's not right: even though this contains all the same
info, it's not layout-compatible with the API struct.  And once the
thread starts running, the ESF gets unwound and the memory recliamed
for the stack frame of the entry function!

Stuff the __thread_entry struct into its own memory at the bottom of
the stack like the other architectures do.  Fixes #7541

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-06-05 13:25:27 -04:00
Tomasz Bursztyka
c5cb8e943c arch/arc: Set the right priority for WDT on quark_se
ARC has only 2 priorities, 0 or 1. So let's set the right priority for
WDT.

It looks like some commit has changed that, somewhere. And wrong
priorities were lurking around.

Fixes #8096

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-06-05 09:08:46 -04:00
Maureen Helm
b423ee5f2a nxp_imx: Move i.MX RT PLL selects to Kconfig.soc
PLL configuration options for i.MX RT SoCs were added in commit
3fd25c64c7, but the selects were
incorrectly added to the SoC defconfig rather than Kconfig.soc. This
resulted in the PLL options not being configured and the part not
booting properly.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-04 22:57:38 -04:00
Wayne Ren
b09b6b6ee8 arch: arc: add comments for _load_stack_check_regs
add comments for _load_stack_check_regs to avoid
wrong usage

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-04 13:31:43 -04:00
Wayne Ren
b829bc78c1 arch: arc: refactor the arc stack check support
* the original stack check codes have no consideration
  for userspace case. This will wrong cause possible stack
  check exception.
* this commit refactors the arc stack check support to
  support the usperspace.

* this commit fixes #7885. All the failed tests in #7885
  are run again to verify this commit. The test results are ok

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-06-04 13:31:43 -04:00
Ryan QIAN
5c6a3991b5 mimxrt1050: check if D-cache is enabled before enabling it.
An issue has been confirmed in CMSIS core header file in
SCB_EnableDCache when stack is in cacheable memory.

Issue report: https://github.com/ARM-software/CMSIS_5/issues/331

To workaround this issue by checking if Dcache's been enabled before
trying to enable it.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
5757b4482e mimxrt1050: fix dcdc value change process
- to check status bit to make sure DCDC output is stable

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
3fd25c64c7 boards: mimxrt1050_evk: add condition to initialize different PLL
- add conditions to initialize different PLL

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Ryan QIAN
b2522d44cb mimxrt1050: remove app specific code from soc file
- Remove clock gating code to be compatible with A1 silicon
- Remove PLL deinitialization code out of soc file

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-06-04 12:09:28 -05:00
Tomasz Bursztyka
0d56036f04 arch/x86: Rename a legacy network Kconfig option
ETHERNET option was from first network stack (a fork of uIP). This
option is now called NET_L2_ETHERNET.

Fixes #7798

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-06-04 08:24:28 -04:00
Alexander Wachter
b97dd472fb drivers: can: Move bit timing and clock to device tree
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-06-01 12:59:42 -05:00
Piotr Zięcik
997a49ade9 arm: userspace: Do not overwrite r7 during syscall.
The r7 register is used as a frame pointer on ARM Thumb. As result, it
cannot be modified by the assembly code in functions using stack frame.

This commit replaces r7 by r8, which is a general purpose register.
Also it fixes #7704.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-06-01 13:07:47 -04:00
Sathish Kuttan
9f4702b3b4 arch: soc: intel_s1000: set M/N divider ownership
Add bit definitions and set M/N divider ownership in
i2s_initialize.
Changes to comply with coding guidelines
Changes to address review comments

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Sathish Kuttan
ed33f43e48 arch: xtensa: intel_s1000: Reference clock API
Added a function to obtain the reference clock frequency value based on
SoC's bootstraps.
Added M/N divider base address in SoC header file

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-06-01 08:59:01 -04:00
Ioannis Glaropoulos
e76ef30aca arch: arm: mpu: minor comment style fixes
This commit fixes some minor function documentation issues
and comments' style in the NXP_MPU driver.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
7f643677be arch: arm: add additional sanity checks before MPU config change
This commit inserts sanity checks every time we are performing
a (re)-configuration of one or multiple MPU regions, ensuring
that we do not attempt to configure an invalid region number.

Particulary for arm_mpu_config(), called during pre-kernel
initialization phase, we add a system ASSERT if we attempt
to initialize more regions that what is supported by hardware.
We do this to ensure the misconfiguration is detected early and
the system boot is aborted.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
25c211d252 arch: arm: implement internal function to disable MPU region
This commit adds an internal function to disable an MPU region.
The function includes an assert that the requested MPU region
number is a valid one. arm_mpu.c is refactor to use this
function in all cases where an MPU region needs to be disabled.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
0967f11f6d arch: arm: enhance internal function documentation
This commit enhaces the documentation of internal functions
in arm_mpu.c by explicitly stating that the caller needs to
ensure the validity of the supplied MPU region index. The
warning is required as these functions modify the ARM MPU_RNR
register, without checking themselves the validity of the
provided region number.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Ioannis Glaropoulos
7b77a25f14 arch: arm: coding and comment style fixes
This commit fixes some minor issues with coding style
and comment syntax in arm_mpu.c

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 15:40:05 -04:00
Joakim Andersson
45b75dd7ff arch: arm: Fix zero interrupt latency priority level
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.

Update comments to reflect the priority levels reserved by the kernel.

Fixes: #8073

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2018-05-31 14:58:43 -04:00
Ioannis Glaropoulos
6399cb6b27 arch: arm: force MpuFaultHandler to inspect multiple error conditions
Upon MemManage Exception, multiple status bits of MMFSR may be
set. This commit modifies the MPU Fault Handler, so that it can
inspect and display information from all error conditions,
instead of just the first error condition that is true.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Ioannis Glaropoulos
56c9760834 arch: arm: use stored value for MMFAR
Make MPU stack guard checks use the previously stored value
of the MemManage Fault Address Register, to ensure that the
address-under-check is valid.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-31 14:05:58 -04:00
Andy Ross
1fe6c36730 esp32: Add some "logging" voodoo to SMP initialization
At least one of my WROOM boards has trouble getting the APPCPU
started, that was magically getting better when I started adding
printk's to debug.  It turns out that UART output (and NOT simply idle
cycles of delay) was the magic dust to fix things.  As this SMP
implementation is reverse engineered voodoo to begin with, this hack
should be acceptable in the medium term.

See in-file comments on smp_log() for details.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-31 14:02:03 -04:00
Gil Pitney
ec7d483b5b arch: arm: soc: cc2650: Remove dead code.
Remove the dead code that was guarded by previously removed
Kconfig symbols for the sensortag board.

With b028a51542,
this fixes #7873

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-30 22:20:37 -04:00
Wayne Ren
3c8ed211c2 arch: arc: fix the wrong setting of STACK_CHECK for user thread
For user thread, the stack check parameters will cover both
user stack part and privilege stack part. Because in arc, they
are in the same array.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-30 20:23:35 -04:00
Johann Fischer
5fae373107 dts: nxp: fix typo in usbd bindings
Fix typo in usbd bindings.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-30 11:23:39 -05:00
Erwan Gouriou
f315afd0a7 arch: stm32: Fix inclusion of SPI headers
In some STM32 series, SPI LL headers where included under
CONFIG_CLOCK_CONTROL_STM32_CUBE flag definition.
Fix this and use CONFIG_SPI_STM32 instead.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-29 07:44:00 -07:00
Adithya Baglody
c2d632d69d arch: arm/arc: Remove usage of zephyr_library_ifdef.
Phasing out the usage of this cmake macro from the arch folder.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Adithya Baglody
a9ea155425 arch: arm: add_subdirectory shouldn't depend on a hidden kconfig.
Previously the directory core/cortex/mpu/ was getting included
on a hidden kconfig. Now this has been replaced with the Kconfig
CONFIG_ARM_CORE_MPU.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Adithya Baglody
699aacad50 arch: arm: add_subdirectory shouldn't depend on a hidden kconfig.
Previously the directory core/mpu/ was getting included on a hidden
kconfig. Now this has been replaced with the Kconfig
CONFIG_ARC_CORE_MPU.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-28 13:23:13 -04:00
Carles Cufi
93a464321d arch: arm: nordic: nrf52: Enable instruction cache
Enable the instruction cache by default in order to achieve a speedup of
up to 20% in code execution.
Cache can be disabled by setting the new NRF_ENABLE_ICACHE Kconfig
option.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-28 17:59:38 +02:00
Aurelien Jarno
cbac8fcadb arch: arm: select CPU_HAS_FPU on STM32L4 family
All the STM32L4 SoCs have a Cortex-M4F CPU, and thus have a FPU. Update
stm32l4/Kconfig.series to select CPU_HAS_FPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-28 09:32:23 -05:00
Kumar Gala
71ce9b524a arch: arc: snps_emsk: Removed dead code
soc.h had defines for CONFIG_ARCV2_TIMER1_INT_{LVL,PRI}.  These defines
are both not used and no Kconfig symbols so lets remove them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-28 10:46:24 +02:00
Ulf Magnusson
cc4473831f soc: soc_family: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
d946ed7328 soc: defconfig.series: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Ulf Magnusson
3ac3216d89 soc: defconfig: Consistently quote string defaults
In preparation for introducing a warning.

Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.

Suggested by Kumar Gala.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-26 19:17:48 -04:00
Leandro Pereira
edd18c8f5a arch: x86: Better document that CR0.WP will also be set when CR0.PG is
Setting bit CR0.WP (bit 16) will inhibit supervisor threads from
writing to RO pages.  It's a necessary flag to be set, and the constant
name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was
being set.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-26 19:09:33 -04:00
Aurelien Jarno
a9fe133d07 arch: arm: fix a typos in Kconfig file
Architectue => Architecture

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-26 19:07:55 -04:00
Ioannis Glaropoulos
0825d0cd19 arch: arm: fix undefined variable bug
This commit fixes a compilation bug for an undefined variable
(mmfar), which is only conditionally defined. Instead of mmfar
we use the ARM register value directly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-26 15:50:56 -04:00
Anthony Kreft
94a22daf36 arch: arm: STM32L053X8 support
Add support for the STM32L053X8 on the NUCLEO-L053R8 board.

Signed-off-by: Anthony Kreft <anthony.kreft@gmail.com>
2018-05-25 13:06:18 -05:00
Gil Pitney
9d2f370ddb boards: cc3220sf_launchxl: Make cc3220sf XIP by default
Previously, there was no easy command-line solution for loading
a Zephyr program to (internal) flash.
So, the default development method was to load via gdb/openocd
to SRAM and debug from there, thus making the cc3220sf platform
non-XIP (CONFIG_XIP=n) by default.

With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu),
the image can now be flashed and debugged via gdb/openocd,
so the default will be changed to XIP (CONFIG_XIP=y).

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-25 11:59:00 -05:00
Jun Li
8cc002e657 soc: stm32f1: add port uart4
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.

Signed-off-by: Jun Li <jun.r.li@intel.com>
2018-05-25 11:58:20 -05:00
Ilya Tagunov
1e6d827a53 drivers: serial: stm32: add LPUART support for L0/L4 series
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Ilya Tagunov
fd26514a4d drivers: serial: stm32: rework macros and fixups
STM32Lx LPUART peripherals do not fit well into existing U(S)ART
port numbering scheme, so there will be two separate namespaces
in Kconfig: one for U(S)ARTs and one for LPUARTs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-05-25 11:54:42 -05:00
Andy Ross
3a0cb2d35d kernel: Remove legacy preemption checking
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.

As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant.  And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-25 09:40:55 -07:00
Ioannis Glaropoulos
49f0dabfcc arch: arm: refactor default _FaultDump to provide fatal error code
Refactor the _FaultDump of the default debug-level (2) to
provide the error code that indicates the fatal error reason.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d54dc42af9 arch: arm: refactor FAULT_DUMP to retrieve the fatal error reason
Refactor FAULT_DUMP macro to obtain and store the fatal error
reason. Make non-default version of FAULT_DUMP (i.e. with
CONFIG_FAULT_DUMP level 1) to retrieve the default reason
for fatal errors (_NANO_ERR_HW_EXCEPTION).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Ioannis Glaropoulos
d2c8a20560 arch: arm: document non-returning fatal handlers
Document that execution does not return from
_NanoFatalErrorHandler and _SysFatalErrorHandler.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-25 09:46:24 -05:00
Wayne Ren
876a9af9d5 arch: arc: fix the bug in register clear for USER_SPACE
* blink, fp should not be always cleared
* clean up code format
* use a better way to save and restore ER_SEC_STAT

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-25 15:56:15 +02:00
Wayne Ren
77eb883ab0 arch: arc: fix the bug in exception return for secure mode
* current codes use a faked interrupt return to do a thread switch
  in exception return.
* so the different between exception return and interrupt return
  should be carefully considered.
* when secure is enabled, the sec_stat should also be pushed in
  exception entry.
* when secure is enabled, SEC_STAT.IRM must be configured corrrectly
  for interrupt return.
* For the case of faked interrupt return in exception return, the
  correct value of SEC_STAT.IRM comes from ER_SEC_STAT.ERM.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-25 15:56:15 +02:00
Andrew Boie
6f6acb4667 arm_mpu: reduce boot MPU regions for various soc
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Fixes #6896

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 19:19:07 -04:00
Andrew Boie
d9a227c19c arm: st_stm32: reduce boot MPU regions
The PPB and Peripheral regions have been removed,
the Shareable options are only important with unlocked
dual cores. Just use the background mapping.

The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.

Related to #6896 and #7877

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-24 15:31:00 -07:00
Leandro Pereira
ecadd465a2 arch: x86: Allow disabling speculative store bypass
In order to mitigate against Spectre V4, add an option that will, at
boot time, verify if the CPU supports the SPEC_CTRL MSR; if so, it'll
attempt to disable the feature.

More information can be found in chapter 4 (Speculative Store Bypass
Mitigation) of the "Speculative Execution Side Channel Mitigations"
document, version 2, published by Intel: https://goo.gl/nocTcj

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-24 13:07:12 -04:00
Leandro Pereira
fb0fba91a5 arch: x86: Rename CPU_NO_SPECTRE to CPU_NO_SPECTRE_V2
There's a new known variant, so make it clear what this one is for.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-24 13:07:12 -04:00
Ioannis Glaropoulos
46a3e8bdf0 arch: arm: fix fault status register bitfield masks
This commit fixes the bitfield masks for the Cortex-M
fault status registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-24 11:31:54 -05:00
Tomasz Bursztyka
2bfcb8496d arch/arc: UART QMSI's baudrate is not present in Kconfig anymore
It's generated through dts.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-24 11:58:17 -04:00
Aurelien Jarno
509e6964cc arch: stm32l432: add support for USB controller
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Aurelien Jarno
dc01b99068 arch: stm32l4: only enable USB OTG on SoCs supporting it
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:

- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller

Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-05-24 09:42:30 -05:00
Kumar Gala
8321b6b64f arch: arm: nxp: Fixup HAS_MCUX_RTC
When the RTC support get added we had a select on HAS_RTC, however this
Kconfig symbol didn't exist.  Clean this up to match the pattern of
HAS_MCUX_RTC.  The driver now depends on that and the SoC selects it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-24 08:21:24 -05:00
Ulf Magnusson
5b20350a72 gdb_server: Remove leftover testing and x86 parts
gdb_server was removed in commit 0f669132a0 ("kernel: remove
gdb_server"), but still has a testcase that sets CONFIG_GDB_SERVER=y,
and some code in arch/x86/debug.

Remove the leftover parts. This also gets gets rid of undefined
references to the CONFIG_GDB_SERVER symbol.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-24 08:10:21 -04:00
Erwan Gouriou
9559277094 arch: stm32: Remove unsupported MPU options
Some code was developped around MPU support in ealy stage
of feature introduction. This code was gated under MPU_ENABLE
flag which does not exist and hence code has never been
enabled nor tested.
Since there has been futher MPU development since then, it seems
safer to simply remove that code and associated Kconfig symbols
to avoid that someone starts using it while it was not part of
MPU development track.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-24 08:04:00 -04:00
Kumar Gala
33628f1c47 arch: arc: userspace: Fix typo in comment
CONFIG_INIT_STACK should be CONFIG_INIT_STACKS

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
Kumar Gala
6ef2f76b2f arch: arm: thread.c: Fix typo in comment
Changed CONFIG_BUIILTIN_STACK_GUARD to CONFIG_BUILTIN_STACK_GUARD.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
Kumar Gala
7faac6a761 arch: arm: atmel_sam: Add quotes to strings in Kconfig
While not technically required, its cleaner to ensure that strings
defaults are quoted.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-23 17:57:06 -04:00
David B. Kinder
44383a394b doc: fix misspellings in Kconfig files
Found some misspellings missed during normal reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-23 16:57:20 -04:00
Leandro Pereira
d4221f9a71 arch: x86: Rename MSR-handling functions to conform to convention
Rename _MsrRead() and _MsrWrite() to _x86_msr_read() and
_x86_msr_write() respectively.

Given that these functions are essentially implemented in assembly.
make them static inline.  They can be inlined by the compiler quite
well, most of the time incurring in space savings due to better
handling of the cobbled registers.

Also simplifies the inline assembly, using constraints instead of
moving registers ourselves.  Should shave off a few bytes from code
using these functions.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-05-23 14:38:22 -04:00
Carles Cufi
5b37cd7346 arch: arm: swap: Remove old context switch code
Remove unused context switch code from the helper assembly file that
manages the SuperVisor Call invocations (SVCs). This is no longer in use
in the code, since all calls to __swap() now go through PendSV directly.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-05-23 09:34:12 -07:00
Andrew Boie
99f36de0a1 arm: userspace: fix initial user sp location
The initial user stack pointer gets rounded to STACK_ALIGN_SIZE,
which can be much finer granularity than MPU regions. With
certain stack size values passed to k_thread_create(), the stack
pointer can be set past the defined region for the user thread's
stack, causing an immediate MPU fault.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Andrew Boie
9731a0cce9 arm: syscalls: fix some register issues
Upon return from a syscall handlers, the r1, r2, and r3 registers
could contain random kernel data that should not be leaked to user
mode. Zero these out before returning from _arm_do_syscall().
Fixes #7753.

The invocation macros need a clobber if r1, r2, or r3 are not used
to carry syscall arguments. This is a partial fix for #7754 but
there appear to be other issues.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-22 15:59:07 -07:00
Sebastian Bøe
cde6bef778 kconfig: Drop support for CONFIG_TOOLCHAIN_VARIANT
The Kconfig option TOOLCHAIN_VARIANT (not to be confused with
ZEPHYR_TOOLCHAIN_VARIANT) is a legacy configuration option that has
very few use-cases and can easily be dropped.

It's functionality is easily covered by CONFIG_X86_IAMCU and
ZEPHYR_TOOLCHAIN_VARIANT.

This commit removes all references of it from Zephyr.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-05-22 11:15:36 -04:00
Savinay Dharmappa
2ebb6a1fee dts: intel_s1000: use dts to set i2c0 priority.
patch removes Kconfig used i2c0 priority, instead use the
macro generated from dts.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 09:30:14 -04:00
Savinay Dharmappa
6701d44967 dts: xtensa: Fix build error due to dts changes for ns16550 driver.
patch add clock frequency and interrupt property to uart
node in intel_s1000.dtsi. Include soc.h after types.h to
prevent build error.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-22 08:51:59 -04:00
Kumar Gala
edf7c4fd08 arch: arm: kw41z: Set DTS fixup for CONFIG_RTC_0_NAME
Recent change to RTC core now gets CONFIG_RTC_0_NAME from device tree.
So we need a fixup for KW41Z for that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-21 14:06:57 -05:00
Maureen Helm
b5db62ca94 frdm_kl25z: Remove incorrect references to spi
The kl25z does not have the same spi hardware as the k64f and therefore
cannot use the same spi driver. Remove all references to spi for the
kl25z soc and frdm_kl25z board until we have a valid spi driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-21 13:26:10 -05:00
Alexander Wachter
e73637af24 boards: stm: Add CAN support for stm32f072b micro controller
This commit adds the can device to the stm32f072b device tree and pinmux

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2018-05-19 20:19:30 +02:00
Tomasz Bursztyka
60d509f3d7 arch: Use dts to set i2c priorities for quark_se/quark_d2000
Fix the qmsi i2c driver and the relevant SoCs accordingly.
Also applying relevant changes on quark_se_c1000_ss as it can use i2c
qmsi driver as well along with qmsi ss i2c driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
ed26b95746 drivers/gpio: Removing dts generated options in QMSI Kconfig
Now that all arch using QMSI gpio driver are generating the right
settings through DTS, these options can be removed from Kconfig.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
bd9706cd9b arch/arc: Use dts to set gpio priorities for quark_se_c1000_ss
Fix the qmsi ss gpio driver accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
61ef30d10e drivers/uart: Use dts to set uart options for ns16550 driver
Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
17c6456678 drivers/uart: Use dts to set uart priorities for QMSI driver
Fix the qmsi uart driver and relevant SoCs accordingly.
Also: using config for irq everwhere relevantly and not an hardcoded
value in the driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
250c4a87ed arch: Use dts to set rtc priorities for Intel quark, x86 and arc
Get the name generated through dts as well.
Fix the rtc driver and relevant SoCs accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Tomasz Bursztyka
53f91976b1 arch/x86: Use dts to set gpio options for quark_se and quark_d2000
Get the name and irq flags generated through dts as well.
Fix Kconfig for the gpio driver accordingly.

Irq priority is not set by dts for D2000 as it's irq controller does
not support it.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-05-18 20:18:50 +03:00
Ramakrishna Pallala
eb0aaca64d lib: posix: Add Posix Style File System API support
Add IEEE 1003.1 Posix Style file system API support.
These API's will internally use corresponding Zephyr
File System API's.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-18 13:32:36 +03:00
Savinay Dharmappa
2948924655 dts: nios2-qemu: add device tree support
Add device tree support for nios2-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-17 14:09:15 -07:00
Savinay Dharmappa
8f908f38e0 dts: nios2f: Add device tree support
Add device tree support for nios2f soc

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-17 14:09:15 -07:00
Ulf Magnusson
4dc9e5b2de kconfig: Get rid of 'option env' bounce symbols
This commit gets rid of the 'option env="ENV_VAR"' bounce symbols.
"$FOO" now expands directly to the value of the environment variable
FOO, instead of to the value of the Kconfig symbol FOO.

This change is likely to soon appear in the C tools as well. Those
'option env' symbols always seemed kinda pointless, and have broken
dependency handling due to forcing symbol evaluation during parsing,
before all the symbols have even been seen.

Compatibility with the C tools could be retained by naming all
'option env' symbols the same as the environment variable they
reference.

This commit also updated the Zephyr documentation to explain the new
behavior. It's relevant for $ZEPHYR_BASE and out-of-tree Kconfig
extensions.

Commit message from Kconfiglib (cbf32e29a130d)
==============================================

Make "$FOO" directly reference the environment variable $FOO in e.g.
'source' statements, instead of the symbol FOO. Use os.path.expandvars()
to expand strings (which preserves "$FOO" as-is if no environment
variable FOO exists).

This gets rid of the 'option env' "bounce" symbols, which are mostly
just spam and are buggy in the C tools (dependencies aren't always
respected, due to parsing and evaluation getting mixed up). The same
change will probably appear soon in the C tools as well.

Keep accepting 'option env' to preserve some backwards compatibility,
but ignore it when expanding strings. For compatibility with the C
tools, bounce symbols will need to be named the same as the environment
variables they reference (which is the case for the Linux kernel).

This is a compatibility break, so the major version will be bumped to 6
at the next release.

The main motivation for adding this now is to allow recording properties
on each MenuNode in a clean way. 'option env' symbols interact badly
with delayed dependency propagation.

Side note: I have a feeling that recording environment variable values
might be redundant to trigger rebuilds if sync_deps() is run at each
compile. It should detect all changes to symbol values due to
environment variables changing value.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-05-17 23:55:07 +03:00
Stanislav Poboril
5477ee4531 mcux: Add MCUX IPM driver for lpc and kinetis socs
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-17 15:07:48 -05:00
Kumar Gala
7514a92cbe arch: arm: nxp_lpc: Added support for init of slave core
Added ability to load and bootup the slave (Cortex-M0+) core on the
LPC54xxx SoC.  Currently we expect a binary image to be specified via
Kconfig for the code that will run on the slave core.  We also specify
via Kconfig the boot/load address for the slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Kumar Gala
b7312d1bbc arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc
Add soc configuration support and dts files for nxp_lpc54xxx_m0.

Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-17 15:07:48 -05:00
Maureen Helm
02253c231d nxp_kinetis: Fix rtc base address in kw41z dts.fixup
Since commit 081c9c3bec,
extract_dts_includes no longer appends _0 to peripheral base addresses.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:03:50 -05:00
Maureen Helm
e9ca0a7dae nxp_kinetis: Enable mcux watchdog driver on k64, kw2xd socs
Enables the mcux kinetis watchdog driver on k64 and kw2xd socs. Adds
relevant soc-level dts fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-17 15:00:55 -05:00
Andy Gross
7b92d3fb1c rtc: nxp: Add RTC driver for NXP Kinetis
This patch adds the configuration, driver, and HAL changes required
to implement a MCUX based RTC driver for the NXP Kinetis KW41Z.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Andy Gross
1fe586f678 dts: nxp: kw41z: Fixup NXP Kinetis RTCs on KW41Z
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks.  DTS fixups were added as well to match up the driver
usage to the DTS output.

Signed-off-by: Andy Gross <agross@kernel.org>
2018-05-17 13:45:08 -05:00
Florian Vaussard
ae71554be3 dts: stm32l4: add node and fixup for i2c4
Add the device tree node for I2C4 and the corresponding fixup.

Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
2018-05-17 13:08:36 -05:00
Ioannis Glaropoulos
b8ec6da38f arch: arm: convenience wrappers for C variable permissions checks
Declare and implement convenience wrappers to evaluate read and
write permissions of C variables using the cmse address range
intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
8e0c830dce arch: arm: implement cmse address range check
This commit contributes the implementation of the
CMSE address range permission checks based on the
ARMv8-M address range check intrinsics.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
600d731c95 arch: arm: select CPU_CORTEX_M_HAS_CMSE in ARMv8-m
Select CPU_CORTEX_M_HAS_CMSE in ARMV8_M arhitectures.
Option ARMV8_M_BASELINE is introduced for this purpose,
so that CMSE API is enabled for both Cortex-M23 and
Cortex-M33 MCUs.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Ioannis Glaropoulos
c842f32ddd arch: arm: Define & implement API for test target (Non-Secure)
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Test Target (TT) instruction
support.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-17 07:52:34 -07:00
Johann Fischer
d6f14291ee arch: nxp_kinetis: enable USB device driver
Enable USB device driver for K64F and KW2xD512 SoC

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Johann Fischer
5dc6f99cfd drivers: usb: add usb device driver for Kinetis USBFSOTG Controller
Add usb device driver for Kinetis USBFSOTG Controller.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Johann Fischer
d8cd119562 dts: arm: nxp: use DT to configure USBD on Kinetis SoC
Add DT and fixup files to configure USB device driver on
Kinetis SoC K64F and KW24D512.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2018-05-17 07:00:49 -05:00
Andrew Boie
97bf001f11 userspace: get dynamic objs from thread rsrc pools
Dynamic kernel objects no longer is hard-coded to use the kernel
heap. Instead, objects will now be drawn from the calling thread's
resource pool.

Since we now have a reference counting mechanism, if an object
loses all its references and it was dynamically allocated, it will
be automatically freed.

A parallel dlist is added for efficient iteration over the set of
all dynamic objects, allowing deletion during iteration.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-16 17:32:59 -07:00
Andrew Boie
0daf69bb57 xtensa: fix CONFIG_INIT_STACKS for IRQ stack
The interrupt stack area wasn't being set to a repeating
0xAA pattern at boot as it should be. This is now done in
kernel_arch_init(), which runs before interrupts are
enabled for the first time.

Fixes #7327

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-16 12:06:31 -07:00
Andrzej Puzdrowski
11c68a10f4 boards/arm/nrf52xx_boards: makes GPIO_AS_PINRESET common
Kconfig keyword GPIO_AS_PINRESET is common for whole nrf52 series.
This patch move it to the series Kconfig.soc file.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-05-16 11:10:52 -05:00
Andrzej Puzdrowski
a5c12b6c05 arch/arm/soc/nordic_nrf/nrf52: NFCT pins configuration
It is possible to use NFCT pins as regular GPIOs.
This patch introduce option for enabling this feature.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-05-16 11:10:52 -05:00
Anas Nashif
48cc46206f boards: frdm_kw41z: enable xoroshiro on board level only
Enabling the driver on board level is sufficient. We need to find a
better way for selecting random drivers on SoC level, this is currently
not possible due to how Kconfig works.

Fixes #7097

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-16 10:36:59 -05:00
Savinay Dharmappa
48e2dba28f dts: xtensa: fix build error.
patch fix the build error due to wrong assignment of macro in
the dts.fixup file

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-16 10:25:19 -05:00
Stanislav Poboril
6871057e31 ext: Modified lpc54114 startup code from mcux for use with Zephyr.
The instructions performed by standard Zephyr startup files are removed
from the file startup_LPC54114_cm4.S. Introduced the section
_PlatformInit which will be called when platform specific initialization
is needed.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-15 15:49:15 -05:00
Stanislav Poboril
fd4759b5d7 arch: nxp: lpc54xxx: Rename SoC bits from LPC54114 to LPC54114_M4
Rename various SoC related defines and files from just being LPC54114
to LPC54114_M4.  This is in prep for supporting a build for the second
core on the LPC54114 (the Cortex-M0+).

* Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4
* Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4
* Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi
* Moved some pinmux related defines into SoC code.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 15:49:15 -05:00
Stanislav Poboril
0b7e22bdb6 arch: arm: Add platform init hook at __start
Add the ability to call platform specific code as the first thing we do.
This is needed because on some platforms we might have to figure out how
to deal with starting up secondary cores and need to do that as the
first thing we do.

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-05-15 15:49:15 -05:00
Adithya Baglody
5ab3960c75 arch: Cmake: Add __ZEPHYR_SUPERVISOR__ macro for arch files.
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the arch files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.

In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-15 17:48:18 +03:00
Ioannis Glaropoulos
70b45c63e5 arch: arm: distinguish integrity signatures with/without FP
Distinguish between the integrity signatures depending on whether the
ARM MCU implements the Floating-Point Extension or not.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
361f4ac94b arch: arm: improve fault dump for secure firmware
This commit partially reworks the fault dump implementation
of faults in non-secure state that target Secure state. In
particular, the return address to secure state is logged along
with the non-secure address which caused the non-secure fault
(that targets the Secure state).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
0a25ad1595 arch: arm: fix bug in AIRCR config on init
Fix bug when setting SCB_AIRCR during initialization; add
Vector Key to permit write to AIRCR fields.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Ioannis Glaropoulos
9bc1dc7296 arch: arm: Secure fault handling for Cortex-M23
This commit contributes the Secure fault handling for ARMv8-m
implementations, that do not support the Main Extension, such
as the (Baseline) Cortex-M23 processor.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-15 08:57:16 -05:00
Wayne Ren
c13b12eb49 arch: arc: explictly list all def config
it seems regular expresssion is not supported in "source xxx" after
latest changes in build system.

So explictly list all def config

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
5eb5bb7df8 arch: arc: add the missing SPI_DW_SPI_CLOCK in dts.fixup
* the SPI share the same clk source with uart

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
47d3a90dca arch: arc: reuse GCC_M_CPU in cmake file and remove unused comments
* reuse GCC_M_CPU in cmake file
* remove unused comments in linker.ld

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
532e4d22ee dts: optimize and bug fixes the dts of em_starterkit
* add gpio, i2c, spi definitions
* optimize and bug fix the dts.fixup
* optimize and bug fix the em_starterkit related definitions
  in dts folder

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Wayne Ren
6307b8b97d arch: arc: refactor the soc part of em_starterkit
The original em7d, em9d and em11d are different configurations of
em_starterkit. They have the same peripherals, e.g. uart, spi, gpio
, ddr. The differences of them are in arc core configurations, interrupt
number assignment.

So em7d, em9d and em11d can be viewed in the same SoC family or SoC
series.

Referring other arch's implementation, this commit merges em7d, em9d
and em11d into the same SoC, named snps_emsk. This will eliminate
unnecessary duplication and make it easier for future maintainment.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-15 09:48:11 +02:00
Savinay Dharmappa
e524f0b846 dts: x86: derive RAM and ROM size from dts instead of Kconfig
patch removes Kconfig defines for RAM and ROM size in x86. Instead
these values are derived from dts.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-14 17:19:23 -04:00
Karol Lasończyk
83e4947cf1 dts: nrf: Expand nRF DTS to support watchdog
Commit introduces support for watchdog configuration for Nordic
Semiconductor nRF SoCs in device tree.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
2018-05-14 10:28:23 -05:00
Yannis Damigos
87d624419d drivers/stm32f0x_ll_clock: Enable SYSCFG in clock_control
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and enable PIN pair PA11/12, used in USB device,
mapped instead of PA9/10.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:45:40 -05:00
Yannis Damigos
f6a9697923 drivers/stm32l0x_ll_clock: Enable SYSCFG in clock_control
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and internal voltage reference for 48 MHz HSI
used in USB device.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:33:29 -05:00
Yannis Damigos
c0b472132c dts/arm/st: Add USB support for stm32l072/73
Add USB support for stm32l072 and stm32l073 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-14 09:33:29 -05:00
Yannis Damigos
329c00dc6b arch/soc/st_stm32: Move STM32Cube HAL core funtions
STM32Cube HAL core initialization functions HAL_GetTick()
and HAL_Delay() are implemented in all STM32 series. This
patch moves these functions in file stm32cube_hal.c under
"common" folder to reduce code duplication.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-13 10:52:12 -05:00
Andrew Boie
42a2c96422 newlib: fix heap user mode access for MPU devices
MPU devices that enforce power-of-two alignment now
specify the size of the buffer used for the newlib heap.
This buffer will be properly aligned and a pointer
exposed in a kernel header, such that it can be added
to a user thread's memory domain configuration if
necessary.

MPU devices that don't have these restrictions allocate
the heap as normal.

In all cases, if an MPU/MMU region needs to be programmed,
the z_newlib_get_heap_bounds() API will return the necessary
information.

Given how precious MPU regions are, no automatic programming
of the MPU is done; applications will need to do this as
needed in their memory domain configurations.

On x86, the x86 MMU-specific code has been moved to arch/x86
using the new z_newlib_get_heap_bounds() API.

Fixes: #6814

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-10 15:09:02 -07:00
Maureen Helm
0d1beb2f9e boards: dts: Add mcr20a bindings and fix networking samples
Adds dts bindings for the mcr20a wireless transceiver. The frdm_k64f
board supports the mcr20a via an Arduino shield, therefore the dts node
is added to the board dts. The kw2xd is a SiP and thus the mcr20a dts
node is added to the soc dts.

The networking samples using prj_frdm_k64f_mcr20a.conf have been broken
since the refactoring of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
a88e31d2ca nxp_kinetis: Remove unused dspi irq defines from soc.h
Now that we get dspi irq numbers from dts, we can remove the defines
from soc.h.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
c7dd4f55f0 nxp_kinetis: Enable mcux dspi driver on kw40/41z socs
The kw40z and kw41z socs have the same dspi peripheral as the k64 and
kw2xd, so we can reuse the existing mcux dspi shim driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Maureen Helm
cae9074492 spi: Refactor mcux dspi driver to use dts
Get the driver name, base address, irq number, and irq priority from
dts.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-10 15:43:42 -05:00
Kumar Gala
071212bec9 arch: arm: atmel_sam: Fixup build issue on sam_e70
With recent dts script change we dropped _0 from define names if there
is only a single one.  So for the MPU we need to use
CONFIG_SRAM_BASE_ADDRESS instead of CONFIG_SRAM_BASE_ADDRESS_0.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-10 12:48:14 -05:00
Kumar Gala
b493f484df arch: arm: soc: Cleanup Kconfig inclusion per SoC
When we included SoC specific Kconfig files we do something like:

gsource "arch/arm/soc/arm/*/Kconfig.soc"

However, we should do that inside an if block for that SoC family so as
to limit SoC family specific options to only being visible when that SoC
family is selected.  So we simply move the gsource and related items
inside the if SOC_FAMILY_<SOC> block.

Fixes: #7452

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-10 11:16:52 -05:00
Adithya Baglody
c136a107aa soc: sam_e70: Mpu regions should include SRAM regions.
In order to disable the execution of code from the RAM region
we need to declare it in arm_mpu_regions.c file.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-05-10 08:40:52 -07:00
Erwan Gouriou
e81d9b98fe arch: nxp dts bindings: Set IP clock name to matching clock controller
In dts.fixup files for used for NXP SoCs, IP clock name was
bound to SIM clock label. This is correct but would require
manual change if IP clock controller was changed in device tree.
Use reference to IP generated define "_CLOCK_CONTROLLER" to get
this value.

Besides, having all IP related values starting with the same prefix
will be easier for possible macro preprocessing (if required one day).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Erwan Gouriou
93d3a42776 scripts: extract_includes_dts: Remove usage of cell_string yaml attribute
'cell_string' yaml attribute has been introduced in order to
help enforcement of specific string during defines generation.
This adds complexity in understanding script behavior as a black
box and create additional dependency which is not strictly required.

For node specific generation functions (pinctrl and interrupts),
this could be replaced directly by an hardcoded version
(as everyone used the same 'cell_string' anyway).
For extract_cells functions, string could be replaced by extracted
property name. As a consequence, we're now able to generate defines
for properties refering to these controllers via phandle.
For instance, in following node
 	spbtle-rf@0 {
 		compatible = "st,spbtle-rf";
 		reg = <0>;
		reset-gpios = <&gpioa 8 0>;
 	};
We'll be able to generate:
 #define ST_STM32_SPI_...LE_RF_0_RESET_GPIOS_CONTROLLER	"GPIOA"
 #define ST_STM32_SPI_...PBTLE_RF_0_RESET_GPIOS_FLAGS_0		0
 #define ST_STM32_SPI_..._SPBTLE_RF_0_RESET_GPIOS_PIN_0		8

Only impact for this whole change is for NXP clocks which were the
only ones using 'cell_string' attribute with a value different than
the default one.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Erwan Gouriou
081c9c3bec scripts: extract_dts_includes: Generate'_0' defines only when needed
Indexed defines were systematically generated even when there
was only one element to generate.
So we ended up generated a lot of _0 defines.
Then we needed to generate aliases to these _0 indexed defines,
in order to get useful defines.
For instance:
 #define GPIO_LEDS_0_GPIO_FLAGS_0	4
 #define GPIO_LEDS_0_GPIO_PIN_0		5
 #define GPIO_LEDS_0_GPIO_FLAGS		GPIO_LEDS_0_GPIO_FLAGS_0
 #define GPIO_LEDS_0_GPIO_PIN		GPIO_LEDS_0_GPIO_PIN_0

This commit allows to generate _0 indexed define only if a
property has more than one elements to define.
Aliases generation to _0 indexed defines are also removed.

Note: IRQ are left untouched since this is frequent to handle
multiple IRQs in a driver

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-10 10:38:23 -05:00
Yannis Damigos
3bbe87e171 dts/arm/st: Add usbotg_fs node to stm32l4 DT
Add otgfs (USB) node to stm32l4.dtsi.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Pushpal Sidhu
e2b27d820d drivers: usb_dc_stm32: enable VDDUSB if needed
This is required on boards that isolate VDDUSB from the system.

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-05-10 07:47:13 -05:00
Pushpal Sidhu
816e3d8767 arch: stm32l4: add HAL_Delay for hal library hooks
Hook required for hal library to delay (in ms)

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
47fe4ee78b dts/arm/st: Add USB support for stm32f070/72
Add USB support for stm32f072 and stm32f070 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
80d69ea47f boards: stm32f3_disco: Add USB support
Add USB support to STM32F3DISCOVERY board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
38d2567e08 boards: olimexino_stm32: Add USB support
Add USB support to OLIMEXINO-STM32 board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-10 07:47:13 -05:00
Yannis Damigos
921bfeb05a drivers: usb_dc_stm32: Add support for all STM32 families
Add support for all STM32 families

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-05-10 07:47:13 -05:00
Ioannis Glaropoulos
47564a0971 arch: arm: feature consistency checks for Cortex M regs
This commit implements consistency checks for the core registers
in ARMv6-M, ARMv7-M, and ARMv8-M architectures, ensuring that
the user cannot accidentally select registers that are not
implemented by the selected Cortex-M processor.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 18:43:50 -05:00
Ioannis Glaropoulos
197e277300 arch: arm: improve description of ARMV7_M_ARMV8_M_MAINLINE option
The commit improves the help text of the ARMV7_M_ARMV8_M_MAINLINE
K-config option.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 18:43:50 -05:00
Ioannis Glaropoulos
dd26f285e5 arch: arm: add synchronization point after Stack Pointer switch
This commit adds a Context Synchronization Point immediately
after the reset handler switches to use the Process Stack
Pointer, during initialization.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-09 12:18:06 -05:00
Maureen Helm
55979aa3a5 arm: Add more flash and ram size options to i.MX RT MPU config
Adds 8 MB and 64 MB flash size options, which correspond to the two
external flashes (qspi flash and hyperflash) on the mimxrt1050_evk
board. Adds a 32 MB SRAM size option, which corresponds to the external
sdram on the board.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-08 17:39:28 -05:00
Gil Pitney
7f271b8689 cc3220sf: soc: Update PRCM call to allow use of ROM API
The API in the current SDK version is rom-patched, and uses
prcm.c code in the driverlib directory.

But, the PRCMMCU3200Init() API call should be prefixed by MAP_
to allow the option to use the ROM API in a future TI SDK version.

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-05-08 17:35:25 -05:00
Andrew Boie
3d69198843 arm_mpu: fix off-by-one in mpu_buffer_validate
The loop that checks the MPU region permissions incorrectly
iterates from (num_region + 1) to 1. This should be
(num_region - 1) to 0. This results in the wrong regions
being checked and possible overflow for any implementation
that uses the max region value of 0xFF.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-05-08 08:56:38 -07:00
Diego Sueiro
e8e76ae433 arch: Add imx7d_m4 gpio definitions
Adds all necessary gpio definitions and configurations for imx7d_m4 soc.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-05-08 06:56:56 -05:00
Ulf Magnusson
547ed9b563 kconfig: Make 'source' non-globbing and use 'gsource'
Until now, Zephyr has used a patched Kconfiglib that turns 'source' into
a globbing source (by replacing 'source' with 'gsource' at the token
level). There's two problems with this:

  - The patch needs to be maintained separately

  - Misspelled filenames are silently ignored, as they look like glob
    patterns that don't match anything

Fix it as follows:

  1. Replace all 'source' statements that use wildcards with 'gsource'

  2. Remove the custom Kconfiglib patch so that 'source' no longer globs

The sed pattern '/source.*[*?]/s/source/gsource/' was run over all
Kconfig* files to do the replacement.

source's that use environment variables that might contain glob patterns
were manually changed to gsource.

Building the docs in doc/ is a good test, as doc/Makefile deliberately
sets the environment variables to glob up as many Kconfig files as
possible.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-05-08 11:14:12 +02:00
Ioannis Glaropoulos
8d1b013f3c arch: arm: thread built-in stack guard implementation
This commit activates the built-in stack guard on the main_thread
before jumping to it upon system initialization. Stack guard is
activated if BUILTIN_STACK_GUARD is enabled by the user. The
commit also activates built-in thread stack guards at every
context switch, if BUILTIN_STACK_GUARD enabled by the user.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ioannis Glaropoulos
91dc3bd0f9 arch: arm: ignore stack pointer limit checks during HF and NMI
Ignore stack pointer limit checking during a HardFault or NMI
exception, to allow for the Fault handling function to execute
properly.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ioannis Glaropoulos
4a41f42e73 arch: arm: set interrupt stack protection with MSPLIM
This commit implements the build-in interrupt stack protection
via the native MSPLIM register in ARMv8-M MCUs that support the
Main Extension. Main stack pointer overflows will cause Stack
Overflow UsageFaults. In addition, the commit introduces a new
config option, BUILTIN_STACK_GUARD, allowing the user to enable
and use the built-in stack protection in ARMv8-M firmware.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-05-04 17:26:57 -04:00
Ramakrishna Pallala
15447fa1d8 drivers: dma: Add dma driver for Nios-II MSGDMA core
Add dma driver for Nios-II Modular Scatter-Gather DMA soft IP.

This driver relies upon the Altera HAL msgdma driver for all
the dma core register programming and interrupt handling.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-03 10:38:09 -04:00
Ramakrishna Pallala
4073db79d7 arch: nios2: Add _nios2_dcache_flush_no_writeback() routine
Add _nios2_dcache_flush_no_writeback() routine to invalidate
cache contents of address provided.

This routine is ported from Altera Nios-II SDK v17.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-05-03 10:38:09 -04:00
Alberto Escolar Piedras
e3efbd54c6 POSIX arch: Fix linker -T warning
Modify the linker script with the command INSERT.
It instructs the linker to augment the default linker script
SECTIONS with the ones provided with the one provided in
this script.
It also modified the meaning of the -T switch, so it no longer
replaces the default linker script

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-05-02 10:19:09 -04:00
Wayne Ren
6c65ac2bb4 arch: arc: fix the typo of label which caused issue #7249
* fix the issue #7249 which is caused by a typo of label

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-05-02 09:31:00 -04:00
Yannis Damigos
2fd277fccf arch/arm/soc/st_stm32/stm32f1: Add I2C1 to dts.fixup
This patch adds the missing defines for I2C1.

Fixes #7248.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-05-02 01:11:36 -04:00
Savinay Dharmappa
7be3236ca4 dts: interrupt_controller: Add dts support for DesignWare controller
Add dts support for multilevel DW interrupt controller

Change-Id: Ia16d6870bd3a46fca933c906aedc6ba78ed5131a
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
9ee4929d56 dts: i2c: Add dts support for i2c
Change-Id: I9104f5230a4efbf1b6979e146e7ea73a76891947
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
97f721d928 dts: xtensa: Add device tree support for xtensa
Change-Id: I309bc50c6b575caa84fbc7ab98cc9890771b4274
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-05-01 16:46:41 -04:00
Savinay Dharmappa
5060f4bd14 driver: usb: enable usb2.0 on intel_s1000
Change-Id: I59091c465e84f1d6ba64433b7320182d83ff9589
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
5b6f02442b drivers: i2s: introduce CAVS I2S
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.

Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
cea1c75e2b boards: intel_s1000_crb: enable DMA
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.

Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
bd0d5133e4 drivers: dma: introduce Intel CAVS DMA
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.

This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.

Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
08172cdf83 xtensa: provide XCC compiler support for Xtensa
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.

ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
		RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/

Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
dadf9e7a81 xtensa: intel_s1000: implement interrupt mechanism
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.

Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
9cc381c07a intel_s1000: i2c: enable I2C for intel_s1000
intel_s1000 makes use of DesignWare IP for I2C.

Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
63d50e158e intel_s1000: gpio: enable GPIO handling
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.

Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
9ed55af2f8 arch: xtensa: set __start as entry point for Xtensa.
__start is deemed the entry point for all architectures in Zephyr.
Accordingly, Xtensa code had to be modified a bit to fall in line
with this convention.

Change-Id: If3ed344721c9f2735378b866662a68d8d5795324
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
47ff96593f intel_s1000: uart: configure UART for intel_s1000
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.

Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
c9ace83c89 xtensa: reset-vector.S hack for booting intel_s1000 [REVERTME]
Setting CACHEATTR from _memmap_cacheattr_reset is making
the intel_s1000 SoC get into some unknown state. Removing
it for intel_s1000_crb for now.

Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
02736e5935 intel_s1000: add intel_s1000_crb board
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).

Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
1fcd39b624 intel_s1000: define memctl_default.S and memerror-vector.S files
Define memctl_default.S and memerror-vector.S files. A reference
could be found in the Xtensa toolchain directories. These are
required for using cavs21_LX6HiFi3_RF3_WB16 Xtensa CPU mainly in
simulator. On boards which have ROM, these would have been already
defined in the ROM. Hence, the contents of these files will be
developed at a later time if required.

Change-Id: Idf52397bb6880c136525e69f47e09defcba7f036
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Rajavardhan Gundi
f14d1be67f intel_s1000: Add intel_s1000 SoC
intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which
belongs to Xtensa family. This is being used in intel_s1000_crb.

Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-05-01 16:46:41 -04:00
Andrew Boie
de7f40acfb kconfig: fix menuconfig
"depends on" cannot use expressions as arguments, this statement
didn't actually do anything for kconfiglib.py and caused an
error with menuconfig.

There's currently no way to depend on a system heap being
present, however forthcoming patches move this feature away
from using the system heap anyway.

For now, if the user enables dynamic objects without defining
a system heap, they will get a build error.

Fixes #7266.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-30 09:22:48 -07:00
Yannis Damigos
d9cdf7bf30 arch/arm/soc/st_stm32: Fix typos in soc.h
Fix typos in soc.h for stm32f1 and stm32l4 families.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-04-28 20:46:08 +05:30
Manivannan Sadhasivam
42a7c5732f arm: soc: Elaborate Kconfig strings for MPU selection
Some of the SoCs specify "Enable MPU" in Kconfig for enabling MPU
support. This will create ambiguity while selecting options via
menuconfig. Hence, append SoC family name to the selection strings
to looks more elaborative.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Manivannan Sadhasivam
c36e5ac129 arm: Fix title for SoC configuration in Kconfig
The title for selecting the configuration options for SoC's should be
"SoC Configuration" not "Board Configuration".

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-04-28 20:38:12 +05:30
Ioannis Glaropoulos
c7d808f965 arch: arm: improve help text for PROGRAMMABLE_FAULT_PRIOS option
Improve the help text of ARM k-config option
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-27 17:41:24 +05:30
Kumar Gala
ae5e11bebc arm: soc: NXP: Enable SEGGER RTT on all NXP SoCs
It seems like SEGGER is supported across all the NXP SoC families so
lets enable it across all of them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-04-26 14:49:57 -05:00
Adithya Baglody
246f03c9e6 x86: minnowboard: Enable the userspace mode
This enables the MMU with PAE mode and also enables the userspace
mode.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-25 14:46:00 -07:00
Adithya Baglody
3e3d1a1c8c x86: minnowboard: Add support for enabling MMU
The required linker and gen_mmu.py support added for minnowboard.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-25 14:46:00 -07:00
Andrew Boie
31bdfc014e userspace: add support for dynamic kernel objects
A red-black tree is maintained containing the metadata for all
dynamically created kernel objects, which are allocated out of the
system heap.

Currently, k_object_alloc() and k_object_free() are supervisor-only.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-24 12:27:54 -07:00
Maureen Helm
adf5b36a78 lpc54114: Remove unused include in soc.c
The lpc54114 soc.c file included clock_config.h unnecessarily.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Maureen Helm
57e80e5345 ext: mcux: Reorganize imported drivers into soc family subfolders
We have been combining imported mcux drivers into a flattened directory
structure to maximize driver reuse, but the introduction of additional
nxp soc families (lpc and imx) to zephyr has introduced driver naming
conflicts. This caused us to rename and modify imported files, such as
fsl_gpio.c/h, to make them unique across all three nxp soc families.
This makes updating the the mcux drivers complicated, especially for the
lpc family.

Reoganize the mcux drivers into soc family subfolders, so we can just
copy all the drivers from an mcux distribution (which is done on an
soc-basis) into the appropriate soc family folder. Undo all of the
naming changes that occurred when lpc and imx drivers were originally
imported. Undo the accidental squashing of the kinetis watchdog and dcdc
drivers that occurred when the imx drivers were introduced.

The drawback to this approach is that we have duplicate files when the
same hw ip modules exist in multiple soc families, however there are
only few cases where this occurs, such as fsl_lpuart and fsl_trng.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-24 07:55:48 -05:00
Leandro Pereira
16472cafcf arch: x86: Use retpolines in core assembly routines
In order to mitigate Spectre variant 2 (branch target injection), use
retpolines for indirect jumps and calls.

The newly-added hidden CONFIG_X86_NO_SPECTRE flag, which is disabled
by default, must be set by a x86 SoC if its CPU performs speculative
execution.  Most targets supported by Zephyr do not, so this is
set to "y" by default.

A new setting, CONFIG_RETPOLINE, has been added to the "Security
Options" sections, and that will be enabled by default if
CONFIG_X86_NO_SPECTRE is disabled.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-24 04:00:01 +05:30
Andy Ross
15cb5d7293 kernel: Further unify _reschedule APIs
Now that other work has eliminated the two cases where we had to do a
reschedule "but yield even if we are cooperative", we can squash both
down to a single _reschedule() function which does almost exactly what
legacy _Swap() did, but wrapped as a proper scheduler API.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Andy Ross
8606fabf74 kernel: Scheduler refactoring: use _reschedule_*() always
There was a somewhat promiscuous pattern in the kernel where IPC
mechanisms would do something that might effect the current thread
choice, then check _must_switch_threads() (or occasionally
__must_switch_threads -- don't ask, the distinction is being replaced
by real English words), sometimes _is_in_isr() (but not always, even
in contexts where that looks like it would be a mistake), and then
call _Swap() if everything is OK, otherwise releasing the irq_lock().
Sometimes this was done directly, sometimes via the inverted test,
sometimes (poll, heh) by doing the test when the thread state was
modified and then needlessly passing the result up the call stack to
the point of the _Swap().

And some places were just calling _reschedule_threads(), which did all
this already.

Unify all this madness.  The old _reschedule_threads() function has
split into two variants: _reschedule_yield() and
_reschedule_noyield().  The latter is the "normal" one that respects
the cooperative priority of the current thread (i.e. it won't switch
out even if there is a higher priority thread ready -- the current
thread has to pend itself first), the former is used in the handful of
places where code was doing a swap unconditionally, just to preserve
precise behavior across the refactor.  I'm not at all convinced it
should exist...

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-04-24 03:57:20 +05:30
Ioannis Glaropoulos
0b7c964f5f arch: arm: clear BFSR sticky bits in ARMv8-M Mainline MCUs
Contrary to ARMv7-M, in ARMv8-M MCUs with the Main Extension,
BusFault Status Register bits are sticky and must be cleared.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-04-23 08:40:15 -05:00
Maureen Helm
50b69fbb55 arm: nxp_kinetis: Remove unused defines from soc.h
Now that we get gpio irq numbers from dts, we can remove the defines
from soc.h

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-20 08:54:11 -05:00
Ding Tao
b4696bd7ec arch: arm: Fix coding style in file irq_relay.S
Make the code more human readable by Remove some TABs.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-04-19 14:54:28 -05:00
Wayne Ren
adf6f48e0d arch: arc: add the support of STACK_SENTINEL
* call the _check_stack_sentinel in unnested isr
return.

* for firq, _check_stack_sentinel is called in kernel
  isr stack because the limitation of banked register

* for normal irq, _check_stak_sentinel is called in
  the interruptted thread stack

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
8da51ee326 arch: arc: optimize the _SysFatalErrorHandler
* For STACK_CANERY, the processor should not hang
* as _SysFatalErrorHandler is always executed in
  isr context, so remove k_is_in_isr
* the function should return after k_thread_abort

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
24acf2a414 arch: arc: bug fixes in irq_load
remove magic numer, use IRQ_OFFLOAD macro

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Wayne Ren
3d9ba10b5c arch: arc: bug fixes and optimization in exception handling
The original exception handling has space to optimize and
and some bugs need to be fixed.

* define NANO_ESF
   * add the definition of NANO_ESF which is an irq_stack_frame
   * add the corresponding codes in exception entry and handler
   * remove _default_esf
* implement the _ARCH_EXCEPT
   * use trap exception to raise exception by kernel
   * add corresponding trap exception entry
   * add _do_kernel_oops to handle the exception raised by
     _ARCH_EXCEPT.
* add the thread context switch in exception return
   * case: kernel oops may raise thread context switch
   * case: some tests will re-implement SysFatalHandler to raise
     thread context switch.
   * as the exception and isr are handled in kernel isr stack, so
     the thread context switch must be in the return of exception/isr
     , and the exception handler must return, should not be decorated
     with FUNC_NORETURN
* for arc, _is_in_isr should consider the case of exception

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-04-17 10:50:12 -07:00
Andy Gross
09a8810b33 arm: userspace: Rework system call arguments
This patch changes the ARM system calls to use registers for passing
or arguments.  This removes the possibility of stack issues when
callers do not adhere to the AAPCS.

Fixes #6802

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-16 10:13:20 -07:00
Adithya Baglody
95126d1af6 boards: sam_e70_xplained: Enable userspace
Enabled userspace support for Atmel SAMe70.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-04-16 09:01:49 -07:00
Leandro Pereira
4d5fbbc517 arch: arm: Flush pipeline after switching privilege levels
During the transition of privilege levels while performing syscalls,
the ARM documentation recommends flushing the pipeline to avoid
pre-fetched instructions from being executed with the previous
privilege level.

The manual says:
   4.16 CONTROL register
   (...) after programming the CONTROL register, an ISB instruction
   should be used.
   (...) This is not implemented in the Cortex M0 processor.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-04-13 15:35:45 -05:00
Andrzej Głąbek
397e52f099 arch: nrf52: Correct the number of IRQs in nRF52840
The old value does not cover the IRQ assigned to the SPIM3 peripheral.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-04-12 14:19:53 -04:00
David Leach
c563e33102 drivers: entropy: Change KW41Z to use XOROSHIRO for RNG source
The TRNG IP block in the KW41Z is really an entropy source and not
intended to be used as a general purpose random number generator
source. The block has 15 slots to read from and when the last slot
is read it has to regenerate the 15 numbers. This process takes
3-5 seconds and is blocking. The change here is to use the TRNG as
an entropy source to the XOROSHIRO pseudo random number function
and then have the KW41Z use XOROSHIRO for random number generation.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
David Leach
00885bbf28 OpenThread: Normalize IEEE802.15.4 driver name for use by L2 layers
- Removed OT_PLAT_RADIO_DEVICE_NAME
- Changed OpenThread binding to use NET_AP_IEEE802154_DEV_NAME
- Modified Kconfig chain to ensure NET_AP_IEEE802154_DEV_NAME
  is enabled for both native 802.15.4 and OpenThread configurations
- Changed default setting of NET_L2_IEEE802154 in defconfig for mkw41z4.
- Fixed OpenThread api support code to use the state of mIsCcaEnabled
  in the transmit frame to conditionally invoke radio_api->cc() on
  transmits.

Signed-off-by: David Leach <david.leach@nxp.com>
2018-04-11 16:57:12 +03:00
Diego Sueiro
816330239e arch: Add imx7d m4 soc support
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.

Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.

The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README

The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.

The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:

+---------------+-----------------+---------------------------+
| Memory Name   | Start Address   | Size                      |
+===============+=================+===========================+
| TCML          | 0x007F8000      | 32KB                      |
+---------------+-----------------+---------------------------+
| TCMU          | 0x20000000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM_S       | 0x20180000      | 32KB                      |
+---------------+-----------------+---------------------------+
| OCRAM         | 0x00900000      | 128KB                     |
+---------------+-----------------+---------------------------+
| DDR           | 0x10000000      | 256MB                     |
+---------------+-----------------+---------------------------+

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-04-11 08:27:05 +02:00
Erwan Gouriou
6c2047fcd0 arch/arm: stm32: All SoCs have dts for I2C and SPI
All boards based on STM32 should use dts for I2C and SPI.
Move CONFIG flags selection from boards to arch and select them
for all STM32 SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-04-10 08:27:50 -05:00
Andrew Boie
548421828e arm_mpu: fix _get_region_attr()
srd bits start at bit 8, not bit 5.
To date we are not using sub-regions so this problem was
undetected.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-04-09 17:15:15 -05:00
Ilya Tagunov
77bbc42eaf arch: arm: soc: stm32l0: fix port H EXTI
Ports F and G are not present on some STM32L0 parts, so
for these parts port H external interrupt should be enabled
by writing value 0x5 instead of 0x7 to SYSCFG_EXTICRn registers
(see e.g. RM0367, 10.2.4).

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-04-05 10:31:43 -05:00
Tomasz Jurtsch
6dae38cb98 arch: riscv32: fe310: Always-On domain adress definition
Added always-on domain address definition

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-05 08:08:08 -05:00
Paolo Teti
700e4bd2e8 ARM: -march compile option is not set
Removing ${} variable evaluation fixes the issue.

For sam4s_xplained:

Before:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
/repos/zephyr/samples/hello_world/build$

After:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
...
-mthumb -mcpu=cortex-m4 -march=armv7e-m
...

Signed-off-by: Paolo Teti <paolo.teti@gmail.com>
2018-04-05 08:36:04 -04:00
Tomasz Bursztyka
a868561339 arch/quark_se: Enable SPI port 2 as a slave only
Quark SE provides a slave SPI.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
1ac6f4bd56 arch/quark_d2000: Switch to SPI DW driver
As QMSI driver does not support new SPI API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
4652f59d64 arch/quark_se_c1000_ss: Switch to SPI DW driver
As QMSI driver does not support new SPI API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
6d870ae25c arch/quark_se: Switch to native SPI DW driver
QMSI is not updated to latest SPI API. Switching to native DW driver,
until we find a way either to update the shim drivers in a
non-performant way, or updating QMSI itself enabling support for
scatter-gather type of buffers.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Tomasz Bursztyka
324265420b api/spi: Disable legacy API by default
Let's start deprecation work of the SPI legacy API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-04-04 19:02:35 +02:00
Youvedeep Singh
4a8b2d2d2f kernel: POSIX: Compatibility layer for POSIX message queue APIs.
This patch provides POSIX message queue APIs for POSIX
1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-04-03 15:30:44 -04:00
Ulf Magnusson
c9c18fa8b0 kconfig: Do not source "arch/posix/core/Kconfig"
This file never existed.

'source' currently ignores missing files instead of throwing an error,
due to Zephyr's custom globbing logic.

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-03-30 17:51:39 -04:00
Ulf Magnusson
93689bdc80 kconfig: Remove no-op selects of choice symbols
Selecting a choice symbol is always a no-op, and the latest version of
Kconfiglib prints a warning. This commit removes all selects of choice
symbols, which might make the Kconfig files a bit clearer and gets rid
of the warnings.

This is just a dumb removal. I did not try to guess the intent of each
select.

Fixes #6849

Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
2018-03-29 08:57:39 -04:00
Anas Nashif
993c350b92 cleanup: replace old jira numbers with GH issues
Replace all references to old JIRA issues (ZEP) with the corrosponding
Github issue ID.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-26 13:13:04 -04:00
Kumar Gala
8a824356e0 arch: arc: em{7,9,11}d: Add initial DTS UART support
Add support for getting some basic params from the DTS for the UART.
The ns16550 driver still needs to be updated to get IRQ and address
info from DTS.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Kumar Gala
311e6b9e3e arch: arc: Use DTS for all ARC SoCs
Now that all ARC SoCs we can remove code associated with !HAS_DTS and
select HAS_DTS at the architecture level.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Kumar Gala
60ec8be309 arch: em{7,9,11}d: Add dts support
Add initial device tree support for the em{7,9,11}d SoC and associated
em_starterkit boards.  The device tree at this point specifies cpu core,
memory, interrupt controller, uart's and i2c controllers.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-23 10:13:53 +01:00
Tomasz Bursztyka
74d1835505 drivers/i2c: Make QMSI SS driver IRQs set via CONFIG_ options
Now that dts i2 qmsi ss nodes generate the right options, let's use
them. Apply the relevant fixup on the targeted SoC.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
7af98f5e67 drivers/i2c: Use standard bitrate settings for QMSI SS driver
Apply the change on relevant arch/boards.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
9b77741d63 drivers/i2c: Use standard bitrate settings for QMSI driver
Apply the change on relevant arch/boards.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
2e972bc867 arch/x86: Enable i2c through DTS for quark_d2000
And adapt the relevant board accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
5fc1f5ff1d arch/x86: Enable i2c through DTS for quark_se
And adapt relevant boards accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
8f891ba702 drivers/i2c: Use standard bitrate settings for DW driver
Applying the change to relevant arch/boards, either in their Kconfig or
the dts specific files.

Taking the opportunity in dw driver to rename the variable the same way
as they are everywhere else in the code (s/dev/dw and s/port/dev) in
init function.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
e35a4a2576 boards/galileo: Switch to DTS for generating i2c settings
Thus dropping SoC based generated information.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
9ddd8d1e4d arch/x86: Enable i2c through DTS for quark_se SS
And adapt relevant boards accordingly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
6d247b5c2b drivers/i2c: Rename generic configure option in DW drivers
And adapt SoC's information relevantly.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Tomasz Bursztyka
d95fa65270 drivers/i2c: Cleanup Kconfig
Move driver specific to dedicated file when relevant (i.e.: more than
1-2 options), use if/endif also.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-03-23 10:42:33 +08:00
Carles Cufi
6656969598 arch: arm: nordic_nrf: Restore copyright years
A previous commit had mistakenly overwritten the copyright years instead
of extending the range. Fix this mistake so that the proper range is
recorded.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 13:25:44 +01:00
Carles Cufi
b2016da563 arch: arm: nrf: Rename common header to apply to all nRFx ICs
The existing nrf5_common.h now applies to other Nordic ICs that are not
part of the "5" family. Instead rename this to nrf_common.h to cover the
upcoming ICs that belong to other families.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Carles Cufi
f49150cab6 arch: arm: nrf: Rename nrf5 SoC Family to nrf
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-20 11:57:14 +01:00
Anas Nashif
e5f1b51f01 debug: fix RTT console Kconfig
Use HAS_ Kconfig option as intended, those are invisible option that
signify support of a certain feature that can be selected by a hardware
or platform.

For RTT and system view this was not dont in an inconsistent way.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-19 15:37:26 -04:00
Ilya Tagunov
48a5fbcaa9 drivers: flash: stm32f0: remove CONFIG_FLASH_PAGE_SIZE
STM32F0 flash driver already uses FLASH_PAGE_SIZE from HAL
in flash layout part, so CONFIG_FLASH_PAGE_SIZE is redundant
and confusing.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-18 17:02:53 -04:00
Andy Ross
9d367eeb0a xtensa, kernel/sched: Move next switch_handle selection to the scheduler
The xtensa asm2 layer had a function to select the next switch handle
to return into following an exception.  There is no arch-specific code
there, it's just scheduler logic.  Move it to the scheduler where it
belongs.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-18 16:58:12 -04:00
Andrew Boie
a967915e52 arch: add Kconfig for stack growth direction
This was previously just a #define in one header file, but we need
this expressed in Kconfig space in case some feature only works
properly with downward-growing stacks.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 16:25:22 -07:00
Leandro Pereira
2f5659d4d2 arch: x86: Unwind the stack on fatal errors
Prints up to 8 stack frames, with the following format:
  RETURN_ADDR(ARGUMENTS)

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-03-16 14:12:15 -07:00
Andrew Boie
e00564d15d x86: fix logic for thread wrappers
If we enable CONFIG_DEBUG_INFO, then we need to fixup the stack
on thread entry so that the EFLAGS value in the EBP slot doesn't
confuse the debugger or any runtime stack unwinding code.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 14:12:15 -07:00
qianfan Zhao
494bf56811 arch: arm: soc: stm32f0: add STM32F070XB SOC
Add initial support for STM32F070XB SOC

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-03-16 09:18:08 -05:00
Ilya Tagunov
00c0520247 arch: arm: soc: stm32l0: add I2C support
Add SPI support for STM32L0 series.
L0 SPI peripheral requires SCK pin speed workaround
to function properly.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-15 10:53:26 -05:00
Kumar Gala
0ecd77e435 arch: arc: quark_se_c1000_ss: Fix DCCM_SIZE
The DCCM_SIZE is defined in terms of K, not bytes, so we need to adjust
it from bytes (generated from dts) to K (used by e CONFIG_DCCM_SIZE).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-15 08:14:27 -05:00
Sundar Subramaniyan
037dddbe8f dts: arm: nrf52840_pca10056: Use DT to configure USB
Configure USB using DT for nrf52840_pca10056

Signed-off-by: Sundar Subramaniyan <sundar.subramaniyan@gmail.com>
2018-03-15 12:39:53 +01:00
Ilya Tagunov
9ae3fdc2ef arch: arm: soc: stm32l0: add I2C support
Add I2C support for STM32L0 series. LL-based driver
was already in place, so I've just enable it.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-14 09:02:25 -05:00
Kumar Gala
c9b0208552 arm: mps2_an385: Move dts.fixup to board dir
Move the dts.fixup back to board dir in prep for support mps2_an521.
The memory maps between the two mps2_an385 and mps2_an521 differ greatly
so its easier to just keep the fixup files with the board.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-13 15:29:21 -05:00
Carles Cufi
9afb0cfab0 kconfig: Remove UTF-8 character from author's name
Kconfiglib does not support UTF-8 properly yet, so avoid issues by
removing the UTF-8 character from the name until this is fixed.

See https://github.com/ulfalizer/Kconfiglib/pull/41

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-03-13 20:30:15 +01:00
Ioannis Glaropoulos
5475de105b arch: arm: define the ARM_SECURE_FIRMWARE option
This commit introduces the ARM_SECURE_FIRMWARE k-option,
which indicates that we are building an ARM Secure application.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ioannis Glaropoulos
a01e7903b2 arch: arm: SecureFault Handling for Cortex-M33
This commit contributes the implementation of the SecureFault
handling for ARMv8-M-based Cortex-M33. The implementation is
compiled conditionally with compile-time directive
CONFIG_ARM_SECURE_FIRMWARE, which is to signify the intention to
build a Secure image on ARMv8-M with Security Extensions.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-13 10:23:40 -05:00
Ilya Tagunov
b6da79cb82 arch: arm: soc: stm32l0: add STM32L073xZ SOC
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Ilya Tagunov
6a1cb6540f arch: arm: soc: stm32l0: fix indentation and comments in Kconfigs
Fix indentation and small comment typos in Kconfigs.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-03-13 10:23:23 -05:00
Aapo Vienamo
422bc240b4 soc: nrf5: Use i2c configure options generated from dts
SoC dts fixups are added and the i2c_nrf5 driver is modified to use
the values generated from the device tree.

The I2C_*_DEFAULT_CFG and I2C_*_IRQ_PRI options are removed from board
defconfigs. Bitrate and IRQ priority are configured using using the
device tree instead.

HAS_DTS_I2C is selected on all nrf5 boards to prevent generation of
conflicting defines from Kconfig.

Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi>
2018-03-13 14:14:13 +01:00
Ioannis Glaropoulos
c028f88b37 arch: arm: remove redundant asm inline headers
This commit removes the unnecessary asm inline header for ARM.
It also adapts the stack.h and exc.h to use the ARM CMSIS inline
functions to access the IPSR and MSP registers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-12 10:14:12 -05:00
Ioannis Glaropoulos
10b40ecaba arch: arm: conditionally select FP extension in cortex-m MCUs
This commit conditionally selects the ARMV7_M_ARMV8_M_FP option
in ARMv7-M/ARMv8-M Mainline processors, when the Floating Point
Extension is implemented (CPU_HAS_FPU is selected).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-11 21:53:50 -05:00
Ioannis Glaropoulos
b75b01050d arch: arm: Stack Overflow Usage Fault log for ARMv8-M Mainline
This commit contributes the Stack Overflow UsageFault dumping
for ARMv8-M implementations that support the Main Extension.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
cfab6e0806 arch: arm: define ARMv8-M Mainline K-option
This commit introduces the ARMV8_M_MAINLINE K-config option. The
option signifies the use of an ARMv8-M CPU supporting the Main
Extension. ARMv8-M Main Extension includes additional features
that are  not present in the ARMv7-M architecture.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Ioannis Glaropoulos
d2e0d975f6 arch: arm: ARMv7-M/ARMv8-M Mainline dependency for programmable prios
This commit forces CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS to
depend on ARMV7_M_ARMV8_M_MAINLINE. This allows the user to get
a build warning if he manually selects
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS for a CPU that does
not implement either ARMv7-M or ARMv8-M Mainline.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 16:10:07 -06:00
Kumar Gala
97331d1e98 arch: arm: mps2: Remove soc_irq.h
Move IRQ numbers into device tree so we can remove soc_irq.h.  We are
already using IRQ defines generated form the DTS so no point in having
soc_irq.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
fa0e8fd06d arch: arm: mps2: remove soc_memory_map.h
Further simplify the mps2 SoC code by removing soc_memory_map.h which
now only contains one define for the FPGAIO_BASE_ADDR.  We can just move
this to the once place its used.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
40b7be5197 drivers: i2c: Add DTS support to ARM SBCon I2C controller
Added device tree support to the ARM SBCon I2C controller.  We utilize
the compatiable "arm,versatile-i2c" the binding from Linux for the some
peripheral block.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
51db7b142c arch: arm: mps2: Remove unused defines and structs
Simplify the mps2 SoC code by removing defines and structs that aren't
used anywhere currently.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Kumar Gala
ad18f84f50 arch: arm: Refactor CONFIG_CORTEX_M
Clean up Kconfig so each SoC just selects the specific Cortex-M
implementaiton rather than having to select both CORTEX_M and
CORTEX_{M0, M3, M4, etc.}.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Justin Watson
aa7c91d0c2 driver: usart: Added support for interrupt driver USART on SAM E70.
Added interrupt support in the USART SAM serial driver.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-03-10 11:42:25 -06:00
Ioannis Glaropoulos
3b2f4b399d arch: arm: add missing floating-point fault logging
This commit adds the missing fault dumping for MemManage or Bus
fault occuring during floating-point lazy state preservation. In
addition, it introduces a Kconfig option for the ARMv7-M/ARMv8-M
Floating Point Extension.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 11:42:25 -06:00
Justin Watson
b9c65e1882 drivers: GPIO Added GPIO for SAM family.
Added GPIO driver for SAM family of SoCs.

Signed-off-by: Justin Watson <jwatson5@gmail.com>
2018-03-10 11:42:25 -06:00
Ioannis Glaropoulos
bd0ff3092a arch: arm: cmsis: cleanup cmsis.h and update error-code macros
This commit removes the macros for ARM fault flags from
include/arch/arm/cortex_m/cmsis.h header, since they are
defined in the respective core_cmXX.h header files. It also
modifies fault.c to use the updated fault macros taken directly
from ARM CMSIS headers.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-10 11:42:25 -06:00
Philémon Jaermann
8834a8d47b arm: stm32f446: Add support for stm32f446 SoC
Support for stm32f446xe SoC

Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
2018-03-10 11:42:25 -06:00
Endre Karlson
deeb74651b arm: stm32l0: Add support for stm32l0 soc
Add necessary kconfig and minimal device tree support for
the stm32l072xz variants.

Signed-off-by: Endre Karlson <endre.karlson@gmail.com>
2018-03-10 11:42:25 -06:00
Yannis Damigos
efbb7c61a1 arch/arm/soc/stm32f4: Add STM32F412CG MCU support
Add STM32F412CG MCU support.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-03-10 11:42:25 -06:00
a8a36a23fc spi: sam0: use Device Tree for configuration.
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.

Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances

Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.

Add the APA102 LED that's on the Trinket as a test.

Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-03-10 11:42:25 -06:00
Nathan Tsoi
28758fe986 arch: arm: STM32F051X8 support
Add support for the STM32F051X8 processor on the STM32F0DISCOVERY board

Signed-off-by: Nathan Tsoi <nathan@vertile.com>
2018-03-10 11:42:25 -06:00
f2651d0cc7 usb: sam0: add a USB device driver.
Implements a USB device driver for the SAM0 series.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-03-10 08:41:39 -05:00
Andy Gross
cc69d373d1 arch: arm: Change method of __swap processing
This patch reworks the current ARM __swap() function into a C function.
Due to some issues with using svc calls withing fault handlers, we
needed to change the way we initiate a swap by removing the dependence
on svc #0.

Before __swap() is called, the system has already done an irq_lock().
Upon return from __swap(), the equivalent of an irq_lock() is done due
to restoration of the key value from the irq_lock preceeding the call.

For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are
enabled.  There is no priority masking in v6m, so it's just a global
enable.  For ARM V7M, the priority mask has to be set to 0x0 to allow
for the pendsv IRQ to be taken.  This is done for both via a call to
irq_unlock(0).

After this unlock, a pendsv irq will be taken, either at the tail end
of the current irq handling if we are in handler mode, or immediately
due to the pendsv being asserted (no other outstanding irqs).  The next
thread will be scheduled.

Upon return from the context switch to the original
thread, the priority mask will already be correct due to the pendsv
processing.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-09 21:43:23 -05:00
Wayne Ren
2c577ff90e arch: arc: fix the bug of context switch in interrupt
* the bug comes out when a context switch happens in interrupt
* the bug only affects the em7d in emsk 2.3
* the bug is caused by
  * wrong operations of stack
  * wrong setting of SEC_STAT's IRM bit

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-03-08 11:01:11 +01:00
Wayne Ren
6612c9f683 arch: arc: bug fixes in arc mpu driver
fix the bug in _is_in_region
* RDB0 -> RDP0

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-03-08 11:01:11 +01:00
Andrzej Puzdrowski
c788f84f25 drivers: flash: move FLASH_HAS_PAGE_LAYOUT Kconfig from arch
Keyword FLASH_HAS_PAGE_LAYOUT is related to flash and should
be declared in its Kconfig.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-03-08 10:18:57 +01:00
Andrew Boie
c0771ea243 arch: x86: fix integer stub comments
The comment was obsolete; we simply do not allow use of the FPU or
vector math in ISRs. There is no desire to add such support, doing
this is properly offloaded to a worker thread.

Fixes #5283.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-06 17:16:03 -05:00
Andy Ross
285c5b26dd xtensa/asm2: Save shift/loop registers on exception entry
This was a little embarassing.  The swap code got this right, and the
interrupt exit path got it right, but on entry we weren't ever saving
the shift and loop registers for the interrupted context.

This almost always worked anyway as the loop registers aren't ever
used in any Zephyr code (gcc won't generate this style of loop AFAICT)
and the SAR shift amount register is generally used only in two pairs
of adjacent instructions making the chance of hitting that exact cycle
quite low in general.

But of course we have shift-happy crypto code in our tests, so this
got caught, thankfully.

See https://github.com/zephyrproject-rtos/zephyr/issues/6470

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-06 14:13:56 -08:00
Ioannis Glaropoulos
8c0c4be16a arch: arm: remove redundant dependence on ARM_CORE_MPU
MPU_STACK_GUARD option has a direct dependence on ARM_CORE_MPU.
Therefore, it is not required to have a conditional selection
of the option (if ARM_CORE_MPU) in ARM_STACK_PROTECTION.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-03-06 08:36:34 -05:00
Punit Vara
a74725f1d3 kernel: Add posix API for semaphore
Add semaphore posix APIs.

Signed-off-by: Punit Vara <punit.vara@intel.com>
2018-03-05 20:51:36 -05:00
Leandro Pereira
02bc5fa8e0 soc: esp32: Enable building with newer ESP-IDF
ESP-IDF commit cb31222e added the dependency on a file named
"sdkconfig.h", which is equivalent to "autoconf.h" generated by kbuild
used in Zephyr.  It does not depend on anything from that file, though,
so just provide an empty file to keep the compiler from complaining.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-03-05 19:49:06 -05:00
Youvedeep Singh
216883ca82 kernel: POSIX: Compatibility layer for POSIX read-write lock APIs.
This patch provides POSIX read-write lock APIs for POSIX 1003.1
PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-03-05 19:27:37 -05:00
Andy Ross
bdac8d070f xtensa/asm2: Fix stack pointer during preemption spills
When returning into a different thread than we interrupted, we
obviously need to spill all the existing register windows to make sure
all their values are in the old thread's stack.  But the code to do
this forgot to reset the current stack pointer to the value it had at
interrupt time (it was still pointing to the saved context below
that), so the caller of the interrupted function was spilling to the
wrong spot.

This wouldn't show up as an instant failure, it would only happen when
switching BACK to the improperly-spilled thread.  And even then it
would be a noop if the original interrupt handler was deep enough to
have spilled that function naturally.

In practice, this happened only in some instances on ESP-32 (which has
more windowed registers than qemu) when interrupting the idle thread
(which is very shallow) with a (very simple) timer interrupt.  Trivial
to see, hard to find.

See https://github.com/zephyrproject-rtos/zephyr/issues/6346 for more
detail.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-03-05 19:06:07 -05:00
Ioannis Glaropoulos
571069e986 arch: arm: correct fault address logging
In ARMv7-M (and ARMv8-M) architecture it is
implementation defined whether separate MMFAR and BFAR are
implemented. This commit ensures that we always get the true
faulting address displayed in case of MemManage- or BusFault.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-27 09:38:43 -06:00
Kumar Gala
83fa6c9554 dts: arm: Refactor SoC dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into arch/arm/soc/<SOC>/dts.fixup so
we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
dc6472f868 dts: x86/atom: Refactor SoC dts.fixup into arch/x86/soc/atom
Move common SoC dts.fixup defines into arch/x86/soc/atom/dts.fixup so we
remove duplication in the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
d08661119e dts: ia32: Refactor SoC dts.fixup into arch/x86/soc/ia32
Move common SoC dts.fixup defines into arch/x86/soc/ia32/dts.fixup so we
remove duplication in the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
7e32b1d11f dts: quark_se: Refactor SoC dts.fixup into arch/x86/soc/intel_quark/<SOC>
Move common SoC dts.fixup defines into
arch/x86/soc/intel_quark/quark_se/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/x86/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Kumar Gala
6becb64dfc dts: quark_se_c1000_ss: Refactor dts.fixup into arch/arc/soc
Move common SoC dts.fixup defines into
arch/arc/soc/quark_se_c1000_ss/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arc/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-26 10:55:36 -06:00
Alberto Escolar Piedras
f004e0475e native: added more proper command line parameters parsing
Added a basic command line parameter parsing framework

Added the following options by now:
--stop-at=<time>: Auto-stop after <time> seconds
--seed=<seed>   : random seed for entropy device
--testargs      : any argument that follows is ignored in top level
                  and made available thru
                  native_get_test_cmd_line_args()

All command line parameters are still avaliable by calling
native_get_cmd_line_args(), but now you can also call
native_get_test_cmd_line_args() to get whatever was set after
--testargs

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-23 07:33:11 -05:00
David B. Kinder
3673698df1 doc: fix misspellings in XTENSA Kconfig
regular scan for spelling issues

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-22 15:28:04 -05:00
Youvedeep Singh
4d72e48d31 arch: POSIX: Add guard into posix_cheats file.
Some of APIs of POSIX implmentation layer has same name as
native_posix architecture. posix_cheats.h is used to handle this
duplication in API name. Adding a guard in posix_cheats.h based on
CONFIG_PTHREAD_API.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
8d040f1bcb kernel: POSIX: Compatibility layer for POSIX timer APIs.
This patch provides POSIX timer APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
d50b1fe981 kernel: POSIX: Compatibility layer for POSIX clock APIs.
This patch provides POSIX clock APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
1f2e126d4d kernel: POSIX: Compatibility layer for POSIX sleep APIs.
This patch provides POSIX sleep APIs for POSIX 1003.1 PSE52 standard.
sleep(n) is implemented using Zephyr k_sleep API.
uleep(n) is implemented using Zephyr k_sleep/k_busy_Wait API.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
7eabf1025c kernel: POSIX: Compatibility layer for scheduler APIs.
This patch provides scheduler APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
Youvedeep Singh
c8aa6570c1 kernel: POSIX: Compatibility layer for pthread APIs.
This patch provides pthread APIs for POSIX 1003.1 PSE52 standard.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2018-02-21 19:17:28 -05:00
2e7146b7a6 arch: refactor the SAM0 SoC fixups into a SoC-level file.
This prepares the way for the Trinket M0.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-02-21 16:03:10 -06:00
Kumar Gala
87a8d199d8 dts: atmel_sam: Refactor SoC dts.fixup into arch/arm/soc/atmel_sam
Move common SoC dts.fixup defines into
arch/arm/soc/atmel_sam/<BAR>/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 16:02:12 -06:00
Kumar Gala
a73e8fa083 dts: nxp: Refactor imx/rt dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into arch/arm/soc/nxp_imx/rt/dts.fixup
so we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
4c50b1f199 dts: nxp: Refactor kwx dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kwx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
8760edd6a5 dts: nxp: Refactor kl2x dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kl2x/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
29d4ea327f dts: nxp: Refactor lpc54xxx dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
340bc66f24 dts: nxp: Refactor k64 dts.fixup into arch/arm/soc
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/k6x/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 11:38:36 -06:00
Kumar Gala
5a5e352899 dts: ti: Refactor TI SoC dts.fixup into arch/arm/soc/ti_simplelink
Move common SoC dts.fixup defines into
arch/arm/soc/ti_simplelink/<BAR>/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-02-21 10:57:23 -06:00
Yannis Damigos
22c1018bfb dts: arm: 96b_carbon use DT to configure USB
Configure USB using DT for 96b_carbon

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-21 09:17:12 -06:00
Leandro Pereira
3beb481bab soc: esp32: Fix compile warnings when redefining BIT() macro
Include `soc.h` first, which will include the ESP-IDF headers -- which
will define the `BIT()` macro without checking if they're already
defined, like the Zephyr headers do.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-02-20 16:23:53 -05:00
Daniel Wagenknecht
44bfd32f22 dts: spi: add remaining SPI fixup defines for STM32
Add SPI fixup defines on STM32 SoC family level for all SPIs that
are supported on one or more SOCs of that SoC family.

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-02-20 09:47:43 -05:00
Andy Ross
60fd06830e xtensa: Make _arch_curr_cpu() work outside SMP
The xtensa headers use this for simplicity when SMP is not enabled.
It should still build on older platforms that don't include the
asm2-style CPU pointer scheme.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
392b3b5aa6 xtensa/asm2: Don't needlessly build asm2 sources
Non-asm2 devices without a generated SoC interrupt file will see a
compile failure due to the missing header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
57f30bd8cc esp32: Move hard firmware function addresses to the linker script
This matches the way other firmware-provided functions are done.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
0244d01fda xtensa/asm2: Don't return into dead threads
It's not impossible that something we just handled (e.g. a machine
exception) called k_thread_abort() on our current thread.  Don't try
to return into it, check the DEAD state.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
3f5027f835 xtensa: Fix noreturn attribute on error handlers in asm2
In asm2, the machine exception handler runs in interrupt context (this
is good: it allows us to defer the test against exception type until
after we have done the stack switch and dispatched any true
interrupts), but that means that the user error handler needs to be
invoked and then return through the interrupt exit code.

So the __attribute__(__noreturn__) that it was being decorated with
was incorrect.  And actually fatal, as with gcc xtensa will crash
trying to return from a noreturn call.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
c3c4ea730d nios2: Add include for _check_stack_sentinel()
This API moved into kswap.h and the resulting warning on this arch got
missed.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
245b54ed56 kernel/include: Missed nano_internal.h -> kernel_internal.h spots
Update heading naming given recent rename

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
53eceffb7f esp32: Set CPU pointer on app cpu at startup
It's not enough to wait for a switch, lots of things need this early.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
b0b9b3d16a xtensa: Report CPU number in exceptions
In SMP contexts it's good to know which CPU blew up.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
e694656345 kernel: Move per-cpu _kernel_t fields into separate struct
When in SMP mode, the nested/irq_stack/current fields are specific to
the current CPU and not to the kernel as a whole, so we need an array
of these.  Place them in a _cpu_t struct and implement a
_arch_curr_cpu() function to retrieve the pointer.

When not in SMP mode, the first CPU's fields are defined as a unioned
with the first _cpu_t record.  This permits compatibility with legacy
assembly on other platforms.  Long term, all users, including
uniprocessor architectures, should be updated to use the new scheme.

Fundamentally this is just renaming: the structure layout and runtime
code do not change on any existing platforms and won't until someone
defines a second CPU.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
9c62cc677d kernel: Add kswap.h header to unbreak cycles
The xtensa-asm2 work included a patch that added nano_internal.h
includes in lots of places that needed to have _Swap defined, because
it had to break a cycle and this no longer got pulled in from the arch
headers.

Unfortunately those new includes created new and more amusing cycles
elsewhere which led to breakage on other platforms.

Break out the _Swap definition (only) into a separate header and use
that instead.  Cleaner.  Seems not to have any more hidden gotchas.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
d3376f2781 kernel, esp32: Add SMP kconfig flag and MP_NUM_CPUS variable
Simply define the Kconfig variables in this patch so they can be used
in later patches.  Define MP_NUM_CPUS correctly on esp32.  No code
changes.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
e717267abf kernel, esp32: Add _arch_start_cpu API
This is a mostly-internal API to start a secondary system CPU, with an
implementation for the ESP-32 "APP" cpu.  Exposed in kernel.h because
it's plausibly useful for asymmetric MP code managed by an app.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
00f3d2e53a esp-32, qemu_xtensa: Use asm2 by default
Set these SoCs to use asm2 by default

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
865bbd6b69 xtensa-asm2: Handle alloca/movsp exceptions
Xtensa register windows have a special exception that happens when the
stack pointer needs to be moved, but the caller function has already
spilled its registers below it.

I thought these were unexercised in Zephyr code, but they turn out to
be thrown by the existing mem_pool tests when run in the 32-register
qemu environment (but not on 64-register hardwre).  Because the effect
of the exception is to unspill the caller, there is no good way to
handle this in a traditional handler.  Instead put a 5-instruction
stub in front of the user exception handler (i.e. incurring that cost
on every trap and every L1 interrupt) to test before doing the normal
entry.

Works, but would be nicer to optimize this in the future so that only
true alloca exceptions take that cost.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
bbd7912a6b xtensa-asm2: Exception/interrupt handler should check stack sentinel
This got forgotten.  Note that this function is empty if
CONFIG_STACK_SENTINEL is unconfigured.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
60932d1427 xtensa: Add hook to do register window spills
This macro was already available add an external symbol so C code can
access it (via CALL0 -- it's not and can't be an actual function).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
2867bfc1eb xtensa asm2: Fixup stack alignment at runtime
The API allows any byte count for stack size, and tests in fact check
that a stack with a 499 byte stack works correctly.  No choice, have
to do this at runtime.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
02b2fe1c9e xtensa: THREAD_MONITOR hooks for asm2
You'd this feature would be portable, but it's arch-specific.
Initialize the CONFIG_THREAD_MONITOR stuff, placing the __thread_entry
struct (which AFAICT is dead: nothing in the tree actually reads it)
at the top of the stack.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
7707fcfa51 xtensa: asm2 needs to honor thread preemption
Forgot to check the thread preemption status when fetching the stack
to restore.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
63ad74f833 xtensa: Fix thread entry point
The stack initilaization was calling the user-provided entry function
directly, which works fine until that function returns, at which point
it will try to unspill A0-A3 from the 16 bytes above the allocated
stack and then "return" to a NULL pointer.

The kernel provides a _thread_entry() function that does cleanup
properly, so use that.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
2c1449bc81 kernel, xtensa: Switch-specific thread return value
When using _arch_switch() context switching, the thread return value
is a generic hook and not provided by the architecture.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
bf2139331c xtensa: Add exception/interrupt vectors in asm2 mode
This adds vectors for all interrupt levels defined by core-isa.h.

Modify the entry code a little bit to select correct linker sections
(levels 1, 6 and 7 get special names for... no particularly good
reason) and to constructed the interrupted PS value correctly (no EPS1
register for exceptions since they had to have interrupted level 0
code and thus differ only in the EXCM bit).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
7de010b5e5 xtensa: Interrupt generator script and output for qemu & esp32
This python script reads the core-isa.h interrupt definitions (via
running a template file through the toolchain preprocessor to generate
an input file) and emits a fully populated, optimized C handling code
that binary searches only the declared interrupts at a given level and
correctly detects spurious interrupts (and/or incorrect core-isa.h
definitions).

The generated code, alas, turns out not to be any faster than simply
searching the interrupt mask with CLZ (er, NSAU in xtensese), though
it could be faster in theory if the compiler made different choices,
see comments.  But I like this for the robustness of the fully
populated search trees and the checking of level vs. mask.

This simply commits the script output into the source tree, including
some checking code to force a build error if the toolchain changes the
headers incompatibly.  It would be better long term to have these
headers be generated at build time, but that requires more cmake fu
than I have.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
c761ae9695 xtensa: Add Kconfig for asm2 layer
The asm2 layer will build alongside the traditional assembly, but the
reverse is not true.  Add a CONFIG_XTENSA_ASM2 to force its use at
runtime and disable the older code.

Note that the older assembly had an initialization function that is
properly part of the timer driver.  Move a C equivalent into the timer
driver itself for now to prevent a build breakage.  Long term we need
to clean that driver up in a bunch of other ways.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
6f3036091a xtensa: Implement _xt_ints_on/off for asm2
Legacy xtensa had a rather complicated implementation of en/disabling
interrupts, owing to the "software priority" feature (which plays
games with INTENABLE and INTLEVEL to allow for interrupts to interrupt
each other outside their normal priorities).  But that's not a Zephyr
feature, it's enabled by a XT_USE_SWPRI value that comes from platform
headers and isn't enabled on any of our boards.  Dead code, basically.

Replace with the obvious implementation when asm2 is in use.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
a0dd2de6fd xtensa: Remove _xt_set_exception_handler()
This was a dead API.  Nothing ever used it, it wasn't exposed in any
API headers.  It never appeared in documentation.  It's not
particularly clear why a Zephy app would want to hook
architecture-specific exceptions instead of simply using the portable
error framework anyway. And it's not supported by asm2.  Delete.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
b2c74e017e xtensa/asm2: Add a _new_thread implementation for asm2/switch
Implement _new_thread in terms of the asm2 switch mechanism.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
042d8ecca9 kernel: Add alternative _arch_switch context switch primitive
The existing __swap() mechanism is too high level for some
applications because of its scheduler-awareness.  This introduces a
new _arch_switch() mechanism, which is a simpler primitive that looks
like:

    void _arch_switch(void *handle, void **old_handle_out);

The new thread handle (typically just a stack pointer) is specified
explicitly instead of being picked up from the scheduler by
per-architecture code, and on return the "old" thread handle that got
switched out is returned through the pointer.

The new primitive (currently available only on xtensa) is selected
when CONFIG_USE_SWITCH is "y".  A new C _Swap() implementation based
on this primitive is then added which operates compatibly.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
32a444c54e kernel: Fix nano_internal.h inclusion
_Swap() is defined in nano_internal.h.  Everything calls _Swap().
Pretty much nothing that called _Swap() included nano_internal.h,
expecting it to be picked up automatically through other headers (as
it happened, from the kernel arch-specific include file).  A new
_Swap() is going to need some other symbols in the inline definition,
so I needed to break that cycle.  Now nothing sees _Swap() defined
anymore.  Put nano_internal.h everywhere it's needed.

Our kernel includes remain a big awful yucky mess.  This makes things
more correct but no less ugly.  Needs cleanup.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
a34f884f23 xtensa: New asm layer to support SMP
SMP needs a new context switch primitive (to disentangle _swap() from
the scheduler) and new interrupt entry behavior (to be able to take a
global spinlock on behalf of legacy drivers).  The existing code is
very obtuse, and working with it led me down a long path of "this
would be so much better if..."  So this is a new context and entry
framework, intended to replace the code that exists now, at least on
SMP platforms.

New features:

* The new context switch primitive is xtensa_switch(), which takes a
  "new" context handle as an argument instead of getting it from the
  scheduler, returns an "old" context handle through a pointer
  (e.g. to save it to the old thread context), and restores the lock
  state(PS register) exactly as it is at entry instead of taking it as
  an argument.

* The register spill code understands wrap-around register windows and
  can avoid spilling A4-A15 registers when they are unused by the
  interrupted function, saving as much as 48 bytes of stack space on
  the interrupted stacks.

* The "spill register windows" routine is entirely different, using a
  different mechanism, and is MUCH FASTER (to the tune of almost 200
  cycles).  See notes in comments.

* Even better, interrupt entry can be done via a clever "cross stack
  call" I worked up, meaning that the interrupted thread's registers
  do not need to be spilled at all until they are naturally pushed out
  by the interrupt handler or until we return from the interrupt into
  a different thread.  This is a big efficiency win for tiny
  interrupts (e.g. timers), and a big latency win for all interrupts.

* Interrupt entry is 100% symmetric with respect to medium/high
  interrupts, avoiding the problems seen with hooking high priority
  interrupts with the current code (e.g. ESP-32's watchdog driver).

* Much smaller code size.  No cut and paste assembly.  No use of HAL
  calls.

* Assumes "XEA2" interrupt architecture, the register window extension
  (i.e. no CALL0 ABI), and the "high priority interrupts" extension.
  Does not support the legacy processor variants for which we have no
  targets.  The old code has some stuff in there to support this, but
  it seems bitrotten, untestable, and I'm all but certain it doesn't
  work.

Note that this simply adds the primitives to the existing tree in a
form where they can be unit tested.  It does not replace the existing
interrupt/exception handling or _Swap() implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
8dca7ae587 xtensa: Make high priority interrupts optional
Xtensa has a "high priority" class of interrupt levels which ignore
the EXCM bit and can thus interrupt running exception handlers.  These
can't be used for C handlers in the general case[1] because C code
needs to be able to throw window over/underflow exceptions, which are
not reentrant.

But the high priority interrupts might be useful to a carefully
designed application, or to unit tests of low level architecture code.
So make their generation optional with this kconfig option.

[1] ESP-32 has a high priority interrupt for its watchdog, apparently.
    Which is sort of OK given that it never needs to return to the
    interrupted code.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Andy Ross
88538e77c1 xtensa: Move register window exception handlers into a separate file
No behavior changes, just code motion.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-02-16 10:44:29 -05:00
Wayne Ren
bb50a88045 arch: arc: apply the new thread stack layout
The new thread stack layout is as follow:

|---------------------|
|  user stack         |
|---------------------|
| stack guard (opt.)  |
|---------------------|
|  privilege stack    |
-----------------------

For MPUv2
  * user stack is aligned to the power of 2 of user stack size
  * the stack guard is 2048 bytes
  * the default size of privileg stack is 256 bytes.
  For user thread, the following MPU regions are needded
    * one region for user stack, no need of stack guard for user stack
    * one region for stack guard when stack guard is enbaled
    * regions for memory domain.
  For kernel thread, the stack guard region will be at the top, adn
  The user stack and privilege stack will be merged.

MPUv3 is the same as V2's layout, except no need of power of 2
alignment.

* reimplement the user mode enter function. Now it's possible for
kernel thread to drop privileg to user thread.

* add a separate entry for user thread

* bug fixes in the cleanup of regs when go to user mode

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
e445ab6f21 arch: arc: handle exception in privilege task when USERSPACE enabled
when USERSPACE is enabled, exception is handled in the privilege
stack of thread. This make thread context switch is possible in the
exception handler. For some case,e.g. tests, this is useful.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
4433f81b47 arch: arc: MPUv2 enables MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
enable MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT for ARC MPU v2

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
0a71b106d1 arch: arc: save user thread's context into privilege stack
disable the U bit of irq.ctrl, so the user thread's context will
be saved into privilege stack when interrupts/exception come.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
a970b5fd32 arch: arc: scrub regs of kernel context before returning to userspace
scrub all the regs of kernel context before returnning to userspace.
For sys call, ro is not cleared as it's a return value of sys call.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
7ef2506611 arch: arc: enable US bit to check user mode
Enable us bit to check user mode more efficienly.

US is read as zero in user mode. This will allow use mode sleep
instructions, and it enables a form of denial-of-service attack
by putting the processor in sleep mode, but since interrupt
level/mask can't be set from user space that's not worse than
executing a loop without yielding.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
8feca6c2ef arch: arc: modify the kconfig for mpu case
* user space support requires THREAD_INFO
* for MPU version 2, the stack align is at least 2048 bytes
  * the smallest mpu region is 2048 bytes
  * the region size must bt power of 2
  * the start address of region must be aligned to the region size

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
e91733c78b arch: arc: bug fixes and add user space support in secure mode
* bug fixes
* add user space support in secure mode

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Wayne Ren
f81dee0b2b arch: arc: add user space support for arc
* add the implementation of syscall
  * based on 'trap_s' intruction, id = 3
* add the privilege stack
  * the privilege stack is allocted with thread stack
  * for the kernel thread, the privilege stack is also a
    part of thread stack, the start of stack can be configured
    as stack guard
  * for the user thread, no stack guard, when the user stack is
    overflow, it will fall into kernel memory area which requires
    kernel privilege, privilege violation will be raised
* modify the linker template and add MPU_ADDR_ALIGN
* add user space corresponding codes in mpu
* the user sp aux reg will be part of thread context
* When user thread is interruptted for the 1st time, the context is
  saved in user stack (U bit of IRQ_CTLR is set to 1). When nest
  interrupt comes, the context is saved in thread's privilege stack
* the arc_mpu_regions.c is moved to board folder, as it's board
  specific
* the above codes have been tested through tests/kernel/mem_protect/
  userspace for MPU version 2

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-02-16 12:20:16 +01:00
Anas Nashif
8949233390 kconfig: fix more help spacing issues
Fix Kconfig help sections and add spacing to be consistent across all
Kconfig file. In a previous run we missed a few.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-15 23:20:55 -05:00
Carles Cufi
f24f50b12e arm: cortex_m: Use new ARMV6_M_ARMV8_M_BASELINE in vector relay
The old ARMV6_M Kconfig option has been removed, and so to correctly set
the dependencies for SW_VECTOR_RELAY we need to use the new
ARMV6_M_ARMV8_M_BASELINE.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-14 12:49:09 +01:00
Andy Gross
4c47d7f7e2 arch: arm: Enable stack guard before starting main
This patch fixes a hole in the stack guard configuration.  The initial
branch to main is missing the stack guard configuration.

Fixes: Issue #3718

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 13:06:41 -08:00
Andy Gross
465e04cae7 arch: arm: Fixup stack end calculations
This patch fixes calculations for the top of the interrupt and main
stacks.  Due to power of two alignment requirements for certain MPUs,
the guard size must be taken into account due to the guard being
counted against the initial stack size.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
f7ec62eb85 arm: mpu: Enable userspace support for NXP and ARM
This patch set implements the APIs and changed required to support
the user mode thread support.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
1c047c9bef arm: userspace: Add ARM userspace infrastructure
This patch adds support for userspace on ARM architectures.  Arch
specific calls for transitioning threads to user mode, system calls,
and associated handlers.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Andy Gross
9ccdcb9be6 arm: mpu: Add user context API placeholder
This patch adds a configure_mpu_user_context API and implements
the required function placeholders in the NXP and ARM MPU files.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 12:42:37 -08:00
Michael Scott
7a9b688526 x86: fix build warning
During compile of lwm2m_client using qemu_x86, the following build
warning was noticed:
zephyr/arch/x86/core/excstub.S:132:2: warning: "/*" within comment [-Wcomment]
  /*

In commit ff42bdd0a0 ("debug: remove option GDB_INFO"), the comment tag
was omitted.  Fix the comment end tag.

Signed-off-by: Michael Scott <michael@opensourcefoundries.com>
2018-02-12 19:21:06 -05:00
Anas Nashif
11a9625eaf debug: remove DEBUG_INFO option
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Anas Nashif
ff42bdd0a0 debug: remove option GDB_INFO
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-12 13:58:28 -08:00
Sean Nyekjaer
a09b6f538a arch: atmel_sam0: rename samd SoC series to samd21
Atmel SAMD21 series was classified too broadly as SAMD.
This patch names it correctly to make room,
for other members of SAMD series

Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
2018-02-09 08:34:55 -06:00
247782a7b3 sam0: move the UART and SPI configuration into pinmux.
Also pull out the SERCOM pads configuration to defines.  Note that the
SAM0 has a two level configuration - a signal (like TX) is mapped to a
pad, and then a pad is mapped to a function on a pin.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-02-08 12:09:46 -06:00
Ioannis Glaropoulos
0d6fa4db0a arch: arm: define Cortex-M23, Cortex-M33 CPUs
This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Ioannis Glaropoulos
a0a03d7597 arch: arm: common Armv8-M support
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-02-08 12:07:38 -06:00
Savinay Dharmappa
98d6a9928c driver: usb_dw: Move base address and irq num of usb to soc.h
base adrress and irq number moved to soc.h

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-02-07 22:55:11 -05:00
Ramakrishna Pallala
3eb62bc905 drivers: i2c: Add i2c master driver for Nios-II i2c core
Add I2C Master driver for Nios-II I2C soft IP core.

This driver relies upon the Altera HAL I2C driver for all the bus level
transactions, interrupt handling and register programming.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-07 19:37:35 -05:00
Alberto Escolar Piedras
3b924ede3e native: coverage exclusions
Just some exclusions to coverage in code which cannot be
reached, or can only be reached in error conditions

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
66c1652fb8 native: native_posix timer + irq fix
Added possibility to reconfigure CONFIG_SYS_CLOCK_TICKS_PER_SEC
for the native_posix board (before it could only be 100)
+
Fixed tickless idle support
+
Minor fixes in irq wrapping

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
Alberto Escolar Piedras
a99a14c3b7 native: added posix_get_hw_cycle()
Added function (for all ARCH_POSIX boards) to get the
the current clock cycle of the CPU

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-07 16:28:16 -05:00
David B. Kinder
c2bf3af1de doc: fix misspellings in Kconfig files
Missed some misspellings during regular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-02-07 14:51:46 -05:00
Carles Cufi
4b23b5d589 arch: arm: Do not enable SW_VECTOR_RELAY with M0+ and VTOR
Whenever a Cortex-M0+ supports the VTOR register it makes no sense to
use the software vector relay mechanism. Therefore change the logic so
that SW_VECTOR_RELAY does not get enabled whenever a VTOR register is
present, but enable it if an M0+ has no VTOR.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-02-07 07:31:32 -06:00
Rajavardhan Gundi
1e6adba9ef drivers/interrupt_controller: Introduce multi-level interrupt support
In a scenario where a platform harbours multiple interrupts to the
extent the core cannot support it, an interrupt controller is added
as an additional level of interrupt. It typically combines several
sources of interrupt into one line that is then routed to the parent
controller.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-02-06 22:39:05 -05:00
Gil Pitney
3f68f2bc97 soc: ti_simplelink: cc32xx: Remove ARMV7_M guard from CMSIS_IRQn_Type
Remove unnecesary #ifdef CONFIG_ARMV7_M guard in soc.h file.

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2018-02-06 17:34:25 -06:00
Chunlin Han
18560a01a4 arm: Generate privileged stacks
This patch adds the generation and incorporation of privileged stack
regions that are used by ARM user mode threads.  This patch adds the
infrastructure for privileged stacks.  Later patches will utilize the
generated stacks and helper functions.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
e8860fe8be arm: Add app data section alignment constraints
This patch adds application data section alignment constraints
to match the region definition requirements for ARM MPUs.  Most MPUs
require a minimum of 32 bytes of alignment for any regions, but some
require power of two alignment to the size of a region.

This requires that the linker align the application data section to
the size of the section.  This requires a linker pass to determine the
size.  Once this is accomplished the correct value is added to a linker
include file that is utilized in subsequent linker operations.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Andy Gross
65ac049105 kernel: arm: core: Fix thread monitor wrapping
This fixes the wrapping of the thread monitor specific parts of the
new thread code.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-06 15:31:16 -08:00
Erwan Gouriou
c734c2972f flash: remove obsolete FLASH_DRIVER_NAME
Replace seldom occurrences of FLASH_DRIVER_NAME by equivalent
and commonly used FLASH_DEV_NAME.

Fixes #5919.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-02-06 11:48:53 -06:00
Ilya Tagunov
d2b09497eb arm: core: cortex_m: introduce CPU_CORTEX_M_HAS_VTOR option
Some ARMv6-M Cortex-M0+-based SOCs have VTOR register
and can relocate vector table just as ARMv7-M ones.
Vector table relocation path should be choosed
by VTOR presence, not by arch.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-02-06 08:59:36 -06:00
Yannis Damigos
5d3016aa65 boards: arm: stm32f3_disco: Enable SPI_1, SPI_2 ports
Enable SPI1 and SPI2 ports on stm32f3_disco.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-05 09:21:33 -06:00
Ramakrishna Pallala
c02a2bed61 drivers: flash: Add Nios-II QSPI flash driver
Add Altera Nios-II QSPI Flash controller driver which has
has 1024 blocks or sectors wich each sector size being 64K bytes.
This driver supports flash erase, write, read and lock operations.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-02-05 06:30:50 -08:00
Alberto Escolar Piedras
fb442b0d9a native: exclude from coverage not coverable code
Some code in the POSIX architecture is only meant to handle
safely errors which should never occur and therefore
are not covered.
=> We exclude them from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
c53924cfe9 native: SOC: exclude unlikely code from coverage
Some code in the POSIX SOC (inf_clock) will only be executed
if the program is terminated by receiving a SIGTERM in a particular
part. Therefore to avoid confusing developers with changing
coverage, let's exclude it from the coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
d9e1182f3a native: POSIX arch: Exclude unlikely code from coverage
Some code in the POSIX arch core will only be executed
in some very atypical cases depending on the host load.
To avoid confusing developers, let's exclude it from the
coverage reports.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-05 06:26:53 -08:00
Alberto Escolar Piedras
a7e55b82dd native: arch: added recommended stack size config
Added a new config variable with the recommended stack
size for threads which are only meant for the posix architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-02-02 07:48:46 -08:00
Yannis Damigos
6a6a4294c2 boards: arm: olimexino_stm32: Enable SPI1 port
Enable SPI1 port on olimexino_stm32.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Yannis Damigos
af0c9fc349 drivers: spi_ll_stm32: Enable SPI driver for F1 family
Enables SPI driver for STM32F1 SoCs

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-02-01 08:19:49 -06:00
Anas Nashif
9a238cd538 soc: atom: support enumerating PCI devices
This hook is needed to support enumerating PCI devices.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-02-01 02:19:45 -05:00
Maureen Helm
d107411820 arm: nxp_kinetis: Define FLASH_DRIVER_NAME macro for kl2x and kwx SoCs
Defines the FLASH_DRIVER_NAME macro in soc.h for kinetis kl2x and kwx
SoC series. This macro is used by the storage and dfu subsystems, as
well as the flash_shell sample.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-01-31 16:43:40 -06:00
Ramakrishna Pallala
301acb8e1b kernel: include: rename nano_internal.h to kernel_internal.h
Rename the nano_internal.h to kernel_internal.h and modify the
header file name accordingly wherever it is used.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-01-31 10:07:21 -06:00
Alberto Escolar Piedras
a35364dd1a native: minor consistency rename
rename main_clean_up() to posix_exit() for consistency
with all other global functions of this architecture

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-01-29 23:23:56 -05:00
Adithya Baglody
77755afa19 userspace: ARM: Fixed Kconfig for ARM_USERSPACE
Currently in zephyr the support for the arm userspace has not be
merged. But the Kconfig always sets the userspace flag and causes a
build failure. This is blocking the test cases for userspace.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-01-29 23:11:11 -05:00
Carles Cufi
7361d3d74d config: bootloader: Add support for MCUboot
Add a new Kconfig option, BOOTLOADER_MCUBOOT, that automatically sets
the required options necessary to make the resulting image bootable by
the MCUboot open source bootloader. This includes the text section
offset and the vector relay table for Cortex-M0, and in the future it
might also add the DTS overlay required to link at slot0 offset in
flash.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-29 18:05:18 -05:00
Kumar Gala
b8173d960e drivers: flash: NXP KL2X/KW4xZ: Add device tree support
Add device tree support for the "nxp,kinetis-ftfa" flash controller used
on the NXP KL2X and KW4xZ SoCs.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Kumar Gala
a394693d2f drivers: flash: NXP k6x/kw2xd: Convert to use device tree
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree.  We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.

Fixes: #5788

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-29 16:34:49 -06:00
Anas Nashif
b8ea7c889d x86: remove HAS_DTS checking
All X86 boards are now DTS enabled.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-29 10:38:32 -06:00
Michał Kruszewski
aee2ff526d ext: nordic: Replace HAL and MDK with the ones from nrfx
The old HAL and MDK have been removed from the source tree.
Since RADIO HAL is not yet present in nrfx, the "nrf_radio.h" file
was temporarily moved to "nrfx/hal" folder. It will be replaced with
the proper file from nrfx in its next update.

Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-01-29 03:02:06 +05:30
Andrzej Głąbek
c84c2eaa82 ext: nordic: Add initial adaptation layer for nrfx
This commit adds a glue layer that adapts nrfx to be usable in Zephyr
as a host environment and files with static configuration of nrfx
drivers for several supported SoCs.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-01-29 03:02:06 +05:30
Daniel Wagenknecht
3f2b376cd6 dts: stm32l4: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 L4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

disco_l475_iot1 boards fixup blocks for devices connected via SPI
and I2C stay in board level dts.fixup file, because they are board
specific.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
080fe4d4cf dts: stm32f3: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F3 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
285c9506d5 dts: stm32f1: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F1 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
d76858f6ae dts: stm32f4: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

96b_carbon boards fixup block for Bluetooth HCI device via SPI
stays in board level dts.fixup file, because it is board specific.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Daniel Wagenknecht
be430a05cb dts: stm32f0: move dts.fixup to soc family level
This moves and merges the existing board-level dts.fixup files
for STM32 F0 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.

Contributes to #5707

Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
2018-01-28 10:35:30 -06:00
Kumar Gala
2dfee62a5e drivers: flash: atmel sam0: Convert to use device tree
Convert Atmel SAM0 flash driver to use device tree to get the flash
controller name and base address.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-27 21:09:28 -06:00
Kumar Gala
dc98605f4a drivers: flash: stm32: Convert to use device tree
Convert STM32 flash drivers to use device tree to get the flash
controller name and base address.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-26 09:25:57 -06:00
Ding Tao
bbd307edfd arch: arm: vector_table: Support vector table soft relay
For SoCs that don't support vector table relocation in hardware, may not
support bootloader like mcuboot.

We introduce a way to relocate vector table in software by forwarding
the control of incoming IRQs to a new vector table which address is save
at fixed SRAM address.

User can change the data in that fixed SRAM address in order to relocate
vector table in software way.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
bf949b0647 arch: arm: Add SW_VECTOR_RELAY Kconfig flag
Eanble soft relay IRQ handler for Cortex-M0 target if this flag set
true.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
e28db91acf arch: arm: stm32f0: Enable CONFIG_CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
Enable this flag for all stm32f0 series in order to support hardware
vector table relocation feature.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Ding Tao
0be502e68f arch: arm: Add CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP Kconfig flag
Cortex-M0 do not have the Vector Table Base Address Offset Register, so
Cortex-M0 vector table address can not be changed.

But in some Cortex-M0 SoCs like STM32F0 series, they have some mechanism
that can remap the vector table address to the start address of SRAM.

Use this flag to indicates whether current Cortex-M0 SoC support such a
remap or not.

Signed-off-by: Ding Tao <miyatsu@qq.com>
2018-01-26 06:57:28 +05:30
Kumar Gala
b0768ec66a arm: nordic: remove last references to CONFIG_SOC_FLASH_NRF5_DEV_NAME
We use FLASH_DEV_NAME everywhere now so we can remove the use of
CONFIG_SOC_FLASH_NRF5_DEV_NAME.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-25 15:23:00 -06:00
Kumar Gala
44141f6939 arm: nordic: Refactor dts.fixup files to SoC vs board
Refactor common dts.fixup for the SoC into the SOC_SERIES dts.fixup
file.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-25 15:23:00 -06:00
Neil Armstrong
d9c00b4e68 arch: arm: soc: provide support for stm32f072
Support the ST STM32F072xB SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-01-25 15:13:53 -06:00
Carles Cufi
90a45d2eca soc: nrf51: Define flash driver name for nRF51
In order to be able to build MCUboot for nRF51 we require the flash
driver name in the nRF51 soc.h header.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-25 14:41:22 +01:00
Anas Nashif
5124711d87 native: ignore format-truncation warnings (REVERTME)
This is enabled by default in GCC 7, disable for now. Tracked in
issue #5732

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-25 04:45:35 +05:30
Andrzej Puzdrowski
ff7dfc4fb4 dts: bindings: add support for the flash driver name
So far, DT did not support the flash driver name.
Any flash-controller should have the appropriate
flash driver that should be identified by its name.

This path adds generic support for extract the description
from the flash-controller node,
adds implementation of this property for all nrf5x targets.


Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2018-01-23 12:29:50 -06:00
Shiksha Patel
4a892ae81a lpc: Add nxp_lpc soc family to soc directory
Add soc configuration support for lpc soc family, Kconfigs and soc files
for lpcxxx soc.

Add dtsi file for lpc54xxx.

Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-01-23 09:18:32 -06:00
Wayne Ren
5ca2c05316 arch: arc: Add _arch_mem_domain_configure
add the _arch_mem_domain_configure api to match the PR #5065 to avoid
compile failure in the future

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-18 11:50:59 -08:00
Wayne Ren
9a40bf6b7e arch: arc: Add the intial support of memory domain
Refering the ARM's implementation, the initial support of memory
domain in ARC is added:
* changes in MPU drivers
* changes in Kconfig
* codes to configure memory domain during thread swap
* changes in linker script template
* memory domain related macro definitions

the commited codes are simply tested through
samples/mpu/mem_domain_apis_test.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2018-01-18 11:50:59 -08:00
73d045e281 spi: add a SPI driver for the SAM0 series.
Impleentation is master only and uses polling to read and write.

Signed-off-by: Michael Hope <mlhx@google.com>
2018-01-13 07:39:05 -05:00
David B. Kinder
fd04de2d10 doc: fix misspellings in Kconfig files
periodic scan for typos missed during normal reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-01-12 20:58:56 -05:00
Kumar Gala
b92a40a798 drivers: entropy: stm32: Remove STM32F411XE from building
It appears the STM32F411XE doesn't support RNG so remove enabling it
from the SoC defconfig and flag an error if attempting to build the
driver on that SoC.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-12 19:42:54 -05:00
Andrew Boie
df48e11d98 build: warn user about Meltdown vulnerability
A fix for this issue is in progress, meanwhile warn the user that
they may be susceptible to this problem if they enable user mode on
an x86-based target that is not known to be immune.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-01-12 15:12:32 -08:00
Sebastian Bøe
4b61bd1b7a kconfig: Prune kconfig files that don't match the ARCH or BOARD
When Kconfiglib was introduced it caused a significant performance
issue. This patch uses pruning to mitigate the performance issue.

The pruning exploits the fact that before the Kconfig database is
parsed we already know what ARCH and BOARD has been selected. So in
theory we could prune away all Kconfig sources that are not related to
the current ARCH or BOARD. In practice, it is only the Kconfig sources
in zephyr/arch/$ARCH and zephyr/board/$ARCH/ that are easy to prune.

Still, that is quite a few Kconfig sources. For qemu_x86 this patch
reduced the number of parsed Kconfig source files from 632 to
272. This pruning resulted in a incremental reconfiguration (time
cmake ..) speedup of 21% (0.56s to 0.46) and a clean build speedup of
4% (Using board qemu_x86 and sample hello_world).

Furthermore, it should be easier to maintain ARCH's and BOARD's
out-of-tree since the user now has a mechanism to redirect where
Kconfig sources are found. But this has not been explored.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-01-12 07:29:05 -05:00
Erwan Gouriou
164fb32cf6 drivers: entropy: stm32: limit driver to SoC supporting it
In STM32 family, RNG IP is available only on F4 and L4 series.
Besides STM32F401 does not support is neither.
Get entropy driver available on STM32 devices supporting it and
generate a compilation issue on STM32 devices that do not own
the RNG IP.

Solves #5448

Signed-Off-By: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-01-11 19:00:19 -05:00
Neil Armstrong
9c3f7e11fb arch: arm: soc: stm32f0: include LL spi header
Include the STM32Cube LL SPI Header for STM32F0

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-01-11 19:00:19 -05:00
Jonas Pfaff
1d8e7a58c0 arm: atmel: soc: Soc init can be executed twice
Signed-off-by: Jonas Pfaff <jonas.pfaff@gmail.com>
2018-01-11 19:00:19 -05:00
Kumar Gala
cd7ca95378 arm: nxp_mpu: Fix build issue when asserts enabled
When asserts are enabled we run into an issue with newlib and types of
printf style formatters not matching.  The easy fix to this is to cast
the uint32_t to u32_t to make things consistent with or without newlib
enabled.

This fixes #5645

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-01-11 15:20:03 -06:00
Yannis Damigos
4d2dbab036 boards: stm32f1: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
c868ac0238 boards: stm32f0: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
2cb692e7de boards: stm32f3: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
96740a0570 boards: stm32l4: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
d60dc69ee7 boards: stm32f4: Clean up driver generic flags
Clean up driver generic flags from boards' _defconfig files

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Yannis Damigos
a6f8283ecd arch: st_stm32: Add common series configuration file
Add common series configuration file

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-01-11 14:35:45 -06:00
Carles Cufi
7d764b35f3 cmake: Use path-corrected version of ZEPHYR_BASE
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.

Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2018-01-11 14:59:03 -05:00
Ilya Tagunov
935d0ce89b soc: arm: stm32: fix startup SystemCoreClock values
Current STM32 SoC initialization code sets really weird startup values
to SystemCoreClock. It should be consistent with Reference Manuals after
this change.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
2018-01-08 08:38:17 -07:00
Anas Nashif
9f6c7838e5 arch: fix typo defafult -> default
Simple typo fix.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-08 08:08:45 -05:00
Anas Nashif
7ae749828f kconfig: fix help text indentation
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-08 08:08:45 -05:00
b69c452e6f arch: add support for the SAMD21G18A used in the Arduino Zero.
Signed-off-by: Michael Hope <mlhx@google.com>
2018-01-04 13:18:25 -05:00
Jan Van Winkel
30b65d8986 arm: stm32l4: include RNG ll header
Include low level random generator header in case stm32 random number
generator should be used by entropy driver

Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
2018-01-04 09:18:21 -05:00
Anas Nashif
61fe98c573 kconfig: rename CONFIG_BSP_SHARED_GDT_RAM_*
We stopped using BSP_ in configs long time ago, this one got stuck for
some reason.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-01-04 09:17:03 -05:00
Sebastian Bøe
74174809da gen_isr_tables: Minor refactoring
Minor refactor to gen_isr_tables.py; "if not" is difficult to read.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-01-04 08:55:26 -05:00
Alberto Escolar Piedras
e04764dbc7 native: Handle gracefully SIGTERM and SIGINT
When SIGTERM or SIGINT are received handle them
by gracefully exiting the program.

Fixes #5477

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-01-02 15:26:34 -05:00
Anas Nashif
72fe097bc0 testing: add option to generate coverage reports
With the native port we are able to generate coverage reports, add the
needed options to the compliler and add a kconfig option to enable this
on the supported architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Alberto Escolar Piedras
76f7644118 arch: native: Run Zephyr natively in a POSIX OS
A new arch (posix) which relies on pthreads to emulate the context
switching
A new soc for it (inf_clock) which emulates a CPU running at an
infinely high clock (so when the CPU is awaken it runs till completion
in 0 time)
A new board, which provides a trivial system tick timer and
irq generation.

Origin: Original

Fixes #1891

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Anas Nashif
5146dbbc58 arch: architecture defines kernel entry
Make defining the kernel entry architecture specific and move it to the
architecture domain.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-27 14:16:08 -05:00
Anas Nashif
f4ddb62bfa kconfig: move ARCH_HAS_THREAD_ABORT to arch level
Was ARM specific and could not be used by other architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2017-12-27 14:16:08 -05:00
Ramakrishna Pallala
12d614d0b8 drivers: gpio: add support for Altera Nios-II PIO controller
The PIO cores on Altera Nios-II processors can be used
for GPIOs and each PIO core can be configured as Input only,
Output only or as Bidirectional port from the Qsys tool.

The present Nios-II softcpu image on the Zephyr only has the
support for Output only port and the PIOs[0:3] are wired to
LED[0:3] on the Altera MAX10 board.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-21 12:02:24 -08:00
Adithya Baglody
9cde20aefa kernel: mem_domain: Add to current thread should configure immediately.
when a current thread is added to a memory domain the pages/sections
must be configured immediately.
A problem occurs when we add a thread to current and then drop
down to usermode. In such a case memory domain will become active
the next time a swap occurs.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-12-21 11:52:27 -08:00
Adithya Baglody
13ac4d4264 kernel: mem_domain: Add an arch interface to configure memory domain
Add an architecure specfic code for the memory domain
configuration. This is needed to support a memory domain API
k_mem_domain_add_thread.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-12-21 11:52:27 -08:00
Ramakrishna Pallala
27aced168d arch: nios2: enable System ID soft IP driver
The system ID core is a simple read-only device that
provides Qsys systems with a unique identifer.

Nios-II processor systems use the system ID core to
verify that an executable program was compiled targeting
the actual hardware image configured in the target FPGA.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-15 18:12:00 -05:00
Anas Nashif
429c2a4d9d kconfig: fix help syntax and add spaces
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-13 17:43:28 -06:00
Wayne Ren
5f349a4d4d arch: arc: fix the comments and coding style
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
cdfb59a276 arch: arc: add the support of MPU version 3
MPU version 3 is included in em7d of em_starterkit 2.3.

The differences of MPU version 3 and version 2 are:

* different aux reg interface
* The address alignment requirement is 32 bytes
* supports secure mode
* supports SID (option)
* does not support memory region overlap

This commit adds the support MPU version 3 and also make some changes to
MPU version 2 to have an unified interface.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
0892cd7f46 board: arc: em_starterkit: Add em7d support of em_starterkit 2.3
* em7d of em_starterkit 2.3 supports secure mode. add the support
  in kconfig and build system.

* change the default configuration of em_starterkit 2.3 to em7d

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
528c960ae7 arch: arc: Add the support of secure mode for em
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:

* different irq stack frame. so need to change the definition of
  _irq_stack_frame, assembly code.

* new aux regs, e.g, secure status(SEC_STAT), secure vector base
  (VECT_BASE_S)

* interrupts and exceptions, secure mode has its own vector base;
  interrupt can be configured as secure or normal through the
  interrupt priority aux reg.

* secure timers. Two secure timers (secure timer 0 and timer 1) are
  added.Here, for simplicity and backwards compatibility original
  internal timers (timer 0 and timer1) are used as sys clock of zephyr

* on reset, the processor is in secure mode and secure vector base is
  used.

Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Wayne Ren
52e4c197f3 arch: arc: Add FIRQ option
Add FIRQ option and change the _isr_wrapper. Currently, firq is
enabled by default, but in some arc configuration, firq can be
disabled.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-12-13 12:05:33 -05:00
Andrzej Puzdrowski
d095963e73 drivers: flash: Assert implementation of Flash Page Layout
Some drivers doesn't implement flash API page layout extension
which is causing the application crash once the API was calling.
This patch introduce system termination for this in those drivers
which doesn't implement extension. This will help to discover this
problem early.

It is not done by preprocessor check because it is possible to have
enabled a driver which support and a driver which doesn't support
this API simultaneously.

Now FLASH_PAGE_LAYOUT configuration option is accessible only in case
that at last one driver which implements mentioned API is enabled.

Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
2017-12-12 14:23:50 -06:00
Neil Armstrong
7e2fd68b1f arm: stm32f0: include I2C ll header
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Sudarsana Nagineni
aca079c9fc boards: olimex stm32-e407, stm32f407g_disc1: Enable USB OTG Support
Enable USB OTG support for olimex stm32-e407 and stm32f407g_disc1
boards by adding USB OTG to the pinmux table. Also, fix out of
range endpoint addresses in CDC ACM case for STM32F4 based boards.

Signed-off-by: Sudarsana Nagineni <sudarsana.nagineni@intel.com>
2017-12-12 12:36:08 -06:00
Neil Armstrong
22b4d19a6d ARM: stm32f030x8: fix FLASH_PAGE_SIZE
Fix to the correct flash page size for the stm32f030x8 SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Neil Armstrong
071cff7fb5 ARM: stm32f0: switch flash registers to volatile
Like other STM SoCs (L4 and F0), switch the flash registers struct
to volatile.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-12 12:36:08 -06:00
Ramakrishna Pallala
47595b1c10 boards: nios2: fix nios2 flashing issue
'make flash' is failing for altera_max10 board due to the
missing NIOS2_CPU_SOF environment variable. Though it is set
in arch/nios2/soc/nios2f-zephyr/CMakeLists.txt but it is not
taking effect when flashing script is run. The reason could be
following which is mentioned in https://itk.org/Wiki/CMake_FAQ

"environment variables SET in the CMakeLists.txt only
take effect for cmake itself (configure-time), so you cannot use
this method to set an environment variable that a custom command
might need (build-time)."

Now, NIOS2_CPU_SOF is set from boards/nios2/altera_max10/board.cmake
file which is more logical because all the FLASH related environment
variables are being set from board.cmake

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-12 11:40:29 -05:00
Ramakrishna Pallala
151f431efa arch: nios2: update nios2 softcpu image
Update nios2 softcpu image which supports additional
soft IP's like I2C, SPI, SGDMA, QSPI, SysID, etc...

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2017-12-12 08:25:58 -05:00
Neil Armstrong
494e1734e0 ARM: stm32f0: fix syscfg mapping to fix EXTI config
The exticrX registers were shifted by a word, so configuring
an EXTI line on a port different of PA misconfigured the EXTI line
source and could flood with unwanted events.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-07 08:08:41 -06:00
Anas Nashif
abbaac9189 cleanup: remove nanokernel/nano leftovers
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-12-05 09:44:23 -06:00
Piotr Mienkowski
dafdfadfbe drivers: Add Atmel SAM I2S (SSC) driver
Added Inter-IC Sound driver (based on SSC module) for Atmel
SAM MCU family.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-2509
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-11-30 10:30:33 -05:00
Piotr Mienkowski
dbcc7429e6 drivers: Add Atmel SAM DMA (XDMAC) driver
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-11-30 10:30:33 -05:00
Savinay Dharmappa
b8745dab61 dts: x86: Add device tree support for QUARK_X1000 soc based devices
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-27 22:18:20 -05:00
Anas Nashif
9c1da0dfa6 kconfig: clean CPU features and define only once
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-27 22:15:30 -05:00
Anas Nashif
a372eaedcc kconfig: move IRQ_OFFLOAD to a more generic place
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-27 22:15:30 -05:00
Adithya Baglody
808ad6101e x86: swap: save the scratch pad registers.
Save the required scratch pad register (in this case only edx)
before calling the C function.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-27 11:50:50 -05:00
Savinay Dharmappa
d77e6581e9 dts: x86: Add device tree support for atom based devices
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-24 10:10:47 -05:00
Anas Nashif
1f1143ac87 build: use kconfig to select generated artifacts
Not all boards require the various binary formats zephyr generates. So
be selective based on the arch, SoC or board and only geenrate the
binaries actually needed.

Fixes #5009

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-23 07:29:13 -05:00
Chunlin Han
d051740ee0 arm: implement API to validate user buffer
Implement API to validate user buffer. This API will iterate
all MPU regions to check if the given buffer is user accessible
or not. For #3832.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-11-17 19:01:11 -05:00
Maureen Helm
457699cd3c arm: Enable the ARM MPU on the NXP i.MX RT SoC and board
Unlike other NXP SoCs currently in Zephyr, the mimxrt1052 has the ARM
MPU rather than the NXP MPU. Start out by enabling it with a simple set
of memory regions for "flash" (ITCM), "ram" (DTCM), and the peripheral
buses. More regions will need to be added when we implement support for
external memories.

Tested with:
- samples/mpu/mpu_stack_guard_test
- tests/kernel/mem_protect/protection

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-11-15 09:09:58 -06:00
Maureen Helm
41d5808321 arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and
series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core,
512 KB TCM, and many peripherals including 2D graphics, an LCD display
controller, camera interface, SPDIF and I2S. Unlike other SoCs in
Zephyr, the mimxrt1052 has no internal flash.

This initial port to mimxrt1052 configures the system clock to operate
at 528 MHz, and enables the serial/uart and gpio interfaces to support
the hello_world and blinky samples. Support for additional Zephyr driver
interfaces will come later.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-11-15 09:09:58 -06:00
Savinay Dharmappa
7c8a23d643 dts: arc: Add dts support for arc
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-11-15 07:21:10 -06:00
Adithya Baglody
4a20aad15a dts: x86: RAM start address needs to be page aligned for arduino 101.
When CONFIG_X86_MMU is enabled for arduino 101 the start address
should be aligned to 4kB. If not aligned the page tables would not
be created and the build fails.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-13 10:21:58 -08:00
Anas Nashif
6d4d1ea912 arch: arm: fix EM7D makefile
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-11-13 10:55:26 -05:00
Sebastian Bøe
0829ddfe9a kbuild: Removed KBuild
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
Sebastian Bøe
12f8f76165 Introduce cmake-based rewrite of KBuild
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.

Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.

This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.

For users that just want to continue their work with minimal
disruption the following should suffice:

Install CMake 3.8.2+

Port any out-of-tree Makefiles to CMake.

Learn the absolute minimum about the new command line interface:

$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..

$ cd build
$ make

PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html

Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
2017-11-08 20:00:22 -05:00
David B. Kinder
7e3ed1465f doc: fix Kconfig misspellings
Kconfig files are processed to create configuration
option documentation.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-11-08 13:50:35 -05:00
Adithya Baglody
538fa7b37c x86: MMU: Configure page tables entries for memory domain in swap.
During swap the required page tables are configured. The outgoing
thread's memory domain pages are reset and the incoming thread's
memory domain is loaded. The pages are configured if userspace
is enabled and if memory domain has been initialized before
calling swap.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Adithya Baglody
f7b0731ce4 x86: MMU: Memory domain implementation for x86
Added support for memory domain implementation.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Adithya Baglody
83bedcc912 ARM: MPU: Arch specific memory domain APIs
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-07 12:22:43 -08:00
Andrew Boie
2a8684f60c x86: de-couple user mode and HW stack protection
This is intended for memory-constrained systems and will save
4K per thread, since we will no longer reserve room for or
activate a kernel stack guard page.

If CONFIG_USERSPACE is enabled, stack overflows will still be
caught in some situations:

1) User mode threads overflowing stack, since it crashes into the
kernel stack page
2) Supervisor mode threads overflowing stack, since the kernel
stack page is marked non-present for non-user threads

Stack overflows will not be caught:

1) When handling a system call
2) When the interrupt stack overflows

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-11-07 09:31:49 -08:00
Gustavo Lima Chaves
9bb07ff69a jailhouse: add support for x2APIC mode for all LOAPIC accesses
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.

By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.

When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.

Here are some outputs of the the command line

  $ sudo ./tools/jailhouse cell stats tiny-demo

on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:

Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                          7         0
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_msr                            1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xapic                          0         0
vmexits_xsetbv                         0         0

Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                       4087        40
vmexits_xapic                       4080        40
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_msr                            1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xsetbv                         0         0

Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)

COUNTER                              SUM   PER SEC
vmexits_total                       4087        40
vmexits_msr                         4080        40
vmexits_management                     3         0
vmexits_cr                             2         0
vmexits_cpuid                          1         0
vmexits_exception                      0         0
vmexits_hypercall                      0         0
vmexits_mmio                           0         0
vmexits_pio                            0         0
vmexits_xapic                          0         0
vmexits_xsetbv                         0         0

See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Gustavo Lima Chaves
97a8716a4f x86: Jailhouse port, tested for UART (# 0, polling) and LOAPIC timer
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:

   - hello_world
   - philosophers
   - synchronization

The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.

Testing it is just a matter of:
  $ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
  $ sudo insmod <path to jailhouse.ko>
  $ sudo jailhouse enable <path to configs/qemu-x86.cell>
  $ sudo jailhouse cell create <path to configs/tiny-demo.cell>
  $ sudo mount -t 9p -o trans/virtio host /mnt
  $ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
  $ sudo jailhouse cell start tiny-demo
  $ sudo jailhouse cell destroy tiny-demo
  $ sudo jailhouse disable
  $ sudo rmmod jailhouse

For the hello_world demo case, one should then get QEMU's serial port
output similar to:

"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""

Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.

As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).

Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.

You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.

Other config differences from pristine QEMU defaults worth of mention
are:

   - there is no HPET when running as Jailhouse guest. We use the LOAPIC
     timer, instead
   - there is no PIC_DISABLE, because there is no 8259A PIC when running
     as a Jailhouse guest
   - XIP makes no sense also when running as Jailhouse guest, and both
     PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
     config is set to

This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.

[1] https://github.com/siemens/jailhouse

Reference to Jailhouse's booting preamble code:

Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Gustavo Lima Chaves
ca3d51b5fa build: Only have MMU_BOOT_REGION decl. for HPET if the latter is on
This would impact builds with no CONFIG_HPET_TIMER=y set.

Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
2017-11-07 08:58:49 -05:00
Youvedeep Singh
833025dd94 timer: xtensa_sys_timer: Tickless Kernel Implementation for Xtensa
Implement Tickless Kernel support for Xtensa Architecture.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-11-07 08:17:40 -05:00
Bobby Noelte
3849b36f09 arch: arm: soc: provide support for stm32f091
Support the ST STM32F091xC SoC.

Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
2017-11-06 11:39:16 -06:00
Youvedeep Singh
fc78ddf7d3 ARM: nrf52: Power Management for nrf52 series SOC
Add support for nrf52 series SOC. This patch Adds :-
1. Architecture specific Power Management APIs.
2. APIs for invoking various Power Management tasks into nrf52.

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-11-06 09:29:10 -05:00
Kumar Gala
75833d4f52 arm: nxp_kinetis: cleanup soc.h - remove unused defines
Remove defines for IRQs we don't use.  We should be getting this from DT
so this gives us a list of what we need to cleanup.  Remove various
memory address offset defines to the ones we actually use.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-11-03 13:52:57 -05:00
Jan Kiszka
283a0cdafb x86: MMU: Rename gen_mmu script
It's x86-only.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2017-11-03 09:29:39 -07:00
Leandro Pereira
b007b64d30 kernel: Add option to ensure writable pages are not executable
This adds CONFIG_EXECUTE_XOR_WRITE, which is enabled by default on
systems that support controlling whether a page can contain executable
code.  This is also known as W^X[1].

Trying to add a memory domain with a page that is both executable and
writable, either for supervisor mode threads, or for user mode threads,
will result in a kernel panic.

There are few cases where a writable page should also be executable
(JIT compilers, which are most likely out of scope for Zephyr), so an
option is provided to disable the check.

Since the memory domain APIs are executed in supervisor mode, a
determined person could bypass these checks with ease.  This is seen
more as a way to avoid people shooting themselves in the foot.

[1] https://en.wikipedia.org/wiki/W%5EX

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-02 13:40:50 -07:00
Adithya Baglody
edd072e730 tests: benchmarking: cleanup of the benchmarking code.
The kernel will no longer reference the code written in the
test folder.

GH-1236

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-11-02 09:01:06 -04:00
Leandro Pereira
da9b0ddf5b drivers: Rename random to entropy
This should clear up some of the confusion with random number
generators and drivers that obtain entropy from the hardware.  Also,
many hardware number generators have limited bandwidth, so it's natural
for their output to be only used for seeding a random number generator.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-01 08:26:29 -04:00
Leandro Pereira
adce1d1888 subsys: Add random subsystem
Some "random" drivers are not drivers at all: they just implement the
function `sys_rand32_get()`.  Move those to a random subsystem in
preparation for a reorganization.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-11-01 08:26:29 -04:00
Carles Cufi
e08a5b0200 arch: arm: kinetis: Remove duplicate CLOCK_CONTROL config option
The CLOCK_CONTROL config option is already defined in
drivers/clock_control, so there's no need to redefine it in arch/.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2017-11-01 11:48:07 +01:00
Anas Nashif
035814efc6 boards: move pinmux driver to board/soc dir
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-31 12:32:34 -04:00
Anas Nashif
9b93334832 soc: ti_simplelink: rename header directory for registers
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-31 12:32:34 -04:00
Anas Nashif
780324b8ed cleanup: rename fiber/task -> thread
We still have many places talking about tasks and threads, replace those
with thread terminology.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-30 18:41:15 -04:00
Andrei Emeltchenko
b1372a857d quark_se: Enable GPIO needed for USB DW driver
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2017-10-30 08:30:48 -04:00
Andrew Boie
3f508e911e x86: fix CONFIG_DEBUG_INFO build error
This doesn't have any register operands and needs a size suffix.
Fixes: #4480

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-24 12:50:13 -07:00
Adithya Baglody
76edf8a681 x86: MMU: Enable boot time PAE page tables.
In PAE boot tables the __mmu_tables_start points to page directory
pointer (PDPT). Enable the PAE by updating the CR4.PAE and
IA32_EFER.NXE bits.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
725de70d86 x86: MMU: Create PAE page structures and unions.
Created structures and unions needed to enable the software to
access these tables.
Also updated the helper macros to ease the usage of the MMU page
tables.

JIRA: ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
d1703691c8 x86: MMU: Generation of PAE tables
If CONFIG_X86_PAE_MODE is enabled for the build, then gen_mmu.py
would generate the boot time page tables in PAE format.
This supports 3 level paging i.e Page Directory Pointer(PDPT), Page
Directory(PD) and Page Table(PT). Each Page Table Entry(PTE) maps to
a 4KB region. Each Page Directory Entry(PDE) maps a 2MB region.
Each Page Directory Pointer Entry(PDPTE) maps to a 1GB region.

JIRA: ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Adithya Baglody
efe795270d x86: MMU: Kconfig option to enable the PAE tables.
Page Address Extension(PAE) page tables would be used
if this option is enabled.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Bobby Noelte
2f7688bfd3 arch: arm: core: fix vector table relocate write to flash
Some SOCs (e.g. STM32F0) can map the flash to address 0 and
the flash base address at the same time. Prevent writing to
duplicate flash address which stops the SOC.

Allow Cortex M SOCs to create their own vector table relocation
function.

Provide a relocation function for STM32F0x SOCs.

Fixes #3923

Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-10-23 12:31:47 +02:00
Maciej Debski
db8fd88fab arch: arm: soc: provide support for stm32f0.
Fixes #3923

Signed-off-by: Maciej Debski <maciej.debski@rndity.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-10-23 12:31:47 +02:00
Piotr Mienkowski
26ba99e972 drivers: Add Atmel SAM family I2C (TWI) driver
Added I2C bus (TWI) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.

Tested on Arduino Due board.

Origin: Original

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-10-23 10:18:08 +02:00
Adam Podogrocki
61467e019e iwdg: the sample of the use of STM32 Independent Watchdog
JIRA: ZEP-2347

Change-Id: I808e9f110681735cae45d14c5802636012f018cc
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-10-23 09:51:16 +02:00
Adam Podogrocki
6d4da19602 iwdg: make independent watchdog driver compliant with STM32Cube LL API
Appropriate inclusion done for F1/F3/F4/L4 families in SoC tree.

JIRA: ZEP-2347

Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
2017-10-23 09:51:16 +02:00
Kumar Gala
46555f17e9 i2c: stm32f3: Cleanup how we enable the specific I2C driver
Match change we made to how I2C is enabled for other stm32 platforms:

Right now we allow for the I2C subsystem to be built without any drivers
enabled that utilize it.  When we added support for the new STM32 I2C
driver we forced the I2C driver to be enabled if the I2C subsystem was
enabled.  While this makes a reasonable amount of sense, it breaks
current assumptions for various testcases that we need to cleanup.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-10-22 22:05:37 -05:00
Andrew Boie
48af600a7a Revert "ARM: MPU: Arch specific memory domain APIs"
This reverts commit 7add3cdd82.
2017-10-20 15:02:59 -04:00
Andrew Boie
d7631ec7e4 Revert "x86: MMU: Memory domain implementation for x86"
This reverts commit d0f6ce2d98.
2017-10-20 15:02:59 -04:00
Andrew Boie
de777adf7b Revert "x86: MMU: Configure page tables entries for memory domain in swap."
This reverts commit a8b9353421.
2017-10-20 15:02:59 -04:00
Adithya Baglody
a8b9353421 x86: MMU: Configure page tables entries for memory domain in swap.
During swap the required page tables are configured. The outgoing
thread's memory domain pages are reset and the incoming thread's
memory domain is loaded. The pages are configured if userspace
is enabled and if memory domain has been initialized before
calling swap.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Adithya Baglody
d0f6ce2d98 x86: MMU: Memory domain implementation for x86
Added support for memory domain implementation.

GH-3852

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Adithya Baglody
7add3cdd82 ARM: MPU: Arch specific memory domain APIs
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-20 10:39:51 -07:00
Erwan Gouriou
da210ba0ba driver: serial: Move STM32 UART driver to LL API
STM32 UART driver was using a mix of LL/HAL APIs.  This commit removes
calls to HAL API and replaces them with LL APIs.  No functional change
have been seen during non regression testing.

But we could note a direct gain of 1Kb of ROM

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-10-20 12:28:11 -05:00
Yannis Damigos
a172f72d84 boards: stm32f3_disco: Add I2C support
Add I2C support to STM32F3DISCOVERY board

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-10-20 12:28:11 -05:00
Maureen Helm
6312b0e6a1 arm: Enable the mcux sim clock control driver on Kinetis SoCs
Because the mcux shim drivers will soon depend on a clock control
interface, enable the mcux sim clock control driver by default on all
Kinetis SoCs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-10-20 12:28:11 -05:00
Manivannan Sadhasivam
05e1d8c46a arch: arm: soc: ti_simplelink: Add MSP432P401R SoC
This patch adds SoC support for TI SimpleLink family MSP432P401R.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2017-10-19 12:16:11 -05:00
David B. Kinder
4600c37ff1 doc: Fix misspellings in header/doxygen comments
Occasional scan for misspellings missed during PR reviews

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-10-17 19:40:29 -04:00
Andrew Boie
c5c104f91e kernel: fix k_thread_stack_t definition
Currently this is defined as a k_thread_stack_t pointer.
However this isn't correct, stacks are defined as arrays. Extern
references to k_thread_stack_t doesn't work properly as the compiler
treats it as a pointer to the stack array and not the array itself.

Declaring as an unsized array of k_thread_stack_t doesn't work
well either. The least amount of confusion is to leave out the
pointer/array status completely, use pointers for function prototypes,
and define K_THREAD_STACK_EXTERN() to properly create an extern
reference.

The definitions for all functions and struct that use
k_thread_stack_t need to be updated, but code that uses them should
be unchanged.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-17 08:24:29 -07:00
Andrew Boie
094f2cb77b x86: fix crash in _x86_mmu_get_flags
Looking up the PTE flags was page faulting if the address wasn't
marked as present in the page directory, since there is no page table
for that directory entry.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-17 08:16:14 -07:00
Pushpal Sidhu
d5cf7e0912 arch: stm32f4: Add CONFIG_GPIO_STM32_PORTD=y
Default enable PD for all stm32f4 series

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2017-10-17 08:56:15 -05:00
Loic Poulain
8a11f91252 usb: Add support for STM32 family USB driver
This is a USB controller driver for STM32F4xx devices using
the STM32 Cube HAL_PCD framework. This has been tested with
the cdc_acm driver on a 96b_carbon board (STM32F401RE).

This is a refactoring of:
usb: usb_dc_stm: Add support for STM32Cube HAL_PCD USB driver
Signed-off-by: Christer Weinigel <christer@weinigel.se>
[daniel.thompson@linaro.org: Removed STM32F40(157) defconfig changes
together with STM32F4Discovery pinmux and defconfig changes, updated
clock settings and pad configuration to match latest mainline]
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[giannis.damigos@gmail.com: Change uint*_t types to u*_t types,
change SYS_LOG_USB_DC_STM_LEVEL to SYS_LOG_USB_DRIVER_LEVEL and
update pinmux to match latest arm branch]
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2017-10-17 09:14:47 -04:00
Yannis Damigos
1f0c6118d2 arch: stm32f4: Select USB_DC_STM32 driver if USB is enabled
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-10-17 09:14:47 -04:00
Andrew Boie
73a5fe77f8 x86: fix stack overflow in double fault handler
At very low optimization levels, the call to
K_THREAD_STACK_BUFFER doesn't get inlined, overflowing the
tiny stack.

Replace with _ARCH_THREAD_STACK_BUFFER() which on x86 is
just a macro.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-16 10:53:48 -07:00
Andrew Boie
da4024b1f7 Kconfig: CONFIG_USERSPACE is experimental
Indicate to users that this feature isn't fully baked yet.
This will be reverted for 1.11 release.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-13 13:40:21 -07:00
Andrew Boie
2b6abf6f89 kernel: USERSPACE implies HW_STACK_PROTECTION
Userspace is built on top of hardware stack protection and assumes
it is there. We can't enable this unless ARCH_HAS_USERSPACE is defined
anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-11 20:27:10 -04:00
Jonas Pfaff
b62a353551 drivers: adc: Add SAM ADC driver
Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-2507

Signed-off-by: Jonas Pfaff <jonas.pfaff@gmail.com>
2017-10-10 11:56:47 -05:00
Christian Taedcke
3959282359 arm: exx32: Add Silabs EFM32WG soc files
The Silicon Labs EFM32 Wonder Gecko MCU includes:

        * Cortex-M4F core at 48MHz
        * up to 256KB of flash and 32KB of RAM
        * USB with host and OTG support
        * multiple low power peripherals

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-10-10 11:56:47 -05:00
Johann Fischer
af1a8fc9f1 arch: nxp_kinetis: initial import KW2XD SiP
Jira: ZEP-1471

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-10-10 11:56:47 -05:00
Leandro Pereira
5f22dab17a esp32: Prefix ROM routines with esp32_rom_
Also provide their prototypes in `soc.h`.  This should help
readability, since some ROM functions, with their names as provided by
Espressif, have sometimes the same prefix as Zephyr APIs.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-10-09 20:53:22 -04:00
Andrew Boie
468190a795 kernel: convert most thread APIs to system calls
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-07 10:45:15 -07:00
Marti Bolivar
313b20d648 dfu: replace FLASH_ALIGN with FLASH_WRITE_BLOCK_SIZE
Use the define generated by the DTS instead of using the FLASH_ALIGN
alias. The latter is an internal mcuboot name. We shouldn't need it in
Zephyr itself.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
c38efa668c arm: soc: stm32l4: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
92e29680c1 arm: soc: stm32f4: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Marti Bolivar
2e6744f215 arm: soc: nxp: k6x: add flash driver for IMG_MANAGER
Add definition required to enable the DFU subsystem image manager.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-10-06 22:12:23 -04:00
Thiago Silveira
e11b9fb4e3 arm: soc: nRF52: Add workaround for incorrect RESETREAS bits, errata 136
This workaround fixes the issue that, after pin reset, RESETREAS bits
other than RESETPIN might also be set.

The workaround was added to both nRF52832 and nRF52840 SoCs.

Signed-off-by: Thiago Silveira <thiago@exati.com.br>
2017-10-06 22:11:21 -04:00
Paul Sokolovsky
808b315cf6 arm: nxp: kw41z: Select IEEE802154_KW41Z driver for networking
802.15.4 is the networking hardware available in KW41Z SoC (and
supported by Zephyr). So, if networking in enabled, automatically
select the corresponding driver. This is similar to how frdm_k64f
automatically selects Ethernet driver, 96b_carbon selects BLE/IPSP
drivers, etc. (But we apply it on SoC level to reuse across the
boards.)

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2017-10-06 14:39:17 -05:00
Savinay Dharmappa
58d54c0f2d dts: x86: qemu_x86: Add device support for uart ns16550
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-10-06 08:35:42 -04:00
Savinay Dharmappa
ddf6a69577 dts: x86: Add device tree support for qemu_x86
patch add device tree support for ia32 soc and qemu_x86
board port

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-10-06 08:35:42 -04:00
Andrew Boie
3e3a237930 x86: fix stack zeroing when dropping to user mode
For 'rep stosl' ECX isn't a size value, it's how many times to repeat
the 4-byte string copy operation.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-05 18:49:09 -04:00
David B. Kinder
f00f58517b doc: replace UTF-8 chars
Some our Zephyr tools don't like seeing UTF-8 characters, as reported in
issue #4131) so a quick scan and replace for UTF-8 characters in .rst,
.h, and Kconfig files using "file --mime-encoding" (excluding the /ext
folders) finds these files to tweak.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-10-03 20:03:57 -04:00
Anas Nashif
ae2e91155e arch: riscv32: define soc family in correct Kconfig
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-03 08:43:50 -04:00
Anas Nashif
be9a0b35ee arm: atmel: define soc family in correct Kconfig
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-03 08:43:50 -04:00
Chunlin Han
e9c9702818 kernel: add memory domain APIs
Add the following application-facing memory domain APIs:

k_mem_domain_init() - to initialize a memory domain
k_mem_domain_destroy() - to destroy a memory domain
k_mem_domain_add_partition() - to add a partition into a domain
k_mem_domain_remove_partition() - to remove a partition from a domain
k_mem_domain_add_thread() - to add a thread into a domain
k_mem_domain_remove_thread() - to remove a thread from a domain

A memory domain would contain some number of memory partitions.
A memory partition is a memory region (might be RAM, peripheral
registers, flash...) with specific attributes (access permission,
e.g. privileged read/write, unprivileged read-only, execute never...).
Memory partitions would be defined by set of MPU regions or MMU tables
underneath.
A thread could only belong to a single memory domain any point in time
but a memory domain could contain multiple threads.
Threads in the same memory domain would have the same access permission
to the memory partitions belong to the memory domain.

The memory domain APIs are used by unprivileged threads to share data
to the threads in the same memory and protect sensitive data from
threads outside their domain. It is not only for improving the security
but also useful for debugging (unexpected access would cause exception).

Jira: ZEP-2281

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-09-29 16:48:53 -07:00
Andrew Boie
13ca6fe284 syscalls: reorganize headers
- syscall.h now contains those APIs needed to support invoking calls
  from user code. Some stuff moved out of main kernel.h.
- syscall_handler.h now contains directives useful for implementing
  system call handler functions. This header is not pulled in by
  kernel.h and is intended to be used by C files implementing kernel
  system calls and driver subsystem APIs.
- syscall_list.h now contains the #defines for system call IDs. This
  list is expected to grow quite large so it is put in its own header.
  This is now an enumerated type instead of defines to make things
  easier as we introduce system calls over the new few months. In the
  fullness of time when we desire to have a fixed userspace/kernel ABI,
  this can always be converted to defines.

Some new code added:

- _SYSCALL_MEMORY() macro added to check memory regions passed up from
  userspace in handler functions
- _syscall_invoke{7...10}() inline functions declare for invoking system
  calls with more than 6 arguments. 10 was chosen as the limit as that
  corresponds to the largest arg list we currently have
  which is for k_thread_create()

Other changes

- auto-generated K_SYSCALL_DECLARE* macros documented
- _k_syscall_table in userspace.c is not a placeholder. There's no
  strong need to generate it and doing so would require the introduction
  of a third build phase.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-28 08:56:20 -07:00
Chunlin Han
95d28e53bb arch: arm: add initial support for CONFIG_USERSPACE
add related configs & (stub) functions for enabling
CONFIG_USERSPACE on arm w/o build errors.

Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
2017-09-26 10:00:53 -07:00
Maureen Helm
f0d50979e8 mcux: nxp_kinetis: Move HAS_TRNG config to ext
SoCs outside the Kinetis family can have the TRNG module, so move the
HAS_TRNG config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
5ba9f26b46 mcux: nxp_kinetis: Move HAS_RNGA config to ext
SoCs outside the Kinetis family can have the RNGA module, so move the
HAS_RNGA config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
694c7f5ca4 mcux: nxp_kinetis: Move HAS_FTM config to ext
SoCs outside the Kinetis family can have the FTM module, so move the
HAS_FTM config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Note that 'select HAS_FTM' was previously missing from Kconfig.soc and
is now fixed.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
f7a37cea8d mcux: nxp_kinetis: Move HAS_ADC16 config to ext
SoCs outside the Kinetis family can have the ADC16 module, so move the
HAS_ADC16 config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
fe4c3aacba mcux: nxp_kinetis: Move HAS_LPSCI config to ext
SoCs outside the Kinetis family can have the LPSCI module, so move the
HAS_LPSCI config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Maureen Helm
bbafc833db mcux: nxp_kinetis: Move HAS_LPUART config to ext
SoCs outside the Kinetis family can have the LPUART module, so move the
HAS_LPUART config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-09-25 12:31:59 -05:00
Anas Nashif
66f1f89da9 qemu: cleanup qemu configurations
Move all QEMU related defines to the boards and cleanup xtensa platforms
which were marked to be QEMU capable by mistake.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-23 16:51:20 -07:00
Andrew Boie
df5cc172f4 gen_mmu.py: load directly
On most workstations this was unintentionally being run under Python 2.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-21 13:27:25 -04:00
Anas Nashif
db4eba64da dfu: img_util: move flash defines to SoC
mcuboot_constraints.h had FLASH information related to the SoC that
should be maintained as part of the SoC and not in the subsystem. Also
fixed Makefiles to check for IMG_UTIL Kconfig and not MCUBOOT.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-21 06:46:27 -04:00
Andrew Boie
1956f09590 kernel: allow up to 6 arguments for system calls
A quick look at "man syscall" shows that in Linux, all architectures
support at least 6 argument system calls, with a few supporting 7. We
can at least do 6 in Zephyr.

x86 port modified to use EBP register to carry the 6th system call
argument.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-20 09:18:59 -07:00
Andrew Boie
a23c245a9a userspace: flesh out internal syscall interface
* Instead of a common system call entry function, we instead create a
table mapping system call ids to handler skeleton functions which are
invoked directly by the architecture code which receives the system
call.

* system call handler prototype specified. All but the most trivial
system calls will implement one of these. They validate all the
arguments, including verifying kernel/device object pointers, ensuring
that the calling thread has appropriate access to any memory buffers
passed in, and performing other parameter checks that the base system
call implementation does not check, or only checks with __ASSERT().

It's only possible to install a system call implementation directly
inside this table if the implementation has a return value and requires
no validation of any of its arguments.

A sample handler implementation for k_mutex_unlock() might look like:

u32_t _syscall_k_mutex_unlock(u32_t mutex_arg, u32_t arg2, u32_t arg3,
                              u32_t arg4, u32_t arg5, void *ssf)
{
        struct k_mutex *mutex = (struct k_mutex *)mutex_arg;
        _SYSCALL_ARG1;

        _SYSCALL_IS_OBJ(mutex, K_OBJ_MUTEX, 0,  ssf);
        _SYSCALL_VERIFY(mutex->lock_count > 0, ssf);
        _SYSCALL_VERIFY(mutex->owner == _current, ssf);

        k_mutex_unlock(mutex);

        return 0;
}

* the x86 port modified to work with the system call table instead of
calling a common handler function. fixed an issue where registers being
changed could confuse the compiler has been fixed; all registers, even
ones used for parameters, must be preserved across the system call.

* a new arch API for producing a kernel oops when validating system call
arguments added. The debug information reported will be from the system
call site and not inside the handler function.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-15 13:44:45 -07:00
Andrew Boie
424e993b41 x86: implement userspace APIs
- _arch_user_mode_enter() implemented
- _arch_is_user_context() implemented
- _new_thread() will honor K_USER option if passed in
- System call triggering macros implemented
- _thread_entry_wrapper moved and now looks for the next function to
call in EDI

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 12:46:36 -07:00
Andrew Boie
9f70c7b281 kernel: reorganize CONFIG_USERSPACE
This now depends on a capability Kconfig.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 12:46:36 -07:00
Anas Nashif
1e8afbfe5a cleanup: remove lots of references to unified kernel
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-12 12:37:11 -04:00
Andrew Boie
d81f9c1e4d x86: revise _x86_mmu_buffer_validate
- There's no point in building up "validity" (declared volatile for some
  strange reason), just exit with false return value if any of the page
  directory or page table checks don't come out as expected

- The function was returning the opposite value as its documentation
  (0 on success, -EPERM on failure). Documentation updated.

- This function will only be used to verify buffers from user-space.
  There's no need for a flags parameter, the only option that needs to
  be passed in is whether the buffer has write permissions or not.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 08:40:41 -07:00
Andrew Boie
3bb677d6eb x86: don't set FS/GS segment selectors
We shouldn't be imposing any policy here, we do not yet use these in
Zephyr. Zero these at boot and otherwise leave alone.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-12 08:40:08 -07:00
Erwan Gouriou
1ded7d7b33 arch: arm: stm32: factorize stm32f417xy socs defconfig files
stm32f417xe and stm32f417xg have been introduced with 2
different defconfig files. Since same code is declared
in both files, mutualize declarations in a single file.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-09-12 11:24:56 -04:00
Yannis Damigos
0f408a003c arch: soc: st_stm32: Remove unused enumeration from F4, F3 SoCs
The enumerations stm32{f3,f4}x_pin_config_mode aren't used any
more. This patch removes them.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-09-12 11:24:56 -04:00
Andrew Boie
1e06ffc815 zephyr: use k_thread_entry_t everywhere
In various places, a private _thread_entry_t, or the full prototype
were being used. Be consistent and use the same typedef everywhere.

Signen-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-11 11:18:22 -07:00
Anas Nashif
d414e7c7ee kconfig: move fatal error handler to arch options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
8379b7b433 kconfig: move interrupt options into arch menu
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
46f66f4295 kconfig: generalised stack protection options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
939889a202 kconfig: remove unused config DEBUG_IRQS
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
261f898e8f kconfig: remove exta menu for x86 core options
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 09:42:35 -07:00
Anas Nashif
7c71608fc1 cleanup: remove commented #include
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Anas Nashif
b1991eba94 cleanup: remove the whitespaces before the # character
Indenting preprocessor directives reduces the code readability, because
it make preprocessor directives harder to spot.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Anas Nashif
8920cf127a cleanup: Move #include directives
Move all #include directives at the very top of the file, before any
code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 12:41:07 -04:00
Marti Bolivar
32482e9cb8 flash: stm32: stm32f4: add page layout support
Add flash page layout support for STM32F4 SoCs.

This almost eliminates the need for flash_map.h, except for
STM32F4X_SECTOR_MASK, so delete the file and move the define into the
F4 implementation, to keep things simple.

Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
2017-09-11 11:41:57 -04:00
Adithya Baglody
609ade891b x86: MMU: Updated MMU code to use the new macros.
Use of X86_MMU_GET_PTE to increase readability of the MMU code.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-09-07 17:13:06 -07:00
Adithya Baglody
65c2432791 x86: MMU: Miscellaneous macros related to MMU.
Helper macros to ease the usage of the MMU page table structures.
Added Macros to get Page table address and Page Table Entry
values.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-09-07 17:13:06 -07:00
Andrew Boie
a34f4fb94f x86: add printk for protection faults
Most x86 exceptions that don't already have their own handlers
are fairly rare, but with the introduction of userspace
people will be seeing General Protection Faults much more
often. Report it as text so that users unfamiliar with x86
internals will know what is happening.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:35:27 -07:00
Andrew Boie
8eaff5d6d2 k_thread_abort(): assert if abort essential thread
Previously, this was only done if an essential thread self-exited,
and was a runtime check that generated a kernel panic.

Now if any thread has k_thread_abort() called on it, and that thread
is essential to the system operation, this check is made. It is now
an assertion.

_NANO_ERR_INVALID_TASK_EXIT checks and printouts removed since this
is now an assertion.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:35:16 -07:00
Andrew Boie
8eeb09765b x86: cleanup _new_thread()
Years of iterative development had made this function more complicated
than it needed to be. Fixed some errors in the documentation as well.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:33:50 -07:00
Andrew Boie
945af95f42 kernel: introduce object validation mechanism
All system calls made from userspace which involve pointers to kernel
objects (including device drivers) will need to have those pointers
validated; userspace should never be able to crash the kernel by passing
it garbage.

The actual validation with _k_object_validate() will be in the system
call receiver code, which doesn't exist yet.

- CONFIG_USERSPACE introduced. We are somewhat far away from having an
  end-to-end implementation, but at least need a Kconfig symbol to
  guard the incoming code with. Formal documentation doesn't exist yet
  either, but will appear later down the road once the implementation is
  mostly finalized.

- In the memory region for RAM, the data section has been moved last,
  past bss and noinit. This ensures that inserting generated tables
  with addresses of kernel objects does not change the addresses of
  those objects (which would make the table invalid)

- The DWARF debug information in the generated ELF binary is parsed to
  fetch the locations of all kernel objects and pass this to gperf to
  create a perfect hash table of their memory addresses.

- The generated gperf code doesn't know that we are exclusively working
  with memory addresses and uses memory inefficently. A post-processing
  script process_gperf.py adjusts the generated code before it is
  compiled to work with pointer values directly and not strings
  containing them.

- _k_object_init() calls inserted into the init functions for the set of
  kernel object types we are going to support so far

Issue: ZEP-2187
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-07 16:33:33 -07:00
Youvedeep Singh
7f2aaedfd7 arch: arm: store/restore regs r0-r3 while making function call.
In benchmark test (test_info) while making function call regs
r0 - r4 are modified into called function. Due to this value
inside r3 is getting lost.
This patch saves and restore the value in r0-r4 regs while making
function calls from assembly language.

Jira: ZEP-2314

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-08-31 14:25:31 -04:00
Youvedeep Singh
76b577e180 tests: benchmark: timing_info: Change API/variable Name.
The API/Variable names in timing_info looks very speicific to
platform (like systick etc), whereas these variabled are used
across platforms (nrf/arm/quark).
So this patch :-
1. changing API/Variable names to generic one.
2. Creating some of Macros whose implimentation is platform
depenent.

Jira: ZEP-2314

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
2017-08-31 14:25:31 -04:00
Andy Gross
ecb0f3e159 arm: mpu: Account for stack guard size correctly
This patch fixes a couple of issues with the stack guard size and
properly constructs the STACK_ALIGN and STACK_ALIGN_SIZE definitions.

The ARM AAPCS requires that the stack pointers be 8 byte aligned.  The
STACK_ALIGN_SIZE definition is meant to contain the stack pointer
alignment requirements.  This is the required alignment at public API
boundaries (ie stack frames).

The STACK_ALIGN definition is the required alignment for the start
address for stack buffer storage.  STACK_ALIGN is used to validate
the allocation sizes for stack buffers.

The MPU_GUARD_ALIGN_AND_SIZE definition is the minimum alignment and
size for the MPU.  The minimum size and alignment just so happen to be
32 bytes for vanilla ARM MPU implementations.

When defining stack buffers, the stack guard alignment requirements
must be taken into consideration when allocating the stack memory.
The __align() must be filled in with either STACK_ALIGN_SIZE or the
align/size of the MPU stack guard.  The align/size for the guard region
will be 0 when CONFIG_MPU_STACK_GUARD is not set, and 32 bytes when it
is.

The _ARCH_THREAD_STACK_XXXXXX APIs need to know the minimum alignment
requirements for the stack buffer memory and the stack guard size to
correctly allocate and reference the stack memory.  This is reflected
in the macros with the use of the STACK_ALIGN definition and the
MPU_GUARD_ALIGN_AND_SIZE definition.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-31 11:20:26 -05:00
Andy Gross
85481d997b arch: arm: Remove redundant check and fix rounding
This patch removes the redundant stack alignment check being done.  The
stack definition macros enforce the alignment requirements via the
__align() directives.

In addition, fix the rounding down of the psp to be correct.  The
actual initial stack pointer is the end of the stack minus the size of
the __esf structure.  Rounding down after the subtraction will get us
to the correct offset.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-31 11:20:26 -05:00
Leandro Pereira
510e5d7ced arch: xtensa: Use the alternate _Level4Vector routine on ESP32
For some reason, the ESP32 HAL defines XCHAL_EXCM_LEVEL to 3.  This
enables a version of _Level4Vector that doesn't work on this hardware.

Without complete visibility if the version that should work be axed,
keep both in the tree, but build the working other version instead
if building for ESP32.

Jira: ZEP-2556
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-25 15:31:46 -04:00
Kumar Gala
e25ee68bbd arch: arm: stm32f1: Fix how we determine pull-up/pull-down for gpio
When we mask out the GPIO High impedance/Pull-up/Pull-down field we
should be shifting the mask file, not shifting the field.  This is
because all the other defines already assume the shift.

Coverity-CID: 173640

Jira: ZEP-2538

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-08-21 11:18:03 -05:00
Leandro Pereira
d52de29fba esp32: Fix redefinition of BIT() macro
Esp-idf defines the BIT macro that is also defined in Zephyr's
misc/util.h.  Fix the issue by including the esp-idf headers first, so
that a check in util.h won't redefine the macro if it's already
defined.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-19 07:50:18 -04:00
David B. Kinder
81f7c82625 doc: fix misspellings and missing EOF newlines
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-08-16 17:38:41 -05:00
Wayne Ren
480cfac4f2 arch: arc: apply STACK_GUARD_SIZE and optimize the mpu driver
* apply STACK_GUARD_SIZE, no extra space will be added if
  MPU_STACK_GUARD is disabled
* When ARC_STACK_CHECKING is enabled, MPU_STACK_GUARD will be
  disabled
* add two new api: arc_core_mpu_default and arc_core_mpu_region
  to configure mpu regions
* improve arc_core_mpu_enable and arc_core_mpu_disable

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-08-16 16:09:45 -04:00
Wayne Ren
12cc6598b0 arch: arc: Add mpu support
* add arc mpu driver
* modify the corresponding kconfig and kbuild
* currently only em_starterkit 2.2's em7d configuration
  has mpu feature (mpu version 2)
* as the minimum region size of arc mpu version 2 is 2048 bytes and
  region size should be power of 2, the stack size of threads
  (including main thread and idle thread) should be at least
  2048 bytes and power of 2
* for mpu stack guard feature, a stack guard region of 2048 bytes
  is generated. This brings more memory footprint
* For arc mpu version 3, the minimum region size is 32 bytes.
* the codes are tested by the mpu_stack_guard_test and stackprot

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2017-08-16 16:09:45 -04:00
Andrew Boie
e434260e19 xtensa: soc: fix IRQ table
The linker scripts were not properly updated to the new
gen_isr_tables mechanism.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-16 10:59:10 -07:00
Gil Pitney
4f67a6c76d cc3200: Remove TI cc3200 SOC and LaunchXL board support
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."

Effectively, the CC3220 SOC replaces the CC3200.

This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.

Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-15 11:02:48 -05:00
Andrew Boie
de6663f601 esp32: fix linker script issues
- .text, .text.*, .literal, .literal.* had no matching input section
   rule and were being passed to the output binary verbatim. These
   are all now in the output "text" section as intended.

- various rules in the data section were unnecessarily using KEEP().

- SW_ISR_TABLE wasn't included in linker script anywhere and was
  ending up in its own section, and not the data section as intended.

- noinit section didn't exist at all, now defined.

Issue: ZEP-2508
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-14 15:27:17 -04:00
Andrew Boie
67a51f9a9e quark_d2000: fix IDT_LIST definition
This should be the same size as other x86 boards.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-14 14:45:07 -04:00
Gil Pitney
1a5537811f cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int
Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with
the NWP interrupt number of 171 caused a hard fault during a
subsequent svc #0 instruction during _Swap().

GNU compiler is generating a bit extension instruction (sxtb) which
converts a positive IRQ value argument to a negative value when
casting to the CMSIS IRQn_Type enum parameter type.

This generates a negative index, which then writes to an SCB
control register instead of NVIC register, causing a hard
fault later on.

This issue only occurs when passing interrupt numbers > 0x80
(eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis.

The solution here is simply to redefine IRQn_Type to be an
unsigned 32 bit integer, while redefining the CMSIS IRQn_Type
enum definitions for interrupts less than zero.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-10 16:46:49 -05:00
Wayne Ren
f8d061faf7 arch: arc: add nested interrupt support
* add nested interrupt support for interrupts
   + use a varibale exc_nest_count to trace nest interrupt and exception
   + regular interrupts can be nested by regular interrupts and fast
interrupts
   + fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
   + remove the coressponding kconfig option
   + all interrupts (normal and fast) and exceptions will be handled
     in the same stack (_interrupt stack)
   + the pros are, smaller memory footprint (no firq stack), simpler
     stack management, simpler codes, etc.. The cons are, possible
     10-15 instructions overhead for the case where fast irq nests
     regular irq
* add the case of ARC in test/kernel/gen_isr_table

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-10 12:47:15 -04:00
Huaqi Fang
725c525a13 boards: em_starterkit: Move peripheral configs from soc to board level
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
7ac0a6a9d1 arc: em7d: Report error when build for 2.3's em7d
When you build application for em starterkit 2.3 em7d, it will
report error during build since it is not supported currently.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
8dfefdf310 arc: em9d/em11d: Update default configurations
Update configurations to support em9d and em11d in
em starterkit 2.2 and 2.3

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
c58aadfece arc: em9d/em11d: Modify and cleanup soc.h
em starterkit has two versions, 2.2 and 2.3.
Change soc.h to support both versions,
main changes are the interrupt connections.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
403e2803bf arc: em7d: Clean up arch/arc/soc/em7d/soc.h
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
7a1f06b374 arc: em7d: Add support for em starterkit 2.2 EM7D
Since em starterkit has different firmware versions(2.2 and 2.3),
but the EM7D of 2.3 has new secureshield feature, which is not supported
in Zephyr, but EM7D of 2.2 is a normal EM core, which can be supported,
so we add support for 2.2 EM7D.

Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Huaqi Fang
d4e9c97173 arc: Remove unused backslash in makefile of arc em9d
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
2017-08-09 23:21:13 -04:00
Xiaorui Hu
eb48a0a73c arm: armv6-m: Support relocating vector table
An abnormal crash was encountered in ARMv6-M SoCs that don't have flash
starting at 0.  With Zephyr OS the reason for this crash is that, on
ARMv6-M the system requires an exception vector table at the 0 address.

We implement the relocate_vector_table function to move the vector table
code to address 0 on systems which don't have the start of code already
at 0.

[kumar.gala: reworderd commit message, tweaked how we check if we need
 to copy vector table]

Signed-off-by: Xiaorui Hu <xiaorui.hu@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-08-09 18:13:29 -04:00
Maureen Helm
469ddab780 pwm: Remove k64-specific driver and k20_sim.h
Now that we have an mcux shim driver, remove the old k64-specific
driver. Also remove include/drivers/k20_sim.h, since the old
k64-specific driver was the only thing left using it.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Maureen Helm
57bd281d4d nxp_kinetis: Switch default pwm driver to mcux
Switches the default pwm driver from the k64-specific driver to the
mcux shim, which can be used on other SoCs with the ftm peripheral.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Maureen Helm
060bf8ea6a pwm: Introduce new mcux ftm shim driver
Adds a shim layer around the mcux ftm driver to adapt it to the Zephyr
pwm interface.

Jira: ZEP-2025

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-09 18:13:29 -04:00
Erwin Rol
8e6ebdb090 arm: support for stm32f417 SOC
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-09 14:53:47 -05:00
Leandro Pereira
99181eb661 arch: xtensa: Move exception table to xtensa_intr.c
This cleans up the exception handling by removing the table declaration
from xtensa_intr_asm.S, and removing the unused
_xt_set_exception_handler() function.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
1e506d3b42 arch: xtensa: Remove mentions of dynamic interrupt settings
Dynamic IRQ allocation has been yanked from Zephyr a few releases ago,
so there's no point in keeping these options available.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Leandro Pereira
c0c79a8041 drivers: gpio: esp32: Add ESP32 GPIO driver
This provides basic GPIO support, with interrupts, and the ability to
read and write to ports on a pin-by-pin basis.

Jira: ZEP-2286
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Erwin Rol
57746488d4 arm: support for stm32f405 SOC
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-09 14:24:21 -05:00
Andy Gross
5930e9d02d arm: mpu: Adjust to use opaque kernel data types
This patch adjusts the ARM MPU implementation to be compliant to the
recent changes that introduced the opaque kernel data types.

Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-09 13:36:09 -05:00
Michel Jaouen
deeaa40e1e arm: mpu: fix: align stack for mpu stack guard
The mimimum mpu size is 32 bytes, but requires mpu base address to be
aligned on 32 bytes to work. Define architecture thread macro when
MPU_STACK_GUARD config to allocate stack with 32 more bytes.

Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
2017-08-09 13:36:09 -05:00
Yannis Damigos
0848843c04 arch: arm: stm32f1: Add missing input port configuration
This patch adds missing configuration bits when GPIO is
configured as input

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-08-09 10:11:51 -05:00
Yannis Damigos
a66b92459b arch: arm: stm32f1: Shift GPIO pin configuration values only once
In the stm32_gpio_flags_to_conf function the configuration
values of the GPIO pin are shifted two times. One in the
stm32-pinctrlf1 header and one in the function. This patch
removes one of those shifts.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2017-08-09 10:11:51 -05:00
Adithya Baglody
ab7b02ce67 x86: MMU: Bug in _x86_mmu_buffer_validate
The value of the PTE (starting_pte_num) was not
calulated correctly. If size of the buffer exceeded 4KB,
the buffer validation API was failing.

JIRA: ZEP-2489

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-08-09 07:06:22 -07:00
Johan Hedberg
2975ca0754 Bluetooth: Kconfig: Rename CONFIG_BLUETOOTH_* to CONFIG_BT_*
The API name space for Bluetooth is bt_* and BT_* so it makes sense to
align the Kconfig name space with this. The additional benefit is that
this also makes the names shorter. It is also in line with what Linux
uses for Bluetooth Kconfig entries.

Some Bluetooth-related Networking Kconfig defines are renamed as well
in order to be consistent, such as NET_L2_BLUETOOTH.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2017-08-09 11:14:19 +03:00
Vincenzo Frascino
de81c16c5a arm: core: mpu: Add Allow write on Flash
This patch adds the allow flash write CONFIG option to the ARM MPU
configuration in privileged mode.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
2017-08-08 11:20:46 -05:00
Vincenzo Frascino
6489b9a0f2 arm: soc: nxp k6x: Add Allow write on Flash
This patch adds the allow flash write CONFIG option to the NXP MPU
configuration in privileged mode.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
2017-08-08 11:20:46 -05:00
Youvedeep Singh
24e083c5d6 arm: handle time slicing before context switch on exception.
Currently Thread time slice is getting reset at end of timer
interrupt. Due to which equal priority threads behind current thread
in ready_q are not getting chance to run and leading to starvation.

This patch handles time slice in _ExcExit section context switch is
required.

Jira: ZEP-2444

Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-08 09:33:25 -04:00
Anas Nashif
09bcd8ee74 Kconfig: make all syslog variables depend on SYS_LOG
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-04 14:34:54 -05:00
Andrew Boie
80e82e7205 x86: stack overflow improvements
As luck would have it, the TSS for the main IA task has
all the information we need, populate an exception stack
frame with it.

The double-fault handler just stashes data and makes the main
hardware thread runnable again, and processing of the
exception continues from there.

We check the first byte before the faulting ESP value to see
if the stack pointer had run up to a non-present page, a sign
that this is a stack overflow and not a double fault for
some other reason.

Stack overflows in kernel mode are now recoverable for non-
essential threads, with the caveat that we hope we weren't in
a critical section updating kernel data structures when it
happened.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
25a8aef275 x86: enable MMU for application memory
Configuring the RAM/ROM regions will be the same for all
x86 targets as this is done with linker symbols.

Peripheral configuration left at the SOC level.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
0f16d98b32 x86: mmu: add runtime modification indicator
The CPU first checks the page directory entry for write
or user permissions on a particular page before looking
at the page table entry.

If a region configured all pages to be non user accessible,
and this was changed for a page within it to be accessible,
the PDE would not be updated and any access would still
return a page fault.

The least amount of runtime logic to deal with this is to
indicate at build time that some pages within a region may
be marked writable or user accessible at runtime, and to
pre-set the flags in the page directory entry accordingly.

The driving need for this is the region configuration for
kernel memory, which will have user permissions set at
runtime for stacks and user-configured memory domains.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Andrew Boie
9ffaaae5ad x86: additional debug output for page faults
Page faults will additionally dump out some interesting
page directory and page table flags for the faulting
memory address.

Intended to help determine whether the page tables have been
configured incorrectly as we enable memory protection features.

This only happens if CONFIG_EXCEPTION_DEBUG is turned on.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-03 11:46:26 -04:00
Erwin Rol
cf7765327b arch: arm: stm32: f3/f4/l4: write output speed to hardware register
The ouput speed of the gpio pins passed via the 'conf' argument was
ignored, causing the speed to always be in its reset state (lowest
possible speed for most pins). This was causing problems for pins that
actually need a speed faster than the default, like the ethernet
controller pins.

Combined with the correct pinmux configuration this fixes problems
of the olimex_stm32_e407 board not being able to send ethernet data.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>
2017-08-02 12:28:11 -05:00
Andrew Boie
507852a4ad kernel: introduce opaque data type for stacks
Historically, stacks were just character buffers and could be treated
as such if the user wanted to look inside the stack data, and also
declared as an array of the desired stack size.

This is no longer the case. Certain architectures will create a memory
region much larger to account for MPU/MMU guard pages. Unfortunately,
the kernel interfaces treat both the declared stack, and the valid
stack buffer within it as the same char * data type, even though these
absolutely cannot be used interchangeably.

We introduce an opaque k_thread_stack_t which gets instantiated by
K_THREAD_STACK_DECLARE(), this is no longer treated by the compiler
as a character pointer, even though it really is.

To access the real stack buffer within, the result of
K_THREAD_STACK_BUFFER() can be used, which will return a char * type.

This should catch a bunch of programming mistakes at build time:

- Declaring a character array outside of K_THREAD_STACK_DECLARE() and
  passing it to K_THREAD_CREATE
- Directly examining the stack created by K_THREAD_STACK_DECLARE()
  which is not actually the memory desired and may trigger a CPU
  exception

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-08-01 16:43:15 -07:00
Kumar Gala
68732efe00 arm: nxp: mcux lpuart: Get IRQ info from DTS
Move to using the generated IRQ defines from the DTS instead of soc.h.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-27 09:27:47 -05:00
Kumar Gala
0ef91e4d07 arm: nxp: mcux uart: Get IRQ info from DTS
Move to using the generated IRQ defines from the DTS instead of soc.h.
This change also fixes a minor bug in that the error irq priority wasn't
getting correctly picked up from device tree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-27 09:27:47 -05:00
Erwan Gouriou
72d2960741 arch: arm: stm32f3: Rework pinmux handler
STM32F3 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
8763939763 arch: arm: stm32f4: Rework pinmux handler
STM32F4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
8d0150000c arch: stm32f1: rework pinmux driver
Rework stm32f1 pinmux code for future dts based pinmux code
generation.
Pin configuration is now done directly thanks to gpio port
configuration. Reference to pseudo alternate functions are
now removed same as the use of pins[] array.
Pins function (uart tx for instance) is set implicitly by
defining gpio mode and configuration.
This behavior is specific to stm32f10x series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
2366d23573 arch: arm: stm32l4: Rework pinmux driver
STM32L4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed and information is transferred to
"pinconf" array

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 15:16:52 -05:00
Erwan Gouriou
92c7ef5939 arch: stm32: l4: factorize HAS_STM32CUBE
In L4 series, select HAS_STM32CUBE is done per soc.
This could be factorized in Kconfig.series.
Aim is  to lower the steps to add a new SoC.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2017-07-26 09:52:59 -05:00
Andrew Boie
d944950aaa x86: install guard page for interrupt stack
We need to know when the interrupt stack overflows as well as
thread stacks.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-26 05:57:45 -04:00
Kumar Gala
0e7067c6be arm: dts: cleanup uart related Kconfig options
Now that we generate BLUETOOTH_UART_ON_DEV_NAME, UART_PIPE_ON_DEV_NAME,
and BLUETOOTH_MONITOR_ON_DEV_NAME Kconfig defines for dts enabled
platforms add those into the appropriate dts files and remove from the
various board/Kconfig.defconfig files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-07-25 12:23:20 -05:00
Andrew Boie
054d47b29c x86: set stack guard page non-writable
This will trigger a page fault if the guard area
is written to. Since the exception itself will try
to write to the memory, a double fault will be triggered
and we will do an IA task switch to the df_tss and panic.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
0fab8a6dc5 x86: page-aligned stacks with guard page
Subsequent patches will set this guard page as unmapped,
triggering a page fault on access. If this is due to
stack overflow, a double fault will be triggered,
which we are now capable of handling with a switch to
a know good stack.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie
6101aa6220 x86: add API for modifying page tables
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00