arch: arm: cortex_r: Add ARCH_EXCEPT macro

With the addition of userspace support, Cortex-R needs to use SVC calls
to handle oops exceptions.  Add that support by defining ARCH_EXCEPT to
do a svc call.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>

arch/arm/core/aarch32/swap_helper.S

@@ -710,11 +710,15 @@ _context_switch:
     b z_arm_int_exit
 
 _oops:
-    push {r0, lr}
-    blx z_do_kernel_oops
-    pop {r0, lr}
-    cpsie i
-    movs pc, lr
+    /*
+     * Pass the exception frame to z_do_kernel_oops.  r0 contains the
+     * exception reason.
+     */
+    cps #MODE_SYS
+    mov r0, sp
+    cps #MODE_SVC
+    bl z_do_kernel_oops
+    b z_arm_int_exit
 
 #if defined(CONFIG_USERSPACE)
     /*

include/arch/arm/aarch32/error.h

@@ -54,7 +54,26 @@ do { \
 		: "memory"); \
 } while (false)
 #elif defined(CONFIG_ARMV7_R)
-/* Pick up the default definition in kernel.h for now */
+/*
+ * In order to support using svc for an exception while running in an
+ * isr, stack $lr_svc before calling svc.  While exiting the isr,
+ * z_check_stack_sentinel is called.  $lr_svc contains the return address.
+ * If the sentinel is wrong, it calls svc to cause an oops.  This svc
+ * call will overwrite $lr_svc, losing the return address from the
+ * z_check_stack_sentinel call if it is not stacked before the svc.
+ */
+#define ARCH_EXCEPT(reason_p) \
+register uint32_t r0 __asm__("r0") = reason_p; \
+do { \
+	__asm__ volatile ( \
+		"push {lr}\n\t" \
+		"cpsie i\n\t" \
+		"svc %[id]\n\t" \
+		"pop {lr}\n\t" \
+		: \
+		: "r" (r0), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
+		: "memory"); \
+} while (false)
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */