dts: bindings: sram: add SiFive dtim0 bindings
Add bindings for SiFive Data Tightly-Integrated Memory. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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/dts/bindings/*/openisa* @MaureenHelm
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/dts/bindings/*/st* @erwango
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/dts/bindings/sensor/ams* @alexanderwachter
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/dts/bindings/*/sifive* @mateusz-holenko @kgugala @pgielda @nategraff-sifive
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/ext/fs/ @nashif @wentongwu
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/ext/hal/atmel/asf/sam/include/same70*/ @aurel32
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/ext/hal/atmel/asf/sam0/include/samr21/ @benpicco
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27
dts/bindings/sram/sifive,dtim0.yaml
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27
dts/bindings/sram/sifive,dtim0.yaml
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#
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# Copyright (c) 2019 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: Data Tightly-Integrated Memory
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version: 0.1
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description: >
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This bindings describes the SiFive Data Tightly-Integrated Memory
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "sifive,dtim0"
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generation: define
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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...
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