michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: update stm32 i2s pll configuration

Browse source 
Add plli2s node to dts/overlay file for boards that already use I2S.
Remove old I2S Kconfig not used anymore

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2023-03-22 10:45:22 +01:00 • committed by Carles Cufí
commit fef5425379
6 changed files with 20 additions and 79 deletions
Download patch file Download diff file Expand all files Collapse all files

7
boards/arm/96b_argonkey/96b_argonkey.dts
View file

@ -65,6 +65,13 @@
status = "okay";
};
&plli2s {
div-m = <8>;
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;

17
boards/arm/96b_argonkey/Kconfig.defconfig
View file

@ -8,23 +8,6 @@ if BOARD_96B_ARGONKEY
config BOARD
default "96b_argonkey"
if I2S
# configure PLLI2S to generate a I2SxCLK=128MHz
config I2S_STM32_USE_PLLI2S_ENABLE
default y
config I2S_STM32_PLLI2S_PLLM
default 8
config I2S_STM32_PLLI2S_PLLN
default 192
config I2S_STM32_PLLI2S_PLLR
default 3
endif # I2S
if LSM6DSL
choice LSM6DSL_TRIGGER_MODE

7
boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts
View file

@ -69,6 +69,13 @@
status = "okay";
};
&plli2s {
div-m = <8>;
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;

17
boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig
View file

@ -8,23 +8,6 @@ if BOARD_96B_STM32_SENSOR_MEZ
config BOARD
default "96b_stm32_sensor_mez"
if I2S
# configure PLLI2S to generate a I2SxCLK=128MHz
config I2S_STM32_USE_PLLI2S_ENABLE
default y
config I2S_STM32_PLLI2S_PLLM
default 8
config I2S_STM32_PLLI2S_PLLN
default 192
config I2S_STM32_PLLI2S_PLLR
default 3
endif # I2S
config SPI_STM32_INTERRUPT
default y
depends on SPI

45
boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig
View file

@ -1,45 +0,0 @@
# Copyright (c) 2020 STMicroelectronics
#
# SPDX-License-Identifier: Apache-2.0
if BOARD_NUCLEO_F411RE
if I2S
# The I2S should be configured in such a way it generates a 2MHz
# clock to the MP34DT05 microphone.
#
# The input clock to I2S block is I2SClk. This clock is generated
# by the PLLI2S from either HSI or HSE osci using this formula:
#
# Fin = HSE or HSI osci
# Fvco = Fin x (PLLN/PLLM)
# I2SClk = Fvco / PLLR
#
# For example, if Fin is HSE at 8MHz and PLLM=8, PLLN=192, PLLR=3,
# the resulting I2SCLk is 64MHz. On the contrary if HSI at 16MHz is
# used the resulting I2SClk frequency would be 128MHz.
# The shield user is invited to verify which osci is configured on
# Nucleo F441RE board defconfig file and calculate the final frequency.
#
# The I2S block then uses I2SDIV and I2SODD register fields to further
# divide I2SClk. These parameters are automatically calculated by
# I2S driver, in order to obtain the requested output @2MHz, so
# having a I2SClk in input at 64MHz or 128MHz does not make a any
# difference.
config I2S_STM32_USE_PLLI2S_ENABLE
default y
config I2S_STM32_PLLI2S_PLLM
default 8
config I2S_STM32_PLLI2S_PLLN
default 192
config I2S_STM32_PLLI2S_PLLR
default 3
endif # I2S
endif # BOARD_NUCLEO_F411RE

6
boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay
View file

@ -4,6 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
&plli2s {
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&dma2 {
status = "okay";
};