soc: sensry: udma, pad renaming
Before that fix the names for UDMA could be misleading. With that fix the namespace is clear and easy to follow. Same applies for peripheral addresses and pad config. Signed-off-by: Sven Ginka <s.ginka@sensry.de>
This commit is contained in:
Sven Ginka
Anas Nashif
parent
795644f8f3
commit
fe4215462d
7 changed files with 301 additions and 290 deletions
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@ -6,39 +6,39 @@
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#ifndef GANYMED_SY1XX_PAD_CTRL_H
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#define GANYMED_SY1XX_PAD_CTRL_H
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#define PAD_CONFIG(pin_offset, SMT, SLEW, PULLUP, PULLDOWN, DRV, PMOD, DIR) \
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#define SY1XX_PAD_CONFIG(pin_offset, SMT, SLEW, PULLUP, PULLDOWN, DRV, PMOD, DIR) \
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(((SMT << 7) | (SLEW << 6) | (PULLUP << 5) | (PULLDOWN << 4) | (DRV << 2) | (PMOD << 1) | \
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DIR) \
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<< pin_offset)
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#define PAD_CONFIG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET)
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#define SY1XX_PAD_CONFIG_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_APB_SOC_CTRL_OFFSET)
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#define PAD_CONFIG_ADDR_UART (PAD_CONFIG_ADDR + 0x020)
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#define PAD_CONFIG_ADDR_SPI (PAD_CONFIG_ADDR + 0x02c)
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#define PAD_CONFIG_ADDR_I2C (PAD_CONFIG_ADDR + 0x100)
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#define PAD_CONFIG_ADDR_MAC (PAD_CONFIG_ADDR + 0x130)
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#define SY1XX_PAD_CONFIG_ADDR_UART (SY1XX_PAD_CONFIG_ADDR + 0x020)
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#define SY1XX_PAD_CONFIG_ADDR_SPI (SY1XX_PAD_CONFIG_ADDR + 0x02c)
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#define SY1XX_PAD_CONFIG_ADDR_I2C (SY1XX_PAD_CONFIG_ADDR + 0x100)
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#define SY1XX_PAD_CONFIG_ADDR_MAC (SY1XX_PAD_CONFIG_ADDR + 0x130)
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#define PAD_SMT_DISABLE 0
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#define PAD_SMT_ENABLE 1
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#define SY1XX_PAD_SMT_DISABLE 0
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#define SY1XX_PAD_SMT_ENABLE 1
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#define PAD_SLEW_LOW 0
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#define PAD_SLEW_HIGH 1
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#define SY1XX_PAD_SLEW_LOW 0
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#define SY1XX_PAD_SLEW_HIGH 1
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#define PAD_PULLUP_DIS 0
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#define PAD_PULLUP_EN 1
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#define SY1XX_PAD_PULLUP_DIS 0
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#define SY1XX_PAD_PULLUP_EN 1
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#define PAD_PULLDOWN_DIS 0
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#define PAD_PULLDOWN_EN 1
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#define SY1XX_PAD_PULLDOWN_DIS 0
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#define SY1XX_PAD_PULLDOWN_EN 1
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#define PAD_DRIVE_2PF 0
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#define PAD_DRIVE_4PF 1
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#define PAD_DRIVE_8PF 2
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#define PAD_DRIVE_16PF 3
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#define SY1XX_PAD_DRIVE_2PF 0
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#define SY1XX_PAD_DRIVE_4PF 1
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#define SY1XX_PAD_DRIVE_8PF 2
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#define SY1XX_PAD_DRIVE_16PF 3
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#define PAD_PMOD_NORMAL 0
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#define PAD_PMOD_TRISTATE 1
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#define SY1XX_PAD_PMOD_NORMAL 0
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#define SY1XX_PAD_PMOD_TRISTATE 1
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#define PAD_DIR_OUTPUT 0
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#define PAD_DIR_INPUT 1
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#define SY1XX_PAD_DIR_OUTPUT 0
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#define SY1XX_PAD_DIR_INPUT 1
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#endif /* GANYMED_SY1XX_PAD_CTRL_H */
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@ -15,33 +15,33 @@ LOG_MODULE_REGISTER(soc);
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#include "soc.h"
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/* ITC */
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#define ARCHI_ITC_MASK_OFFSET 0x0
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#define ARCHI_ITC_MASK_SET_OFFSET 0x4
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#define ARCHI_ITC_MASK_CLR_OFFSET 0x8
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#define ARCHI_ITC_STATUS_OFFSET 0xc
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#define ARCHI_ITC_STATUS_SET_OFFSET 0x10
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#define ARCHI_ITC_STATUS_CLR_OFFSET 0x14
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#define ARCHI_ITC_ACK_OFFSET 0x18
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#define ARCHI_ITC_ACK_SET_OFFSET 0x1c
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#define ARCHI_ITC_ACK_CLR_OFFSET 0x20
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#define ARCHI_ITC_FIFO_OFFSET 0x24
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#define SY1XX_ARCHI_ITC_MASK_OFFSET 0x0
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#define SY1XX_ARCHI_ITC_MASK_SET_OFFSET 0x4
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#define SY1XX_ARCHI_ITC_MASK_CLR_OFFSET 0x8
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#define SY1XX_ARCHI_ITC_STATUS_OFFSET 0xc
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#define SY1XX_ARCHI_ITC_STATUS_SET_OFFSET 0x10
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#define SY1XX_ARCHI_ITC_STATUS_CLR_OFFSET 0x14
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#define SY1XX_ARCHI_ITC_ACK_OFFSET 0x18
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#define SY1XX_ARCHI_ITC_ACK_SET_OFFSET 0x1c
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#define SY1XX_ARCHI_ITC_ACK_CLR_OFFSET 0x20
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#define SY1XX_ARCHI_ITC_FIFO_OFFSET 0x24
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void sys_arch_reboot(int type)
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{
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ARG_UNUSED(type);
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}
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#define ARCHI_REF_CLOCK (32768)
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#define ARCHI_PER_CLOCK (125000000)
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#define SY1XX_ARCHI_REF_CLOCK (32768)
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#define SY1XX_ARCHI_PER_CLOCK (125000000)
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uint32_t soc_get_rts_clock_frequency(void)
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uint32_t sy1xx_soc_get_rts_clock_frequency(void)
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{
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return ARCHI_REF_CLOCK;
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return SY1XX_ARCHI_REF_CLOCK;
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}
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uint32_t soc_get_peripheral_clock(void)
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uint32_t sy1xx_soc_get_peripheral_clock(void)
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{
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return ARCHI_PER_CLOCK;
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return SY1XX_ARCHI_PER_CLOCK;
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}
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void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)
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@ -51,17 +51,18 @@ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)
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void soc_enable_irq(uint32_t idx)
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{
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uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET);
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uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
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sys_write32(current | (1 << (idx & 0x1f)), ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET);
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sys_write32(current | (1 << (idx & 0x1f)),
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SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET);
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}
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void soc_disable_irq(uint32_t idx)
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{
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uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET);
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uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
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sys_write32(current & (~(1 << (idx & 0x1f))),
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ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET);
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SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET);
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}
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/*
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@ -82,10 +83,10 @@ void soc_interrupt_init(void)
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*
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* @return 0
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*/
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static int soc_sy1xx_init(void)
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static int sy1xx_soc_init(void)
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{
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return 0;
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}
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SYS_INIT(soc_sy1xx_init, PRE_KERNEL_1, 0);
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SYS_INIT(sy1xx_soc_init, PRE_KERNEL_1, 0);
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@ -12,33 +12,34 @@
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/* SOC PERIPHERALS */
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#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000
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#define SY1XX_ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000
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#define ARCHI_GPIO_OFFSET 0x00001000
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#define ARCHI_UDMA_OFFSET 0x00002000
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#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000
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#define ARCHI_SOC_EU_OFFSET 0x00006000
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#define ARCHI_FC_ITC_OFFSET 0x00009800
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#define ARCHI_FC_TIMER_OFFSET 0x0000B000
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#define ARCHI_STDOUT_OFFSET 0x0000F000
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#define SY1XX_ARCHI_GPIO_OFFSET 0x00001000
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#define SY1XX_ARCHI_UDMA_OFFSET 0x00002000
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#define SY1XX_ARCHI_APB_SOC_CTRL_OFFSET 0x00004000
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#define SY1XX_ARCHI_SOC_EU_OFFSET 0x00006000
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#define SY1XX_ARCHI_FC_ITC_OFFSET 0x00009800
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#define SY1XX_ARCHI_FC_TIMER_OFFSET 0x0000B000
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#define SY1XX_ARCHI_STDOUT_OFFSET 0x0000F000
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#define ARCHI_GPIO_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET)
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#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET)
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#define ARCHI_APB_SOC_CTRL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET)
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#define ARCHI_SOC_EU_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET)
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#define ARCHI_FC_ITC_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET)
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#define ARCHI_FC_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET)
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#define ARCHI_STDOUT_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET)
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#define SY1XX_ARCHI_GPIO_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_GPIO_OFFSET)
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#define SY1XX_ARCHI_UDMA_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_UDMA_OFFSET)
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#define SY1XX_ARCHI_APB_SOC_CTRL_ADDR \
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(SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_APB_SOC_CTRL_OFFSET)
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#define SY1XX_ARCHI_SOC_EU_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_SOC_EU_OFFSET)
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#define SY1XX_ARCHI_FC_ITC_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_FC_ITC_OFFSET)
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#define SY1XX_ARCHI_FC_TIMER_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_FC_TIMER_OFFSET)
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#define SY1XX_ARCHI_STDOUT_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_STDOUT_OFFSET)
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#define ARCHI_PLL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR)
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#define ARCHI_SECURE_MRAM_CTRL_ADDR 0x1D180000
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#define ARCHI_GLOBAL_MRAM_CTRL_ADDR 0x1E080000
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#define ARCHI_MRAM_EFUSE_ADDR 0x1D070100
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#define ARCHI_TSN_ADDR 0x1A120000
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#define ARCHI_CAN_ADDR 0x1A130000
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#define SY1XX_ARCHI_PLL_ADDR (SY1XX_ARCHI_SOC_PERIPHERALS_ADDR)
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#define SY1XX_ARCHI_SECURE_MRAM_CTRL_ADDR 0x1D180000
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#define SY1XX_ARCHI_GLOBAL_MRAM_CTRL_ADDR 0x1E080000
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#define SY1XX_ARCHI_MRAM_EFUSE_ADDR 0x1D070100
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#define SY1XX_ARCHI_TSN_ADDR 0x1A120000
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#define SY1XX_ARCHI_CAN_ADDR 0x1A130000
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uint32_t soc_get_rts_clock_frequency(void);
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uint32_t soc_get_peripheral_clock(void);
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uint32_t sy1xx_soc_get_rts_clock_frequency(void);
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uint32_t sy1xx_soc_get_peripheral_clock(void);
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void soc_enable_irq(uint32_t idx);
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void soc_disable_irq(uint32_t idx);
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@ -6,98 +6,98 @@
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#include "soc.h"
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#include "udma.h"
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#define UDMA_CTRL_PER_CG (ARCHI_UDMA_ADDR + UDMA_CONF_OFFSET)
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#define SY1XX_UDMA_CTRL_PER_CG (SY1XX_ARCHI_UDMA_ADDR + SY1XX_UDMA_CONF_OFFSET)
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#define DRIVERS_MAX_UART_COUNT 3
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#define DRIVERS_MAX_I2C_COUNT 4
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#define DRIVERS_MAX_SPI_COUNT 7
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#define DEVICE_MAX_ETH_COUNT 1
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#define SY1XX_MAX_UART_COUNT 3
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#define SY1XX_MAX_I2C_COUNT 4
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#define SY1XX_MAX_SPI_COUNT 7
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#define SY1XX_MAX_ETH_COUNT 1
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void drivers_udma_enable_clock(udma_module_t module, uint32_t instance)
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void sy1xx_udma_enable_clock(sy1xx_udma_module_t module, uint32_t instance)
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{
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uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG);
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uint32_t udma_ctrl_per_cg = sys_read32(SY1XX_UDMA_CTRL_PER_CG);
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switch (module) {
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case DRIVERS_UDMA_UART:
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if (instance >= DRIVERS_MAX_UART_COUNT) {
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case SY1XX_UDMA_MODULE_UART:
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if (instance >= SY1XX_MAX_UART_COUNT) {
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return;
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}
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udma_ctrl_per_cg |= 1 << (instance + 0);
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break;
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case DRIVERS_UDMA_I2C:
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if (instance >= DRIVERS_MAX_I2C_COUNT) {
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case SY1XX_UDMA_MODULE_I2C:
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if (instance >= SY1XX_MAX_I2C_COUNT) {
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return;
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}
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udma_ctrl_per_cg |= 1 << (instance + 10);
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break;
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case DRIVERS_UDMA_SPI:
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if (instance >= DRIVERS_MAX_SPI_COUNT) {
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case SY1XX_UDMA_MODULE_SPI:
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if (instance >= SY1XX_MAX_SPI_COUNT) {
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return;
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}
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udma_ctrl_per_cg |= 1 << (instance + 3);
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break;
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case DRIVERS_UDMA_MAC:
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if (instance >= DEVICE_MAX_ETH_COUNT) {
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case SY1XX_UDMA_MODULE_MAC:
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if (instance >= SY1XX_MAX_ETH_COUNT) {
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return;
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}
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udma_ctrl_per_cg |= 1 << (instance + 20);
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break;
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case DRIVERS_MAX_UDMA_COUNT:
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case SY1XX_UDMA_MAX_MODULE_COUNT:
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break;
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}
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sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG);
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sys_write32(udma_ctrl_per_cg, SY1XX_UDMA_CTRL_PER_CG);
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}
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void drivers_udma_disable_clock(udma_module_t module, uint32_t instance)
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void sy1xx_udma_disable_clock(sy1xx_udma_module_t module, uint32_t instance)
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{
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uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG);
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uint32_t udma_ctrl_per_cg = sys_read32(SY1XX_UDMA_CTRL_PER_CG);
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switch (module) {
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case DRIVERS_UDMA_UART:
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if (instance >= DRIVERS_MAX_UART_COUNT) {
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case SY1XX_UDMA_MODULE_UART:
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if (instance >= SY1XX_MAX_UART_COUNT) {
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return;
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}
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udma_ctrl_per_cg &= ~(1 << (instance + 0));
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break;
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case DRIVERS_UDMA_I2C:
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if (instance >= DRIVERS_MAX_I2C_COUNT) {
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case SY1XX_UDMA_MODULE_I2C:
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if (instance >= SY1XX_MAX_I2C_COUNT) {
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return;
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}
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udma_ctrl_per_cg &= ~(1 << (instance + 10));
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break;
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case DRIVERS_UDMA_SPI:
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if (instance >= DRIVERS_MAX_SPI_COUNT) {
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case SY1XX_UDMA_MODULE_SPI:
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if (instance >= SY1XX_MAX_SPI_COUNT) {
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return;
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}
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udma_ctrl_per_cg &= ~(1 << (instance + 3));
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break;
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case DRIVERS_UDMA_MAC:
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if (instance >= DEVICE_MAX_ETH_COUNT) {
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case SY1XX_UDMA_MODULE_MAC:
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if (instance >= SY1XX_MAX_ETH_COUNT) {
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return;
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}
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udma_ctrl_per_cg &= ~(1 << (instance + 20));
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break;
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case DRIVERS_MAX_UDMA_COUNT:
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case SY1XX_UDMA_MAX_MODULE_COUNT:
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break;
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}
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sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG);
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sys_write32(udma_ctrl_per_cg, SY1XX_UDMA_CTRL_PER_CG);
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}
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void drivers_udma_busy_delay(uint32_t msec)
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void sy1xx_udma_busy_delay(uint32_t msec)
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{
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uint32_t sec = 250000000;
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uint32_t millis = (sec / 1000) * msec;
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@ -107,32 +107,35 @@ void drivers_udma_busy_delay(uint32_t msec)
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}
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}
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int32_t drivers_udma_cancel(uint32_t base, uint32_t channel)
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int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel)
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{
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uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
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/* clear existing */
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UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_CLEAR);
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SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_CFG_REG + channel_offset,
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SY1XX_UDMA_CHANNEL_CFG_CLEAR);
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return 0;
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}
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int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel)
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int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel)
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{
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uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
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int32_t isBusy = UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN);
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int32_t isBusy = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) &
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(SY1XX_UDMA_CHANNEL_CFG_EN);
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return isBusy ? 0 : 1;
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}
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int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel)
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int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel)
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{
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uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
volatile uint32_t timeout = 200;
|
||||
|
||||
while (UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN)) {
|
||||
drivers_udma_busy_delay(1);
|
||||
while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + channel_offset) &
|
||||
(SY1XX_UDMA_CHANNEL_CFG_EN)) {
|
||||
sy1xx_udma_busy_delay(1);
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
|
|
@ -142,13 +145,13 @@ int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_wait_for_status(uint32_t base)
|
||||
int32_t sy1xx_udma_wait_for_status(uint32_t base)
|
||||
{
|
||||
|
||||
volatile uint32_t timeout = 200;
|
||||
|
||||
while (UDMA_READ_REG(base, UDMA_STATUS) & (0x3)) {
|
||||
drivers_udma_busy_delay(1);
|
||||
while (SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_STATUS) & (0x3)) {
|
||||
sy1xx_udma_busy_delay(1);
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
|
|
@ -158,23 +161,24 @@ int32_t drivers_udma_wait_for_status(uint32_t base)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg)
|
||||
int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
UDMA_WRITE_REG(base, UDMA_SADDR_REG + channel_offset, saddr);
|
||||
UDMA_WRITE_REG(base, UDMA_SIZE_REG + channel_offset, size);
|
||||
UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_EN | optional_cfg);
|
||||
SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_SADDR_REG + channel_offset, saddr);
|
||||
SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_SIZE_REG + channel_offset, size);
|
||||
SY1XX_UDMA_WRITE_REG(base, SY1XX_UDMA_CFG_REG + channel_offset,
|
||||
SY1XX_UDMA_CHANNEL_CFG_EN | optional_cfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel)
|
||||
int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
int32_t size = UDMA_READ_REG(base, UDMA_SIZE_REG + channel_offset);
|
||||
int32_t size = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_SIZE_REG + channel_offset);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,21 +11,20 @@
|
|||
#include <soc.h>
|
||||
|
||||
/* UDMA */
|
||||
#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET)
|
||||
|
||||
#define UDMA_PERIPH_AREA_SIZE_LOG2 7
|
||||
#define UDMA_PERIPH_OFFSET(id) (((id) << UDMA_PERIPH_AREA_SIZE_LOG2))
|
||||
#define SY1XX_UDMA_PERIPH_AREA_SIZE_LOG2 7
|
||||
#define SY1XX_UDMA_PERIPH_OFFSET(id) (((id) << SY1XX_UDMA_PERIPH_AREA_SIZE_LOG2))
|
||||
|
||||
#define ARCHI_UDMA_UART_ID(id) (0 + (id))
|
||||
#define ARCHI_UDMA_SPIM_ID(id) (3 + (id))
|
||||
#define ARCHI_UDMA_I2C_ID(id) (10 + (id))
|
||||
#define ARCHI_UDMA_I2S_ID(id) (14 + (id))
|
||||
#define ARCHI_UDMA_HYPER_ID(id) (19 + (id))
|
||||
#define ARCHI_UDMA_TSN_ID(id) (20 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_UART_ID(id) (0 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_SPIM_ID(id) (3 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_I2C_ID(id) (10 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_I2S_ID(id) (14 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_HYPER_ID(id) (19 + (id))
|
||||
#define SY1XX_ARCHI_UDMA_TSN_ID(id) (20 + (id))
|
||||
|
||||
#define UDMA_CHANNEL_RX_OFFSET 0x00
|
||||
#define UDMA_CHANNEL_TX_OFFSET 0x10
|
||||
#define UDMA_CHANNEL_CUSTOM_OFFSET 0x20
|
||||
#define SY1XX_UDMA_CHANNEL_RX_OFFSET 0x00
|
||||
#define SY1XX_UDMA_CHANNEL_TX_OFFSET 0x10
|
||||
#define SY1XX_UDMA_CHANNEL_CUSTOM_OFFSET 0x20
|
||||
|
||||
/*
|
||||
* For each channel, the RX and TX part have the following registers
|
||||
|
|
@ -33,119 +32,119 @@
|
|||
*/
|
||||
|
||||
/* Start address register */
|
||||
#define UDMA_CHANNEL_SADDR_OFFSET 0x0
|
||||
#define SY1XX_UDMA_CHANNEL_SADDR_OFFSET 0x0
|
||||
/* Size register */
|
||||
#define UDMA_CHANNEL_SIZE_OFFSET 0x4
|
||||
#define SY1XX_UDMA_CHANNEL_SIZE_OFFSET 0x4
|
||||
/* Configuration register */
|
||||
#define UDMA_CHANNEL_CFG_OFFSET 0x8
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_OFFSET 0x8
|
||||
/* Int configuration register */
|
||||
#define UDMA_CHANNEL_INTCFG_OFFSET 0xC
|
||||
#define SY1XX_UDMA_CHANNEL_INTCFG_OFFSET 0xC
|
||||
|
||||
/*
|
||||
* The configuration register of the RX and TX parts for each channel can be accessed using the
|
||||
* following bits
|
||||
*/
|
||||
|
||||
#define UDMA_CHANNEL_CFG_SHADOW_BIT (5)
|
||||
#define UDMA_CHANNEL_CFG_CLEAR_BIT (5)
|
||||
#define UDMA_CHANNEL_CFG_EN_BIT (4)
|
||||
#define UDMA_CHANNEL_CFG_SIZE_BIT (1)
|
||||
#define UDMA_CHANNEL_CFG_CONT_BIT (0)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SHADOW_BIT (5)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_CLEAR_BIT (5)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_EN_BIT (4)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SIZE_BIT (1)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_CONT_BIT (0)
|
||||
|
||||
/* Indicates if a shadow transfer is there */
|
||||
#define UDMA_CHANNEL_CFG_SHADOW (1 << UDMA_CHANNEL_CFG_SHADOW_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SHADOW (1 << SY1XX_UDMA_CHANNEL_CFG_SHADOW_BIT)
|
||||
/* Stop and clear all pending transfers */
|
||||
#define UDMA_CHANNEL_CFG_CLEAR (1 << UDMA_CHANNEL_CFG_CLEAR_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_CLEAR (1 << SY1XX_UDMA_CHANNEL_CFG_CLEAR_BIT)
|
||||
/* Start a transfer */
|
||||
#define UDMA_CHANNEL_CFG_EN (1 << UDMA_CHANNEL_CFG_EN_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_EN (1 << SY1XX_UDMA_CHANNEL_CFG_EN_BIT)
|
||||
/* Configure for 8-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_8 (0 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SIZE_8 (0 << SY1XX_UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for 16-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_16 (1 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SIZE_16 (1 << SY1XX_UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for 32-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_32 (2 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_SIZE_32 (2 << SY1XX_UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for continuous mode */
|
||||
#define UDMA_CHANNEL_CFG_CONT (1 << UDMA_CHANNEL_CFG_CONT_BIT)
|
||||
#define SY1XX_UDMA_CHANNEL_CFG_CONT (1 << SY1XX_UDMA_CHANNEL_CFG_CONT_BIT)
|
||||
|
||||
/* Configuration area offset */
|
||||
#define UDMA_CONF_OFFSET 0xF80
|
||||
#define SY1XX_UDMA_CONF_OFFSET 0xF80
|
||||
/* Clock-gating control register */
|
||||
#define UDMA_CONF_CG_OFFSET 0x00
|
||||
#define SY1XX_UDMA_CONF_CG_OFFSET 0x00
|
||||
|
||||
static inline void plp_udma_cg_set(unsigned int value)
|
||||
{
|
||||
sys_write32(value, ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET +
|
||||
UDMA_CONF_CG_OFFSET);
|
||||
sys_write32(value, SY1XX_ARCHI_SOC_PERIPHERALS_ADDR + SY1XX_ARCHI_UDMA_OFFSET +
|
||||
SY1XX_UDMA_CONF_OFFSET + SY1XX_UDMA_CONF_CG_OFFSET);
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
DRIVERS_UDMA_UART,
|
||||
DRIVERS_UDMA_I2C,
|
||||
DRIVERS_UDMA_SPI,
|
||||
DRIVERS_UDMA_MAC,
|
||||
DRIVERS_MAX_UDMA_COUNT
|
||||
} udma_module_t;
|
||||
SY1XX_UDMA_MODULE_UART,
|
||||
SY1XX_UDMA_MODULE_I2C,
|
||||
SY1XX_UDMA_MODULE_SPI,
|
||||
SY1XX_UDMA_MODULE_MAC,
|
||||
SY1XX_UDMA_MAX_MODULE_COUNT
|
||||
} sy1xx_udma_module_t;
|
||||
|
||||
void drivers_udma_enable_clock(udma_module_t module, uint32_t instance);
|
||||
void drivers_udma_disable_clock(udma_module_t module, uint32_t instance);
|
||||
void sy1xx_udma_enable_clock(sy1xx_udma_module_t module, uint32_t instance);
|
||||
void sy1xx_drivers_udma_disable_clock(sy1xx_udma_module_t module, uint32_t instance);
|
||||
|
||||
int32_t drivers_udma_cancel(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_wait_for_status(uint32_t base);
|
||||
int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg);
|
||||
int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel);
|
||||
int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel);
|
||||
int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel);
|
||||
int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel);
|
||||
int32_t sy1xx_udma_wait_for_status(uint32_t base);
|
||||
int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg);
|
||||
int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel);
|
||||
|
||||
typedef enum {
|
||||
UDMA_SADDR_REG = 0x00,
|
||||
UDMA_SIZE_REG = 0x04,
|
||||
UDMA_CFG_REG = 0x08,
|
||||
SY1XX_UDMA_SADDR_REG = 0x00,
|
||||
SY1XX_UDMA_SIZE_REG = 0x04,
|
||||
SY1XX_UDMA_CFG_REG = 0x08,
|
||||
|
||||
} udma_regs_t;
|
||||
|
||||
typedef enum {
|
||||
UDMA_RX_SADDR_REG = 0x00,
|
||||
UDMA_RX_SIZE_REG = 0x04,
|
||||
UDMA_RX_CFG_REG = 0x08,
|
||||
SY1XX_UDMA_RX_SADDR_REG = 0x00,
|
||||
SY1XX_UDMA_RX_SIZE_REG = 0x04,
|
||||
SY1XX_UDMA_RX_CFG_REG = 0x08,
|
||||
|
||||
UDMA_TX_SADDR_REG = 0x10,
|
||||
UDMA_TX_SIZE_REG = 0x14,
|
||||
UDMA_TX_CFG_REG = 0x18,
|
||||
SY1XX_UDMA_TX_SADDR_REG = 0x10,
|
||||
SY1XX_UDMA_TX_SIZE_REG = 0x14,
|
||||
SY1XX_UDMA_TX_CFG_REG = 0x18,
|
||||
|
||||
UDMA_STATUS = 0x20,
|
||||
UDMA_SETUP_REG = 0x24,
|
||||
SY1XX_UDMA_STATUS = 0x20,
|
||||
SY1XX_UDMA_SETUP_REG = 0x24,
|
||||
} udma_reg_t;
|
||||
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_8 (0x0 << 1)
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_16 (0x1 << 1)
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_32 (0x2 << 1)
|
||||
#define SY1XX_UDMA_RX_DATA_ADDR_INC_SIZE_8 (0x0 << 1)
|
||||
#define SY1XX_UDMA_RX_DATA_ADDR_INC_SIZE_16 (0x1 << 1)
|
||||
#define SY1XX_UDMA_RX_DATA_ADDR_INC_SIZE_32 (0x2 << 1)
|
||||
|
||||
#define UDMA_RX_CHANNEL 0
|
||||
#define UDMA_TX_CHANNEL 1
|
||||
#define SY1XX_UDMA_RX_CHANNEL 0
|
||||
#define SY1XX_UDMA_TX_CHANNEL 1
|
||||
|
||||
#define UDMA_READ_REG(udma_base, reg) sys_read32(udma_base + reg)
|
||||
#define UDMA_WRITE_REG(udma_base, reg, value) sys_write32(value, udma_base + reg)
|
||||
#define SY1XX_UDMA_READ_REG(udma_base, reg) sys_read32(udma_base + reg)
|
||||
#define SY1XX_UDMA_WRITE_REG(udma_base, reg, value) sys_write32(value, udma_base + reg)
|
||||
|
||||
#define UDMA_CANCEL_RX(udma_base) drivers_udma_cancel(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_CANCEL_TX(udma_base) drivers_udma_cancel(udma_base, UDMA_TX_CHANNEL)
|
||||
#define SY1XX_UDMA_CANCEL_RX(udma_base) sy1xx_udma_cancel(udma_base, SY1XX_UDMA_RX_CHANNEL)
|
||||
#define SY1XX_UDMA_CANCEL_TX(udma_base) sy1xx_udma_cancel(udma_base, SY1XX_UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_IS_FINISHED_RX(udma_base) drivers_udma_is_ready(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_IS_FINISHED_TX(udma_base) drivers_udma_is_ready(udma_base, UDMA_TX_CHANNEL)
|
||||
#define SY1XX_UDMA_IS_FINISHED_RX(udma_base) sy1xx_udma_is_ready(udma_base, SY1XX_UDMA_RX_CHANNEL)
|
||||
#define SY1XX_UDMA_IS_FINISHED_TX(udma_base) sy1xx_udma_is_ready(udma_base, SY1XX_UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_WAIT_FOR_FINISHED_RX(udma_base) \
|
||||
drivers_udma_wait_for_finished(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_WAIT_FOR_FINISHED_TX(udma_base) \
|
||||
drivers_udma_wait_for_finished(udma_base, UDMA_TX_CHANNEL)
|
||||
#define SY1XX_UDMA_WAIT_FOR_FINISHED_RX(udma_base) \
|
||||
sy1xx_udma_wait_for_finished(udma_base, SY1XX_UDMA_RX_CHANNEL)
|
||||
#define SY1XX_UDMA_WAIT_FOR_FINISHED_TX(udma_base) \
|
||||
sy1xx_udma_wait_for_finished(udma_base, SY1XX_UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_START_RX(base, addr, size, cfg) \
|
||||
drivers_udma_start(base, UDMA_RX_CHANNEL, addr, size, cfg)
|
||||
#define UDMA_START_TX(base, addr, size, cfg) \
|
||||
drivers_udma_start(base, UDMA_TX_CHANNEL, addr, size, cfg)
|
||||
#define SY1XX_UDMA_START_RX(base, addr, size, cfg) \
|
||||
sy1xx_udma_start(base, SY1XX_UDMA_RX_CHANNEL, addr, size, cfg)
|
||||
#define SY1XX_UDMA_START_TX(base, addr, size, cfg) \
|
||||
sy1xx_udma_start(base, SY1XX_UDMA_TX_CHANNEL, addr, size, cfg)
|
||||
|
||||
#define UDMA_GET_REMAINING_RX(base) drivers_udma_get_remaining(base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_GET_REMAINING_TX(base) drivers_udma_get_remaining(base, UDMA_TX_CHANNEL)
|
||||
#define SY1XX_UDMA_GET_REMAINING_RX(base) sy1xx_udma_get_remaining(base, SY1XX_UDMA_RX_CHANNEL)
|
||||
#define SY1XX_UDMA_GET_REMAINING_TX(base) sy1xx_udma_get_remaining(base, SY1XX_UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_WAIT_FOR_STATUS_IDLE(udma_base) drivers_udma_wait_for_status(udma_base)
|
||||
#define SY1XX_UDMA_WAIT_FOR_STATUS_IDLE(udma_base) sy1xx_udma_wait_for_status(udma_base)
|
||||
|
||||
#endif /* GANYMED_SY1XX_UDMA_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue