boards: Add support for Silicon Labs EFR32BG22-SLTB010A board

This commit adds support for Silicon Labs efr32bg22_sltb010a boardo

Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Co-authored-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>

boards/arm/efr32bg_sltb010a/CMakeLists.txt

@@ -0,0 +1,7 @@
+# Copyright (c) 2021 Sateesh Kotapati
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_UART_GECKO)
+  zephyr_library()
+  zephyr_library_sources(board.c)
+endif()

boards/arm/efr32bg_sltb010a/Kconfig

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+# EFR32BG SLTB010A board
+
+# Copyright (c) 2022, Silicon Labs
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EFR32BG_SLTB010A
+
+module = BOARD_EFR32BG22
+module-str = Board Control
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # BOARD_EFR32BG_SLTB010A

boards/arm/efr32bg_sltb010a/Kconfig.board

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+# EFR32BG SLTB010A board
+
+# Copyright (c) 2021, Sateesh Kotapati
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EFR32BG_SLTB010A
+	bool "SiLabs EFR32BG-SLTB010A (Thunderboard BG22)"
+	depends on SOC_SERIES_EFR32BG22
+	select SOC_PART_NUMBER_EFR32BG22C224F512IM40

boards/arm/efr32bg_sltb010a/Kconfig.defconfig

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+# EFR32BG SLTB010A board
+
+# Copyright (c) 2021, Sateesh Kotapati
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EFR32BG_SLTB010A
+
+config BOARD
+	default "efr32bg_sltb010a"
+
+config CMU_HFXO_FREQ
+	default 40000000
+
+config CMU_LFXO_FREQ
+	default 32768
+
+endif # BOARD_EFR32BG_SLTB010A

boards/arm/efr32bg_sltb010a/board.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+
+#ifdef CONFIG_SOC_GECKO_DEV_INIT
+#include "em_cmu.h"
+#endif
+
+LOG_MODULE_REGISTER(efr32bg_sltb010a, CONFIG_BOARD_EFR32BG22_LOG_LEVEL);
+
+static int efr32bg_sltb010a_init_clocks(void);
+
+static int efr32bg_sltb010a_init(const struct device *dev)
+{
+	int ret;
+
+#ifdef CONFIG_SOC_GECKO_DEV_INIT
+	efr32bg_sltb010a_init_clocks();
+#endif
+	static struct gpio_dt_spec wake_up_gpio_dev =
+		GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios);
+
+	ARG_UNUSED(dev);
+
+	if (!device_is_ready(wake_up_gpio_dev.port)) {
+		LOG_ERR("Wake-up GPIO device was not found!\n");
+		return -ENODEV;
+	}
+	ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_SOC_GECKO_DEV_INIT
+static int efr32bg_sltb010a_init_clocks(void)
+{
+	CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL);
+#if defined(_CMU_EM01GRPACLKCTRL_MASK)
+	CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL);
+#endif
+#if defined(_CMU_EM01GRPBCLKCTRL_MASK)
+	CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL);
+#endif
+	CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO);
+	CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO);
+#if defined(RTCC_PRESENT)
+	CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO);
+#endif
+	CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO);
+
+	return 0;
+}
+#endif
+
+/* needs to be done after GPIO driver init */
+SYS_INIT(efr32bg_sltb010a_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

boards/arm/efr32bg_sltb010a/board.cmake

@@ -0,0 +1,7 @@
+# Copyright (c) 2021, Sateesh Kotapati
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/efr32bg_sltb010a/doc/index.rst

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+.. _efr32bg_sltb010a:
+
+EFR32BG-SLTB010A
+################
+
+Overview
+********
+
+The EFR32™ Blue Gecko Starter Kit EFR32BG-SLTB010A (a.k.a Thunderboard EFR32BG22)
+contains a MCU from the EFR32BG family built on ARM® Cortex®-M33F
+processor with low power capabilities.
+
+.. image:: ./efr32bg_sltb010a.jpg
+   :align: center
+   :alt: EFR32BG-SLTB010A
+
+Hardware
+********
+
+- EFR32BG22 Blue Gecko Wireless SoC with upto 76.8 MHz operating frequency
+- ARM® Cortex® M33 core with 32 kB RAM and 512 kB Flash
+- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F)
+- 2.4 GHz ceramic antenna for wireless transmission
+- Silicon Labs Si7021 relative humidity and temperature sensor
+- Silicon Labs Si1133 UV index and ambient light sensor
+- Silicon Labs Si7210 hall effect sensor
+- TDK InvenSense ICM-20648 6-axis inertial sensor
+- One LED and one push button
+- Power enable signals and isolation switches for ultra low power operation
+- On-board SEGGER J-Link debugger for easy programming and debugging, which
+  includes a USB virtual COM port and Packet Trace Interface (PTI)
+- Mini Simplicity connector for access to energy profiling and advanced wireless
+  network debugging
+- Breakout pads for GPIO access and connection to external hardware
+- Reset button
+- Automatic switch-over between USB and battery power
+- CR2032 coin cell holder and external battery connector
+
+For more information about the EFR32BG SoC and Thunderboard EFR32BG22
+(EFR32BG-SLTB010A) board:
+
+- `EFR32BG22 Website`_
+- `EFR32BG22 Datasheet`_
+- `EFR32xG22 Reference Manual`_
+- `EFR32BG22-SLTB010A Website`_
+- `EFR32BG22-SLTB010A User Guide`_
+- `EFR32BG22-SLTB010A Schematics`_
+
+Supported Features
+==================
+
+The efr32bg_sltb010a board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| MPU       | on-chip    | memory protection unit              |
++-----------+------------+-------------------------------------+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| COUNTER   | on-chip    | stimer                              |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash memory                        |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial                              |
++-----------+------------+-------------------------------------+
+| WATCHDOG  | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+| TRNG      | on-chip    | true random number generator        |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+``boards/arm/efr32bg_sltb010a/efr32bg_sltb010a_defconfig``.
+
+Other hardware features are currently not supported by the port.
+
+Connections and IOs
+===================
+
+The EFR32BG SoC has six gpio controllers (PORTA, PORTB, PORTC, PORTD,
+PORTE and PORTF).
+
+In the following table, the column Name contains Pin names. For example, PE2
+means Pin number 2 on PORTE and #27 represents the location bitfield , as used
+in the board's and microcontroller's datasheets and manuals.
+
++------+-------------+-----------------------------------+
+| Name | Function    | Usage                             |
++======+=============+===================================+
+| PB0  | GPIO        | LED0 (RED)                        |
++------+-------------+-----------------------------------+
+| PB1  | GPIO        | SW0 Push Button PB0               |
++------+-------------+-----------------------------------+
+| PA5  | UART_TX     | UART TX Console VCOM_TX US1_TX #1 |
++------+-------------+-----------------------------------+
+| PA6  | UART_RX     | UART RX Console VCOM_RX US1_RX #1 |
++------+-------------+-----------------------------------+
+
+System Clock
+============
+
+The EFR32BG SoC is configured to use the 38.4 MHz external oscillator on the
+board.
+
+Serial Port
+===========
+
+The EFR32BG22 SoC has two USARTs.
+USART1 is connected to the board controller and is used for the console.
+
+Programming and Debugging
+*************************
+
+.. note::
+   Before using the kit the first time, you should update the J-Link firmware
+   from `J-Link-Downloads`_
+
+Flashing
+========
+
+The EFR32BG-SLTB010A includes an `J-Link`_ serial and debug adaptor built into the
+board. The adaptor provides:
+
+- A USB connection to the host computer, which exposes a Mass Storage and a
+  USB Serial Port.
+- A Serial Flash device, which implements the USB flash disk file storage.
+- A physical UART connection which is relayed over interface USB Serial port.
+
+Flashing an application to EFR32BG-SLTB010A
+-------------------------------------------
+
+The sample application :ref:`hello_world` is used for this example.
+Build the Zephyr kernel and application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: efr32bg_sltb010a
+   :goals: build
+
+Connect the EFR32BG-SLTB010A to your host computer using the USB port and you
+should see a USB connection.
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! efr32bg_sltb010a
+
+
+.. _EFR32BG22-SLTB010A Website:
+   https://www.silabs.com/development-tools/thunderboard/thunderboard-bg22-kit
+
+.. _EFR32BG22-SLTB010A User Guide:
+   https://www.silabs.com/documents/public/user-guides/ug415-sltb010a-user-guide.pdf
+
+.. _EFR32BG22-SLTB010A Schematics:
+   https://www.silabs.com/documents/public/schematic-files/BRD4184A-A01-schematic.pdf
+
+.. _EFR32BG22 Website:
+   https://www.silabs.com/wireless/bluetooth/efr32bg22-series-2-socs
+
+.. _EFR32BG22 Datasheet:
+   https://www.silabs.com/documents/public/data-sheets/efr32bg22-datasheet.pdf
+
+.. _EFR32xG22 Reference Manual:
+   https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf
+
+.. _J-Link:
+   https://www.segger.com/jlink-debug-probes.html
+
+.. _J-Link-Downloads:
+   https://www.segger.com/downloads/jlink

boards/arm/efr32bg_sltb010a/dts/bindings/silabs,gecko-wake-up-triggers.yaml

@@ -0,0 +1,15 @@
+# Copyright (c) 2022, Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+description: GPIO Wake Up Trigger for EFR32BG22
+
+compatible: "silabs,gecko-wake-up-trigger"
+
+include: base.yaml
+
+properties:
+  gpios:
+    type: phandle-array
+    required: true
+    description: |
+      GPIO used as wake up trigger from EM4 sleep

boards/arm/efr32bg_sltb010a/efr32bg_sltb010a.dts

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/efr32bg22c224f512im40.dtsi>
+#include <silabs/efr32bg22-pinctrl.dtsi>
+
+/ {
+	model = "Silicon Labs EFR32BG SLTB010A (aka Thunderboard BG22)";
+	compatible = "silabs,efr32bg_sltb010a", "silabs,efr32bg22";
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		sw0 = &button0;
+	};
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>;
+			label = "LED 0";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>;
+			label = "User Push Button 0";
+		};
+	};
+
+	wake_up_trigger: gpio-wake-up  {
+		compatible = "silabs,gecko-wake-up-trigger";
+		gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>;
+	};
+
+};
+
+&cpu0 {
+	clock-frequency = <76800000>;
+};
+
+&usart1 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserve 32 kB for the bootloader */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 0x00008000>;
+			read-only;
+		};
+
+		/* Reserve 220 kB for the application in slot 0 */
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x0008000 0x00037000>;
+		};
+
+		/* Reserve 220 kB for the application in slot 1 */
+		slot1_partition: partition@3f000 {
+			label = "image-1";
+			reg = <0x0003f000 0x00037000>;
+		};
+
+		/* Reserve 32 kB for the scratch partition */
+		scratch_partition: partition@76000 {
+			label = "image-scratch";
+			reg = <0x00076000 0x00008000>;
+		};
+
+		/* Set 8Kb of storage at the end of the 512KB of flash */
+		storage_partition: partition@7e000 {
+			label = "storage";
+			reg = <0x0007e000 0x00002000>;
+		};
+
+	};
+};
+
+&gpio {
+	location-swo = <0>;
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&stimer0 {
+	status = "okay";
+};

boards/arm/efr32bg_sltb010a/efr32bg_sltb010a.yaml

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+identifier: efr32bg_sltb010a
+name: EFR32BG-SLTB010A
+type: mcu
+arch: arm
+ram: 32
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - counter
+  - gpio
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm/efr32bg_sltb010a/efr32bg_sltb010a_defconfig

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_SOC_SERIES_EFR32BG22=y
+CONFIG_BOARD_EFR32BG_SLTB010A=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000
+CONFIG_CMU_HFCLK_HFXO=y
+CONFIG_SOC_GECKO_EMU_DCDC=y
+CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_CMU_HFCLK_HFRCO=y
+CONFIG_PINCTRL=y

boards/arm/efr32bg_sltb010a/pre_dt_board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# SPI is implemented via usart so node name isn't spi@...
+list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")

boards/arm/efr32bg_sltb010a/sl_device_init_hfxo_config.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2022 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H
+#define SL_DEVICE_INIT_HFXO_CONFIG_H
+
+#define SL_DEVICE_INIT_HFXO_MODE           cmuHfxoOscMode_Crystal
+#define SL_DEVICE_INIT_HFXO_FREQ           38400000
+#define SL_DEVICE_INIT_HFXO_CTUNE          120
+
+#endif /* SL_DEVICE_INIT_HFXO_CONFIG_H */