diff --git a/soc/riscv/openisa_rv32m1/Kconfig.defconfig b/soc/riscv/openisa_rv32m1/Kconfig.defconfig
index 20a7fd1c86b..75177475362 100644
--- a/soc/riscv/openisa_rv32m1/Kconfig.defconfig
+++ b/soc/riscv/openisa_rv32m1/Kconfig.defconfig
@@ -41,17 +41,6 @@ config RISCV_SOC_INTERRUPT_INIT
 config WDOG_INIT
 	def_bool y
 
-# The event unit looks for vector tables at the end of each core's
-# flash space. These vector tables are not relocatable.
-config RISCV_RV32M1_VECTOR_BASE_ADDR
-	hex
-	default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
-	default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
-
-config RISCV_RV32M1_VECTOR_SIZE
-	hex
-	default 0x100
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 8000000
 
diff --git a/soc/riscv/openisa_rv32m1/linker.ld b/soc/riscv/openisa_rv32m1/linker.ld
index b441b899470..0e900afd511 100644
--- a/soc/riscv/openisa_rv32m1/linker.ld
+++ b/soc/riscv/openisa_rv32m1/linker.ld
@@ -26,7 +26,7 @@
 #define ROMABLE_REGION              ROM
 #define RAMABLE_REGION              RAM
 
-#define VECTOR_SIZE CONFIG_RISCV_RV32M1_VECTOR_SIZE
+#define VECTOR_SIZE 0x100
 
 #ifdef CONFIG_USE_DT_CODE_PARTITION