drivers: spi: Add MEC172x QMSPI-LDMA driver

Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>

boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts

@@ -46,6 +46,7 @@
 };
 
 &cpu0 {
+	clock-frequency = <96000000>;
 	status = "okay";
 };
 
@@ -139,3 +140,10 @@
 	label = "I2C7";
 	port_sel = <7>;
 };
+
+&spi0 {
+	status = "okay";
+	clock-frequency = <4000000>;
+	lines = <4>;
+	chip-select = <0>;
+};

boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig

@@ -18,3 +18,5 @@ CONFIG_UART_CONSOLE=y
 CONFIG_ADC=y
 CONFIG_I2C=y
 CONFIG_ESPI=y
+CONFIG_SPI=y
+CONFIG_SPI_ASYNC=y

drivers/spi/CMakeLists.txt

@@ -27,5 +27,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_TEST		spi_test.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6		spi_psoc6.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU	spi_npcx_fiu.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG		spi_bitbang.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA	spi_xec_qmspi_ldma.c)
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		spi_handlers.c)

drivers/spi/Kconfig

@@ -97,4 +97,6 @@ source "drivers/spi/Kconfig.npcx_fiu"
 
 source "drivers/spi/Kconfig.bitbang"
 
+source "drivers/spi/Kconfig.xec_qmspi_ldma"
+
 endif # SPI

drivers/spi/Kconfig.xec_qmspi

@@ -6,7 +6,7 @@
 config SPI_XEC_QMSPI
 	bool "Microchip XEC QMSPI driver"
 	default y
-	depends on SOC_FAMILY_MEC
+	depends on SOC_SERIES_MEC1501X
 	select DMA if SPI_ASYNC
 	help
 	  Enable support for the Microchip XEC QMSPI driver.

drivers/spi/Kconfig.xec_qmspi_ldma

@@ -0,0 +1,11 @@
+# Microchip XEC QMSPI with LDMA
+
+# Copyright (c) 2021 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_XEC_QMSPI_LDMA
+	bool "Microchip XEC QMSPI LDMA driver"
+	default y
+	depends on SOC_SERIES_MEC172X
+	help
+	  Enable support for the Microchip XEC QMSPI with local DMA driver.

dts/arm/microchip/mec172xnsz.dtsi

@@ -754,23 +754,17 @@
 			#size-cells = <0>;
 		};
 		spi0: spi@40070000 {
+			compatible = "microchip,xec-qmspi-ldma";
 			reg = <0x40070000 0x400>;
 			interrupts = <91 2>;
-			girqs = <18 1>;
+			girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >;
 			pcrs = <4 8>;
 			clock-frequency = <12000000>;
 			label = "SPI_0";
-			ldmas = <3 3>;
 			lines = <1>;
-			chip_select = <0>;
+			chip-select = <0>;
-			dcsckon = <6>;
-			dckcsoff = <4>;
-			dldh = <6>;
-			dcsda = <6>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			#ldma-cells = <2>;
-			#legdma-cells = <2>;
 			status = "disabled";
 		};
 		spi1: spi@40009400 {

dts/bindings/spi/microchip,xec-qmspi-ldma.yaml

@@ -0,0 +1,106 @@
+# Copyright (c) 2018, Google LLC.
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC QMSPI controller with local DMA
+
+compatible: "microchip,xec-qmspi-ldma"
+
+include: spi-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: |
+        An array of integers encoding each interrupt signal connection.
+        This information includes the aggregated GIRQ number, GIRQ bit
+        position, aggregated GIRQ NVIC connection, and direct NVIC
+        connection of the GIRQ bit.
+
+    pcrs:
+      type: array
+      required: true
+      description: |
+        A two entry integer array containing the QMSPI PCR sleep register
+        index and bit position.
+
+    lines:
+      type: int
+      required: false
+      description: |
+        QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
+        MOSI and MISO or half-duplex on MOSI only. Lines set to 2
+        or 4 indicate dual or quad I/O modes. Defaults to 1.
+
+    port-sel:
+      type: int
+      required: false
+      description: |
+        SPI Port 0, 1, or 2. Port 0 is the shared SPI, port 1 is
+        the private SPI, and port 2 is the internal SPI port for
+        chip configurations with an embedded SPI flash. Defaults
+        to port 0 (shared SPI port).
+
+    chip-select:
+      type: int
+      required: false
+      description: |
+        Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
+        Ports 1 and 2 implement CS0# only. Defaults to CS0#.
+
+    dcsckon:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# assertion to first clock edge.
+        If not present use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    dckcsoff:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
+        If not presetn use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    dldh:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
+        and WP#. If not present use hardware default value. Refer to chip
+        documention for QMSPI input clock frequency.
+
+    dcsda:
+      type: int
+      required: false
+      description: |
+        Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
+        If not present use hardware default value. Refer to chip documention
+        for QMSPI input clock frequency.
+
+    cs1-freq:
+      type: int
+      required: false
+      description: |
+        Allows different frequencies for CS#0 and CS1# devices. This applies
+        to ports implementing CS1#.
+
+    tctradj:
+      type: int
+      required: false
+      description: |
+        An optional signed 8-bit value for adjusting the QMSPI control signal
+        timing tap.
+
+    tsckadj:
+      type: int
+      required: false
+      description: |
+        An optional signed 8-bit value for adjusting the QMSPI clock signal
+        timing tap.

soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz

@@ -35,4 +35,8 @@ config ESPI_XEC_V2
 	default y
 	depends on ESPI
 
+config SPI_XEC_QMSPI_LDMA
+	default y
+	depends on SPI
+
 endif # SOC_MEC172X_NSZ

soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h

@@ -21,8 +21,8 @@
 
 /* MEC172XH-B0-SZ (144-pin) */
 #define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036  GIRQ11 */
-#define MCHP_GPIO_PORT_B_BITMAP 0x0FFFFFFDu /* GPIO_0040 - 0076  GIRQ10 */
+#define MCHP_GPIO_PORT_B_BITMAP 0x3FFFFFFDu /* GPIO_0040 - 0076  GIRQ10 */
-#define MCHP_GPIO_PORT_C_BITMAP 0x07FF3CF7u /* GPIO_0100 - 0136  GIRQ09 */
+#define MCHP_GPIO_PORT_C_BITMAP 0x07FFFCF7u /* GPIO_0100 - 0136  GIRQ09 */
 #define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFu /* GPIO_0140 - 0176  GIRQ08 */
 #define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFu /* GPIO_0200 - 0236  GIRQ12 */
 #define MCHP_GPIO_PORT_F_BITMAP 0x0000397Fu /* GPIO_0240 - 0276  GIRQ26 */

soc/arm/microchip_mec/mec172x/reg/mec172x_qspi.h

@@ -252,12 +252,14 @@
 /* Status Register */
 #define MCHP_QMSPI_STS_REG_MASK		0x0f01ff1fu
 #define MCHP_QMSPI_STS_RO_MASK		0x0f013300u
-#define MCHP_QMSPI_STS_RW1C_MASK	0x0000cc1fu
+#define MCHP_QMSPI_STS_RW1C_MASK	0x0000cc7fu
 #define MCHP_QMSPI_STS_DONE		BIT(0)
 #define MCHP_QMSPI_STS_DMA_DONE		BIT(1)
 #define MCHP_QMSPI_STS_TXB_ERR		BIT(2)
 #define MCHP_QMSPI_STS_RXB_ERR		BIT(3)
 #define MCHP_QMSPI_STS_PROG_ERR		BIT(4)
+#define MCHP_QMSPI_STS_LDMA_RX_ERR	BIT(5)
+#define MCHP_QMSPI_STS_LDMA_TX_ERR	BIT(6)
 #define MCHP_QMSPI_STS_TXBF_RO		BIT(8)
 #define MCHP_QMSPI_STS_TXBE_RO		BIT(9)
 #define MCHP_QMSPI_STS_TXBR		BIT(10)
@@ -283,6 +285,8 @@
 #define MCHP_QMSPI_IEN_TXB_ERR		BIT(2)
 #define MCHP_QMSPI_IEN_RXB_ERR		BIT(3)
 #define MCHP_QMSPI_IEN_PROG_ERR		BIT(4)
+#define MCHP_QMSPI_IEN_LDMA_RX_ERR	BIT(5)
+#define MCHP_QMSPI_IEN_LDMA_TX_ERR	BIT(6)
 #define MCHP_QMSPI_IEN_TXB_FULL		BIT(8)
 #define MCHP_QMSPI_IEN_TXB_EMPTY	BIT(9)
 #define MCHP_QMSPI_IEN_TXB_REQ		BIT(10)