From fd42bf7443cb2f36619be0eab7aa378c30f49da7 Mon Sep 17 00:00:00 2001 From: Patrik Flykt Date: Thu, 14 Mar 2019 16:04:29 -0600 Subject: [PATCH] soc: Rename reserved function names Rename reserved function names in the soc/ subdirectory. Signed-off-by: Patrik Flykt --- arch/arm/include/cortex_m/exc.h | 2 +- drivers/pinmux/pinmux_esp32.c | 2 +- soc/arc/quark_se_c1000_ss/power.c | 18 +++++++++--------- soc/arc/quark_se_c1000_ss/soc.c | 2 +- soc/arc/quark_se_c1000_ss/soc.h | 2 +- soc/arc/quark_se_c1000_ss/soc_power.S | 16 ++++++++-------- soc/arm/atmel_sam/sam3x/soc.c | 2 +- soc/arm/atmel_sam/sam4s/soc.c | 2 +- soc/arm/atmel_sam/same70/soc.c | 2 +- soc/arm/atmel_sam0/samd20/soc.c | 2 +- soc/arm/atmel_sam0/samd21/soc.c | 2 +- soc/arm/nordic_nrf/nrf52/soc.c | 2 +- soc/arm/nordic_nrf/nrf91/soc.c | 2 +- soc/arm/nxp_imx/mcimx6x_m4/soc.c | 2 +- soc/arm/nxp_imx/rt/soc.c | 2 +- soc/arm/nxp_kinetis/k6x/soc.c | 2 +- soc/arm/nxp_kinetis/kwx/soc_kw2xd.c | 2 +- soc/arm/nxp_lpc/lpc54xxx/soc.c | 2 +- soc/arm/silabs_exx32/common/soc.c | 2 +- soc/arm/st_stm32/stm32f0/soc.c | 2 +- soc/arm/st_stm32/stm32f1/soc.c | 2 +- soc/arm/st_stm32/stm32f2/soc.c | 2 +- soc/arm/st_stm32/stm32f3/soc.c | 2 +- soc/arm/st_stm32/stm32f4/soc.c | 2 +- soc/arm/st_stm32/stm32f7/soc.c | 2 +- soc/arm/st_stm32/stm32l0/soc.c | 2 +- soc/arm/st_stm32/stm32l4/soc.c | 2 +- soc/arm/ti_lm3s6965/reboot.S | 12 ++++++------ soc/arm/ti_lm3s6965/sys_arch_reboot.c | 8 ++++---- soc/x86/intel_quark/quark_se/power.c | 18 +++++++++--------- soc/x86/intel_quark/quark_se/soc.c | 4 ++-- soc/x86/intel_quark/quark_se/soc.h | 2 +- soc/x86/intel_quark/quark_se/soc_power.S | 22 +++++++++++----------- soc/xtensa/esp32/esp32-mp.c | 18 +++++++++--------- 34 files changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h index df89eb07b31..4306b3536cc 100644 --- a/arch/arm/include/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -144,7 +144,7 @@ static ALWAYS_INLINE void z_ExcSetup(void) * * @return N/A */ -static ALWAYS_INLINE void _ClearFaults(void) +static ALWAYS_INLINE void z_clearfaults(void) { #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) diff --git a/drivers/pinmux/pinmux_esp32.c b/drivers/pinmux/pinmux_esp32.c index a796e59b004..8f0819f6f27 100644 --- a/drivers/pinmux/pinmux_esp32.c +++ b/drivers/pinmux/pinmux_esp32.c @@ -112,7 +112,7 @@ static int pinmux_pullup(struct device *dev, u32_t pin, u8_t func) return -EINVAL; } -#define CFG(id) ((GPIO_ ## id ## _REG) & 0xff) +#define CFG(id) ((GPIO_ ## id ## Z_REG) & 0xff) static int pinmux_input(struct device *dev, u32_t pin, u8_t func) { static const u8_t offs[2][3] = { diff --git a/soc/arc/quark_se_c1000_ss/power.c b/soc/arc/quark_se_c1000_ss/power.c index 0663b5ead32..bd314c24cdb 100644 --- a/soc/arc/quark_se_c1000_ss/power.c +++ b/soc/arc/quark_se_c1000_ss/power.c @@ -18,20 +18,20 @@ #include "vreg.h" #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) -extern void _power_soc_sleep(void); -extern void _power_soc_deep_sleep(void); -extern void _power_soc_lpss_mode(void); +extern void z_power_soc_sleep(void); +extern void z_power_soc_deep_sleep(void); +extern void z_power_soc_lpss_mode(void); -static void _deep_sleep(enum power_states state) +static void deep_sleep(enum power_states state) { qm_power_soc_set_ss_restore_flag(); switch (state) { case SYS_POWER_STATE_DEEP_SLEEP_2: - _power_soc_sleep(); + z_power_soc_sleep(); break; case SYS_POWER_STATE_DEEP_SLEEP_3: - _power_soc_deep_sleep(); + z_power_soc_deep_sleep(); break; default: break; @@ -54,11 +54,11 @@ void sys_set_power_state(enum power_states state) case SYS_POWER_STATE_DEEP_SLEEP_1: qm_ss_power_soc_lpss_enable(); qm_power_soc_set_ss_restore_flag(); - _power_soc_lpss_mode(); + z_power_soc_lpss_mode(); break; case SYS_POWER_STATE_DEEP_SLEEP_2: case SYS_POWER_STATE_DEEP_SLEEP_3: - _deep_sleep(state); + deep_sleep(state); break; #endif default: @@ -90,7 +90,7 @@ void _sys_pm_power_state_exit_post_ops(enum power_states state) * its execution. */ if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) { - _quark_se_ss_ready(); + z_quark_se_ss_ready(); __builtin_arc_seti(0); } else { QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY; diff --git a/soc/arc/quark_se_c1000_ss/soc.c b/soc/arc/quark_se_c1000_ss/soc.c index 68a3df3de09..38c88fd3f54 100644 --- a/soc/arc/quark_se_c1000_ss/soc.c +++ b/soc/arc/quark_se_c1000_ss/soc.c @@ -24,7 +24,7 @@ static int quark_se_arc_init(struct device *arg) { ARG_UNUSED(arg); - _quark_se_ss_ready(); + quark_se_ss_ready(); return 0; } diff --git a/soc/arc/quark_se_c1000_ss/soc.h b/soc/arc/quark_se_c1000_ss/soc.h index ca576977406..e9202712ab1 100644 --- a/soc/arc/quark_se_c1000_ss/soc.h +++ b/soc/arc/quark_se_c1000_ss/soc.h @@ -201,7 +201,7 @@ #define DT_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) -static inline void _quark_se_ss_ready(void) +static inline void quark_se_ss_ready(void) { shared_data->flags |= ARC_READY; } diff --git a/soc/arc/quark_se_c1000_ss/soc_power.S b/soc/arc/quark_se_c1000_ss/soc_power.S index b33359932bc..4be678763f4 100644 --- a/soc/arc/quark_se_c1000_ss/soc_power.S +++ b/soc/arc/quark_se_c1000_ss/soc_power.S @@ -11,11 +11,11 @@ #ifdef CONFIG_SYS_POWER_DEEP_SLEEP_STATES GDATA(_pm_arc_context) -GTEXT(_sys_resume_from_deep_sleep) -GTEXT(_power_restore_cpu_context) -GTEXT(_power_soc_sleep) -GTEXT(_power_soc_deep_sleep) -GTEXT(_power_soc_lpss_mode) +GTEXT(sys_resume_from_deep_sleep) +GTEXT(z_power_restore_cpu_context) +GTEXT(z_power_soc_sleep) +GTEXT(z_power_soc_deep_sleep) +GTEXT(z_power_soc_lpss_mode) #define GPS0_REGISTER 0xb0800100 #define GP0_REGISTER 0xb0800114 @@ -47,7 +47,7 @@ SECTION_FUNC(TEXT, save_cpu_context) j_s [blink] /* Jump to context of BLINK register. */ -SECTION_FUNC(TEXT, _power_soc_sleep) +SECTION_FUNC(TEXT, z_power_soc_sleep) /* * Save the return address. * The restore function will pop this and jump @@ -60,7 +60,7 @@ SECTION_FUNC(TEXT, _power_soc_sleep) j @qm_power_soc_sleep /* Does not return */ -SECTION_FUNC(TEXT, _power_soc_deep_sleep) +SECTION_FUNC(TEXT, z_power_soc_deep_sleep) /* * Save the return address. * The restore function will pop this and jump @@ -73,7 +73,7 @@ SECTION_FUNC(TEXT, _power_soc_deep_sleep) j @qm_power_soc_deep_sleep /* Does not return */ -SECTION_FUNC(TEXT, _power_soc_lpss_mode) +SECTION_FUNC(TEXT, z_power_soc_lpss_mode) /* * Setup 'sleep' instruction operand. */ diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c index a36db7ff2bc..9bcaad2b95f 100644 --- a/soc/arm/atmel_sam/sam3x/soc.c +++ b/soc/arm/atmel_sam/sam3x/soc.c @@ -209,7 +209,7 @@ static int atmel_sam3x_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* * Set FWS (Flash Wait State) value before increasing Master Clock diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c index 880101e8f32..6bc8d7233f9 100644 --- a/soc/arm/atmel_sam/sam4s/soc.c +++ b/soc/arm/atmel_sam/sam4s/soc.c @@ -197,7 +197,7 @@ static int atmel_sam4s_init(struct device *arg) key = irq_lock(); /* Clear all faults. */ - _ClearFaults(); + z_clearfaults(); /* * Set FWS (Flash Wait State) value before increasing Master Clock diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c index 6c8d0daa715..d4dd0c36833 100644 --- a/soc/arm/atmel_sam/same70/soc.c +++ b/soc/arm/atmel_sam/same70/soc.c @@ -234,7 +234,7 @@ static int atmel_same70_init(struct device *arg) } /* Clear all faults */ - _ClearFaults(); + z_clearfaults(); /* * Set FWS (Flash Wait State) value before increasing Master Clock diff --git a/soc/arm/atmel_sam0/samd20/soc.c b/soc/arm/atmel_sam0/samd20/soc.c index 64417504a0e..ee77f0f5f01 100644 --- a/soc/arm/atmel_sam0/samd20/soc.c +++ b/soc/arm/atmel_sam0/samd20/soc.c @@ -172,7 +172,7 @@ static int atmel_samd_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); flash_waitstates_init(); osc8m_init(); diff --git a/soc/arm/atmel_sam0/samd21/soc.c b/soc/arm/atmel_sam0/samd21/soc.c index edfec76019d..f56218b3ec9 100644 --- a/soc/arm/atmel_sam0/samd21/soc.c +++ b/soc/arm/atmel_sam0/samd21/soc.c @@ -173,7 +173,7 @@ static int atmel_samd_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); flash_waitstates_init(); osc8m_init(); diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/arm/nordic_nrf/nrf52/soc.c index 1209405e73f..44e9edbdf8b 100644 --- a/soc/arm/nordic_nrf/nrf52/soc.c +++ b/soc/arm/nordic_nrf/nrf52/soc.c @@ -69,7 +69,7 @@ static int nordicsemi_nrf52_init(struct device *arg) nrf_power_dcdcen_set(true); #endif - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/arm/nordic_nrf/nrf91/soc.c index 62a201b1111..72a53db8b02 100644 --- a/soc/arm/nordic_nrf/nrf91/soc.c +++ b/soc/arm/nordic_nrf/nrf91/soc.c @@ -50,7 +50,7 @@ static int nordicsemi_nrf91_init(struct device *arg) NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk; #endif - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c index d20a3d054df..f22e1699329 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c +++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c @@ -187,7 +187,7 @@ static int mcimx6x_m4_init(struct device *arg) /* Initialize Cache */ SOC_CacheInit(); - _ClearFaults(); + z_clearfaults(); /* Initialize clock */ SOC_ClockInit(); diff --git a/soc/arm/nxp_imx/rt/soc.c b/soc/arm/nxp_imx/rt/soc.c index bda9b546a2f..126a07f76ec 100644 --- a/soc/arm/nxp_imx/rt/soc.c +++ b/soc/arm/nxp_imx/rt/soc.c @@ -210,7 +210,7 @@ static int imxrt_init(struct device *arg) SCB_EnableDCache(); } - _ClearFaults(); + z_clearfaults(); /* Initialize system clock */ clkInit(); diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c index cd03b97405d..179ec6667e8 100644 --- a/soc/arm/nxp_kinetis/k6x/soc.c +++ b/soc/arm/nxp_kinetis/k6x/soc.c @@ -180,7 +180,7 @@ static int fsl_frdm_k64f_init(struct device *arg) SYSMPU->CESR = temp_reg; #endif /* !CONFIG_ARM_MPU */ - _ClearFaults(); + z_clearfaults(); /* Initialize PLL/system clock to 120 MHz */ clkInit(); diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c index 9c7550a0c36..9c7962e8ec4 100644 --- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c +++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c @@ -189,7 +189,7 @@ static int kw2xd_init(struct device *arg) /* release I/O power hold to allow normal run state */ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; - _ClearFaults(); + z_clearfaults(); /* Initialize PLL/system clock to 48 MHz */ clkInit(); diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c index 9fe3462adc1..ee526d8532d 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c @@ -87,7 +87,7 @@ static int nxp_lpc54114_init(struct device *arg) /* disable interrupts */ oldLevel = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Initialize FRO/system clock to 48 MHz */ clkInit(); diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c index d6b67f89ec5..24d83347343 100644 --- a/soc/arm/silabs_exx32/common/soc.c +++ b/soc/arm/silabs_exx32/common/soc.c @@ -119,7 +119,7 @@ static int silabs_exx32_init(struct device *arg) /* handle chip errata */ CHIP_Init(); - _ClearFaults(); + z_clearfaults(); #ifdef CONFIG_SOC_GECKO_EMU_DCDC dcdc_init(); diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/arm/st_stm32/stm32f0/soc.c index c9d10f63e90..b652909816e 100644 --- a/soc/arm/st_stm32/stm32f0/soc.c +++ b/soc/arm/st_stm32/stm32f0/soc.c @@ -62,7 +62,7 @@ static int stm32f0_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/arm/st_stm32/stm32f1/soc.c index 74bed869621..714eb3b0c1a 100644 --- a/soc/arm/st_stm32/stm32f1/soc.c +++ b/soc/arm/st_stm32/stm32f1/soc.c @@ -30,7 +30,7 @@ static int stm32f1_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/arm/st_stm32/stm32f2/soc.c index b027196a07d..78fbc782143 100644 --- a/soc/arm/st_stm32/stm32f2/soc.c +++ b/soc/arm/st_stm32/stm32f2/soc.c @@ -34,7 +34,7 @@ static int stm32f2_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/arm/st_stm32/stm32f3/soc.c index 9b68c0588db..042d31c55fe 100644 --- a/soc/arm/st_stm32/stm32f3/soc.c +++ b/soc/arm/st_stm32/stm32f3/soc.c @@ -30,7 +30,7 @@ static int stm32f3_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/arm/st_stm32/stm32f4/soc.c index cd24d70fa6c..952efbd2095 100644 --- a/soc/arm/st_stm32/stm32f4/soc.c +++ b/soc/arm/st_stm32/stm32f4/soc.c @@ -31,7 +31,7 @@ static int st_stm32f4_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c index 87261dfd733..2e6a711008a 100644 --- a/soc/arm/st_stm32/stm32f7/soc.c +++ b/soc/arm/st_stm32/stm32f7/soc.c @@ -37,7 +37,7 @@ static int st_stm32f7_init(struct device *arg) SCB_EnableDCache(); } - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/arm/st_stm32/stm32l0/soc.c index 3254c18987f..2cce2a7f135 100644 --- a/soc/arm/st_stm32/stm32l0/soc.c +++ b/soc/arm/st_stm32/stm32l0/soc.c @@ -32,7 +32,7 @@ static int stm32l0_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/arm/st_stm32/stm32l4/soc.c index 96abca3e51a..01ffd2844ab 100644 --- a/soc/arm/st_stm32/stm32l4/soc.c +++ b/soc/arm/st_stm32/stm32l4/soc.c @@ -31,7 +31,7 @@ static int stm32l4_init(struct device *arg) key = irq_lock(); - _ClearFaults(); + z_clearfaults(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise diff --git a/soc/arm/ti_lm3s6965/reboot.S b/soc/arm/ti_lm3s6965/reboot.S index f0defaf5958..6c74cd6ee95 100644 --- a/soc/arm/ti_lm3s6965/reboot.S +++ b/soc/arm/ti_lm3s6965/reboot.S @@ -13,8 +13,8 @@ _ASM_FILE_PROLOGUE GDATA(_interrupt_stack) -GTEXT(_do_software_reboot) -SECTION_FUNC(TEXT,_do_software_reboot) +GTEXT(z_do_software_reboot) +SECTION_FUNC(TEXT,z_do_software_reboot) eors r0, r0 @@ -26,8 +26,8 @@ SECTION_FUNC(TEXT,_do_software_reboot) bx r0 -GTEXT(_force_exit_one_nested_irq) -SECTION_FUNC(TEXT,_force_exit_one_nested_irq) +GTEXT(z_force_exit_one_nested_irq) +SECTION_FUNC(TEXT,z_force_exit_one_nested_irq) ldr r0, =_SCS_ICSR_RETTOBASE ldr r1, =_SCS_ICSR @@ -41,9 +41,9 @@ SECTION_FUNC(TEXT,_force_exit_one_nested_irq) */ ittee eq ldreq lr, =0xfffffff1 - ldreq r2, =_force_exit_one_nested_irq + ldreq r2, =z_force_exit_one_nested_irq ldrne lr, =0xfffffffd - ldrne r2, =_do_software_reboot + ldrne r2, =z_do_software_reboot ldr ip, =_interrupt_stack add.w ip, ip, #(___esf_t_SIZEOF * 2) /* enough for a stack frame */ diff --git a/soc/arm/ti_lm3s6965/sys_arch_reboot.c b/soc/arm/ti_lm3s6965/sys_arch_reboot.c index f0a7692b58d..9140eac67c8 100644 --- a/soc/arm/ti_lm3s6965/sys_arch_reboot.c +++ b/soc/arm/ti_lm3s6965/sys_arch_reboot.c @@ -28,8 +28,8 @@ void sys_arch_reboot(int type) * which address can _always_ be found in the vector table reset slot * located at address 0x4. */ - extern void _do_software_reboot(void); - extern void _force_exit_one_nested_irq(void); + extern void z_do_software_reboot(void); + extern void z_force_exit_one_nested_irq(void); /* * force enable interrupts locked via PRIMASK if somehow disabled: the * boot code does not enable them @@ -37,10 +37,10 @@ void sys_arch_reboot(int type) __asm__ volatile("cpsie i" :::); if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) == 0) { - _do_software_reboot(); + z_do_software_reboot(); } else { __asm__ volatile( - "ldr r0, =_force_exit_one_nested_irq\n\t" + "ldr r0, =z_force_exit_one_nested_irq\n\t" "bx r0\n\t" :::); } diff --git a/soc/x86/intel_quark/quark_se/power.c b/soc/x86/intel_quark/quark_se/power.c index f420f4b57a7..51adfb58865 100644 --- a/soc/x86/intel_quark/quark_se/power.c +++ b/soc/x86/intel_quark/quark_se/power.c @@ -21,15 +21,15 @@ u64_t _pm_save_gdtr; u64_t _pm_save_idtr; u32_t _pm_save_esp; -extern void _power_soc_sleep(void); -extern void _power_restore_cpu_context(void); -extern void _power_soc_deep_sleep(void); +extern void z_power_soc_sleep(void); +extern void z_power_restore_cpu_context(void); +extern void z_power_soc_deep_sleep(void); #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) static u32_t *__x86_restore_info = (u32_t *)CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR; -static void _deep_sleep(enum power_states state) +static void deep_sleep(enum power_states state) { /* * Setting resume vector inside the restore_cpu_context @@ -39,17 +39,17 @@ static void _deep_sleep(enum power_states state) * can be done before cpu context is restored and control * transferred to _sys_suspend. */ - qm_x86_set_resume_vector(_power_restore_cpu_context, + qm_x86_set_resume_vector(z_power_restore_cpu_context, *__x86_restore_info); qm_power_soc_set_x86_restore_flag(); switch (state) { case SYS_POWER_STATE_DEEP_SLEEP_1: - _power_soc_sleep(); + z_power_soc_sleep(); break; case SYS_POWER_STATE_DEEP_SLEEP_2: - _power_soc_deep_sleep(); + z_power_soc_deep_sleep(); break; default: break; @@ -74,7 +74,7 @@ void sys_set_power_state(enum power_states state) #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) case SYS_POWER_STATE_DEEP_SLEEP_1: case SYS_POWER_STATE_DEEP_SLEEP_2: - _deep_sleep(state); + deep_sleep(state); break; #endif default: @@ -96,7 +96,7 @@ void _sys_pm_power_state_exit_post_ops(enum power_states state) #if (defined(CONFIG_SYS_POWER_DEEP_SLEEP_STATES)) case SYS_POWER_STATE_DEEP_SLEEP_2: #ifdef CONFIG_ARC_INIT - _arc_init(NULL); + z_arc_init(NULL); #endif /* CONFIG_ARC_INIT */ /* Fallthrough */ case SYS_POWER_STATE_DEEP_SLEEP_1: diff --git a/soc/x86/intel_quark/quark_se/soc.c b/soc/x86/intel_quark/quark_se/soc.c index 334b339d477..ca236259a81 100644 --- a/soc/x86/intel_quark/quark_se/soc.c +++ b/soc/x86/intel_quark/quark_se/soc.c @@ -62,7 +62,7 @@ MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE); * @return N/A */ /* This function is also called at deep sleep resume. */ -int _arc_init(struct device *arg) +int z_arc_init(struct device *arg) { u32_t *reset_vector; @@ -108,7 +108,7 @@ skip_arc_init: return 0; } -SYS_INIT(_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +SYS_INIT(z_arc_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /*CONFIG_ARC_INIT*/ diff --git a/soc/x86/intel_quark/quark_se/soc.h b/soc/x86/intel_quark/quark_se/soc.h index adf2c021479..71500762fc3 100644 --- a/soc/x86/intel_quark/quark_se/soc.h +++ b/soc/x86/intel_quark/quark_se/soc.h @@ -84,7 +84,7 @@ #endif /* _ASMLANGUAGE */ #ifdef CONFIG_ARC_INIT -int _arc_init(struct device *arg); +int z_arc_init(struct device *arg); #endif /* CONFIG_ARC_INIT */ #endif /* __SOC_H_ */ diff --git a/soc/x86/intel_quark/quark_se/soc_power.S b/soc/x86/intel_quark/quark_se/soc_power.S index 9fda1c53f72..2fabdcc4912 100644 --- a/soc/x86/intel_quark/quark_se/soc_power.S +++ b/soc/x86/intel_quark/quark_se/soc_power.S @@ -11,10 +11,10 @@ GDATA(_pm_save_gdtr) GDATA(_pm_save_idtr) GDATA(_pm_save_esp) -GTEXT(_sys_resume_from_deep_sleep) -GTEXT(_power_restore_cpu_context) -GTEXT(_power_soc_sleep) -GTEXT(_power_soc_deep_sleep) +GTEXT(sys_resume_from_deep_sleep) +GTEXT(z_power_restore_cpu_context) +GTEXT(z_power_soc_sleep) +GTEXT(z_power_soc_deep_sleep) SECTION_FUNC(TEXT, save_cpu_context) movl %esp, %eax /* save ptr to return address */ @@ -43,7 +43,7 @@ SECTION_FUNC(TEXT, save_cpu_context) pushl (%eax) /* push return address */ ret -SECTION_FUNC(TEXT, _power_restore_cpu_context) +SECTION_FUNC(TEXT, z_power_restore_cpu_context) lgdtl _pm_save_gdtr /* restore gdtr */ lidtl _pm_save_idtr /* restore idtr */ movl _pm_save_esp, %esp /* restore saved stack ptr */ @@ -70,23 +70,23 @@ SECTION_FUNC(TEXT, _power_restore_cpu_context) * * Saved context * ESP ---> Return address of save_cpu_context - * Return address of _power_soc_sleep/deep_sleep + * Return address of z_power_soc_sleep/deep_sleep * * We just popped the saved context. Next we pop out the address * of the caller of save_cpu_context.Then the ret would return - * to caller of _power_soc_sleep or _power_soc_deep_sleep. + * to caller of z_power_soc_sleep or z_power_soc_deep_sleep. * */ addl $4, %esp ret -SECTION_FUNC(TEXT, _power_soc_sleep) +SECTION_FUNC(TEXT, z_power_soc_sleep) call save_cpu_context wbinvd call qm_power_soc_sleep /* Does not return */ -SECTION_FUNC(TEXT, _power_soc_deep_sleep) +SECTION_FUNC(TEXT, z_power_soc_deep_sleep) call save_cpu_context wbinvd call qm_power_soc_deep_sleep @@ -104,8 +104,8 @@ SECTION_FUNC(TEXT, _power_soc_deep_sleep) */ SECTION_FUNC(TEXT, _sys_resume_from_deep_sleep) movl $CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR, %eax - cmpl $_power_restore_cpu_context, (%eax) - je _power_restore_cpu_context + cmpl $z_power_restore_cpu_context, (%eax) + je z_power_restore_cpu_context ret #endif diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/esp32/esp32-mp.c index 55029b7a194..d700753d054 100644 --- a/soc/xtensa/esp32/esp32-mp.c +++ b/soc/xtensa/esp32/esp32-mp.c @@ -11,16 +11,16 @@ #include #include -#define _REG(base, off) (*(volatile u32_t *)((base) + (off))) +#define Z_REG(base, off) (*(volatile u32_t *)((base) + (off))) #define RTC_CNTL_BASE 0x3ff48000 -#define RTC_CNTL_OPTIONS0 _REG(RTC_CNTL_BASE, 0x0) -#define RTC_CNTL_SW_CPU_STALL _REG(RTC_CNTL_BASE, 0xac) +#define RTC_CNTL_OPTIONS0 Z_REG(RTC_CNTL_BASE, 0x0) +#define RTC_CNTL_SW_CPU_STALL Z_REG(RTC_CNTL_BASE, 0xac) #define DPORT_BASE 0x3ff00000 -#define DPORT_APPCPU_CTRL_A _REG(DPORT_BASE, 0x02C) -#define DPORT_APPCPU_CTRL_B _REG(DPORT_BASE, 0x030) -#define DPORT_APPCPU_CTRL_C _REG(DPORT_BASE, 0x034) +#define DPORT_APPCPU_CTRL_A Z_REG(DPORT_BASE, 0x02C) +#define DPORT_APPCPU_CTRL_B Z_REG(DPORT_BASE, 0x030) +#define DPORT_APPCPU_CTRL_C Z_REG(DPORT_BASE, 0x034) struct cpustart_rec { int cpu; @@ -103,10 +103,10 @@ static void appcpu_entry2(void) * set to zero for the called function (a null return value is the * signal for "top of stack" to the debugger). */ -void _appcpu_stack_switch(void *stack, void *entry); +void z_appcpu_stack_switch(void *stack, void *entry); __asm__("\n" ".align 4" "\n" - "_appcpu_stack_switch:" "\n\t" + "z_appcpu_stack_switch:" "\n\t" "entry a1, 16" "\n\t" @@ -153,7 +153,7 @@ __asm__("\n" */ static void appcpu_entry1(void) { - _appcpu_stack_switch(appcpu_top, appcpu_entry2); + z_appcpu_stack_switch(appcpu_top, appcpu_entry2); } /* The calls and sequencing here were extracted from the ESP-32