From fcdf31521f278c7989511efd85f8f1a2f04ac04d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Manuel=20Arg=C3=BCelles?= Date: Wed, 20 Sep 2023 16:05:52 +0700 Subject: [PATCH] tests: counter: enable RTU.PIT tests for s32z270dc2_r52 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable testing RTU.PIT on s32z270dc2_r52 boards. Signed-off-by: Manuel Argüelles --- .../counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay | 8 +++++++- .../counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay index 32e77ec10fe..d35e70e8a12 100644 --- a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,3 +23,9 @@ prescaler = <32>; status = "okay"; }; + +&pit0 { + pit-channel = <0>; + pit-period = <1000000>; + status = "okay"; +}; diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay index 32e77ec10fe..d35e70e8a12 100644 --- a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay +++ b/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,3 +23,9 @@ prescaler = <32>; status = "okay"; }; + +&pit0 { + pit-channel = <0>; + pit-period = <1000000>; + status = "okay"; +};