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dts: bindings: pll i2s for the stm32f412 has a Q divider

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There is a Q-divider factor [2..15] for the stm32f412 serie
which supplies the 48MHz clock.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-11-26 16:32:49 +01:00 • committed by Benjamin Cabé
commit fcc5f9dac1
2 changed files with 30 additions and 6 deletions
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20
dts/bindings/clock/st,stm32f411-plli2s-clock.yaml
View file

@ -24,3 +24,23 @@ properties:
description: | description: |
Division factor for the PLL input clock Division factor for the PLL input clock
Valid range: 2 - 63 Valid range: 2 - 63
div-q:
type: int
description: |
PLLI2S division factor for I2S Clocks to supply USB/SDIO/RNG
enum:
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
- 12
- 13
- 14
- 15

16
include/zephyr/dt-bindings/clock/stm32f4_clock.h
View file

@ -28,14 +28,18 @@
/* defined in stm32_common_clocks.h */ /* defined in stm32_common_clocks.h */
/** Fixed clocks */ /** Fixed clocks */
/* Low speed clocks defined in stm32_common_clocks.h */ /* Low speed clocks defined in stm32_common_clocks.h */
#define STM32_SRC_HSI (STM32_SRC_LSI + 1) #define STM32_SRC_HSI (STM32_SRC_LSI + 1)
#define STM32_SRC_HSE (STM32_SRC_HSI + 1) #define STM32_SRC_HSE (STM32_SRC_HSI + 1)
/** PLL clock outputs */ /** PLL clock outputs */
#define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) #define STM32_SRC_PLL_P (STM32_SRC_HSE + 1)
#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
/** I2S sources */ /** I2S sources */
#define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1) #define STM32_SRC_PLLI2S_Q (STM32_SRC_PLL_R + 1)
#define STM32_SRC_PLLI2S_R (STM32_SRC_PLLI2S_Q + 1)
/* CLK48MHz sources */
#define STM32_SRC_CK48 (STM32_SRC_PLLI2S_R + 1)
/* I2S_CKIN not supported yet */ /* I2S_CKIN not supported yet */
/* #define STM32_SRC_I2S_CKIN TBD */ /* #define STM32_SRC_I2S_CKIN TBD */