From fcaa259e22c2cbc555f242914ad3c8e4579f900a Mon Sep 17 00:00:00 2001
From: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Date: Fri, 30 Jun 2023 11:15:25 +0200
Subject: [PATCH] soc: arm: remove all unnecessary NMI_INIT() calls

NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
---
 soc/arm/arm/beetle/soc.c                 | 14 -------
 soc/arm/arm/designstart/CMakeLists.txt   |  4 --
 soc/arm/arm/designstart/soc.c            | 22 ----------
 soc/arm/arm/mps2/soc.c                   | 21 ----------
 soc/arm/arm/mps3/soc.c                   | 21 ----------
 soc/arm/arm/musca_b1/soc.c               | 21 ----------
 soc/arm/arm/musca_s1/CMakeLists.txt      |  4 --
 soc/arm/arm/musca_s1/soc.c               | 28 -------------
 soc/arm/atmel_sam/sam3x/soc.c            | 14 -------
 soc/arm/atmel_sam/sam4e/soc.c            | 15 -------
 soc/arm/atmel_sam/sam4l/soc.c            | 15 -------
 soc/arm/atmel_sam/sam4s/soc.c            | 15 -------
 soc/arm/atmel_sam/same70/soc.c           | 13 ------
 soc/arm/atmel_sam/samv71/soc.c           | 13 ------
 soc/arm/atmel_sam0/common/soc_samc2x.c   | 13 ------
 soc/arm/atmel_sam0/common/soc_samd2x.c   | 13 ------
 soc/arm/atmel_sam0/common/soc_samd5x.c   | 12 ------
 soc/arm/atmel_sam0/common/soc_saml2x.c   | 13 ------
 soc/arm/bcm_vk/valkyrie/CMakeLists.txt   |  3 --
 soc/arm/bcm_vk/valkyrie/soc.c            | 34 ----------------
 soc/arm/bcm_vk/viper/soc.c               |  9 ----
 soc/arm/gigadevice/gd32a50x/soc.c        | 10 +----
 soc/arm/gigadevice/gd32e10x/soc.c        |  9 ----
 soc/arm/gigadevice/gd32e50x/soc.c        | 10 +----
 soc/arm/gigadevice/gd32f3x0/soc.c        |  9 ----
 soc/arm/gigadevice/gd32f403/soc.c        | 10 +----
 soc/arm/gigadevice/gd32f4xx/soc.c        | 10 +----
 soc/arm/gigadevice/gd32l23x/soc.c        |  9 ----
 soc/arm/intel_socfpga_std/cyclonev/soc.c |  2 -
 soc/arm/nordic_nrf/nrf51/soc.c           | 21 ----------
 soc/arm/nordic_nrf/nrf52/soc.c           | 13 ------
 soc/arm/nordic_nrf/nrf53/soc.c           | 12 ------
 soc/arm/nordic_nrf/nrf91/soc.c           | 13 ------
 soc/arm/nxp_imx/mcimx6x_m4/soc.c         | 17 --------
 soc/arm/nxp_imx/rt/soc_rt10xx.c          | 15 -------
 soc/arm/nxp_imx/rt/soc_rt11xx.c          | 16 --------
 soc/arm/nxp_imx/rt5xx/soc.c              | 18 --------
 soc/arm/nxp_imx/rt6xx/soc.c              | 16 --------
 soc/arm/nxp_kinetis/k2x/soc.c            | 14 -------
 soc/arm/nxp_kinetis/k6x/soc.c            | 14 -------
 soc/arm/nxp_kinetis/k8x/soc.c            | 14 -------
 soc/arm/nxp_kinetis/ke1xf/soc.c          | 13 ------
 soc/arm/nxp_kinetis/kl2x/soc.c           | 14 -------
 soc/arm/nxp_kinetis/kv5x/soc.c           | 15 -------
 soc/arm/nxp_kinetis/kwx/soc_kw2xd.c      | 15 -------
 soc/arm/nxp_kinetis/kwx/soc_kw4xz.c      | 15 -------
 soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt  |  8 ----
 soc/arm/nxp_lpc/lpc11u6x/soc.c           | 52 ------------------------
 soc/arm/nxp_lpc/lpc54xxx/soc.c           | 17 --------
 soc/arm/nxp_lpc/lpc55xxx/soc.c           | 16 --------
 soc/arm/nxp_s32/s32ze/soc.c              |  6 ---
 soc/arm/quicklogic_eos_s3/soc.c          |  9 ----
 soc/arm/renesas_rcar/gen3/soc.c          | 20 ---------
 soc/arm/renesas_smartbond/da1469x/soc.c  |  4 --
 soc/arm/rpi_pico/rp2/soc.c               | 13 ------
 soc/arm/silabs_exx32/common/soc.c        | 15 -------
 soc/arm/st_stm32/stm32c0/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f0/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f1/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f2/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f3/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f4/soc.c           | 15 -------
 soc/arm/st_stm32/stm32f7/soc.c           | 15 -------
 soc/arm/st_stm32/stm32g0/soc.c           | 15 -------
 soc/arm/st_stm32/stm32g4/soc.c           | 15 -------
 soc/arm/st_stm32/stm32h5/soc.c           | 15 -------
 soc/arm/st_stm32/stm32h7/soc_m4.c        | 14 -------
 soc/arm/st_stm32/stm32h7/soc_m7.c        | 15 -------
 soc/arm/st_stm32/stm32l0/soc.c           | 15 -------
 soc/arm/st_stm32/stm32l1/soc.c           | 15 -------
 soc/arm/st_stm32/stm32l4/soc.c           | 15 -------
 soc/arm/st_stm32/stm32l5/soc.c           | 15 -------
 soc/arm/st_stm32/stm32mp1/soc.c          | 15 -------
 soc/arm/st_stm32/stm32u5/soc.c           | 15 -------
 soc/arm/st_stm32/stm32wb/soc.c           | 15 -------
 soc/arm/st_stm32/stm32wl/soc.c           | 15 -------
 soc/arm/ti_lm3s6965/CMakeLists.txt       |  1 -
 soc/arm/ti_lm3s6965/soc.c                | 43 --------------------
 soc/arm/xilinx_zynq7000/xc7zxxx/soc.c    | 19 ---------
 soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c   | 19 ---------
 soc/arm/xilinx_zynqmp/soc.c              | 20 ---------
 81 files changed, 4 insertions(+), 1198 deletions(-)
 delete mode 100644 soc/arm/arm/designstart/soc.c
 delete mode 100644 soc/arm/arm/musca_s1/soc.c
 delete mode 100644 soc/arm/bcm_vk/valkyrie/soc.c
 delete mode 100644 soc/arm/nxp_lpc/lpc11u6x/soc.c
 delete mode 100644 soc/arm/ti_lm3s6965/soc.c

diff --git a/soc/arm/arm/beetle/soc.c b/soc/arm/arm/beetle/soc.c
index c61e753b7ec..0cf8668a514 100644
--- a/soc/arm/arm/beetle/soc.c
+++ b/soc/arm/arm/beetle/soc.c
@@ -17,8 +17,6 @@
 #include <zephyr/init.h>
 #include <soc.h>
 
-#include <zephyr/arch/cpu.h>
-
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -32,21 +30,9 @@
  */
 static int arm_beetle_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	/* Setup various clocks and wakeup sources */
 	soc_power_init();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/arm/designstart/CMakeLists.txt b/soc/arm/arm/designstart/CMakeLists.txt
index 332416ba43b..9881313609a 100644
--- a/soc/arm/arm/designstart/CMakeLists.txt
+++ b/soc/arm/arm/designstart/CMakeLists.txt
@@ -1,5 +1 @@
 # SPDX-License-Identifier: Apache-2.0
-
-zephyr_sources(
-  soc.c
-  )
diff --git a/soc/arm/arm/designstart/soc.c b/soc/arm/arm/designstart/soc.c
deleted file mode 100644
index d914210277b..00000000000
--- a/soc/arm/arm/designstart/soc.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-
-static int arm_designstart_init(void)
-{
-
-	/*
-	 * Install default handler that simply resets the CPU if
-	 * configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(arm_designstart_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/arm/mps2/soc.c b/soc/arm/arm/mps2/soc.c
index 4b9659d72a8..76edaa388f5 100644
--- a/soc/arm/arm/mps2/soc.c
+++ b/soc/arm/arm/mps2/soc.c
@@ -7,9 +7,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/drivers/gpio/gpio_mmio32.h>
-#include <zephyr/init.h>
 #include <soc.h>
 #include <zephyr/linker/linker-defs.h>
 
@@ -70,22 +68,3 @@ uint32_t sse_200_platform_get_cpu_id(void)
 
 	return (uint32_t)*p_cpu_id;
 }
-
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * @return 0
- */
-static int arm_mps2_init(void)
-{
-
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(arm_mps2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/arm/mps3/soc.c b/soc/arm/arm/mps3/soc.c
index 86c7c2649bf..e51a9ba5c59 100644
--- a/soc/arm/arm/mps3/soc.c
+++ b/soc/arm/arm/mps3/soc.c
@@ -4,9 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/drivers/gpio/gpio_mmio32.h>
-#include <zephyr/init.h>
 #include <soc.h>
 #include <zephyr/linker/linker-defs.h>
 
@@ -24,22 +22,3 @@
 FPGAIO_INIT(0);
 FPGAIO_INIT(1);
 FPGAIO_INIT(2);
-
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * @return 0
- */
-static int arm_mps3_init(void)
-{
-
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(arm_mps3_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/arm/musca_b1/soc.c b/soc/arm/arm/musca_b1/soc.c
index 44d8d887d50..5e9f869c330 100644
--- a/soc/arm/arm/musca_b1/soc.c
+++ b/soc/arm/arm/musca_b1/soc.c
@@ -4,8 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/cpu.h>
-#include <zephyr/init.h>
 #include <soc.h>
 #include <zephyr/linker/linker-defs.h>
 
@@ -46,22 +44,3 @@ uint32_t sse_200_platform_get_cpu_id(void)
 
 	return (uint32_t)*p_cpu_id;
 }
-
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * @return 0
- */
-static int arm_musca_b1_init(void)
-{
-
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(arm_musca_b1_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/arm/musca_s1/CMakeLists.txt b/soc/arm/arm/musca_s1/CMakeLists.txt
index ae3f7d6c3be..2ceba388601 100644
--- a/soc/arm/arm/musca_s1/CMakeLists.txt
+++ b/soc/arm/arm/musca_s1/CMakeLists.txt
@@ -3,7 +3,3 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 #
-
-zephyr_sources(
-  soc.c
-  )
diff --git a/soc/arm/arm/musca_s1/soc.c b/soc/arm/arm/musca_s1/soc.c
deleted file mode 100644
index 7570678d1a3..00000000000
--- a/soc/arm/arm/musca_s1/soc.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2019-2020 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/cpu.h>
-#include <zephyr/init.h>
-#include <soc.h>
-
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * @return 0
- */
-static int arm_musca_s1_init(void)
-{
-
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise.
-	 */
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(arm_musca_s1_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c
index 891b205e195..fb4ef6db866 100644
--- a/soc/arm/atmel_sam/sam3x/soc.c
+++ b/soc/arm/atmel_sam/sam3x/soc.c
@@ -17,9 +17,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/irq.h>
 
 /*
  * PLL clock = Main * (MULA + 1) / DIVA
@@ -204,11 +202,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_sam3x_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock
 	 * (MCK) frequency.
@@ -221,13 +214,6 @@ static int atmel_sam3x_init(void)
 	/* Setup system clocks */
 	clock_init();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam/sam4e/soc.c b/soc/arm/atmel_sam/sam4e/soc.c
index 4407b2325d3..8c6f4965483 100644
--- a/soc/arm/atmel_sam/sam4e/soc.c
+++ b/soc/arm/atmel_sam/sam4e/soc.c
@@ -18,9 +18,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.
@@ -192,11 +190,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_sam4e_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock
 	 * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet.
@@ -210,14 +203,6 @@ static int atmel_sam4e_init(void)
 	/* Setup system clocks. */
 	clock_init();
 
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise.
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam/sam4l/soc.c b/soc/arm/atmel_sam/sam4l/soc.c
index 88427c990cd..9c67f99c6b6 100644
--- a/soc/arm/atmel_sam/sam4l/soc.c
+++ b/soc/arm/atmel_sam/sam4l/soc.c
@@ -14,8 +14,6 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
-#include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 
 /** Watchdog control register first write keys */
@@ -265,11 +263,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_sam4l_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 #if defined(CONFIG_WDT_DISABLE_AT_BOOT)
 	wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
 	while (WDT->CTRL & WDT_CTRL_EN) {
@@ -280,14 +273,6 @@ static int atmel_sam4l_init(void)
 	/* Setup system clocks. */
 	clock_init();
 
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise.
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c
index 395972549d7..d89363928e0 100644
--- a/soc/arm/atmel_sam/sam4s/soc.c
+++ b/soc/arm/atmel_sam/sam4s/soc.c
@@ -17,9 +17,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Setup various clock on SoC at boot time.
@@ -191,11 +189,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_sam4s_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	/*
 	 * Set FWS (Flash Wait State) value before increasing Master Clock
 	 * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet.
@@ -210,14 +203,6 @@ static int atmel_sam4s_init(void)
 	/* Setup system clocks. */
 	clock_init();
 
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise.
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c
index 5bded6490db..35913cb0fa4 100644
--- a/soc/arm/atmel_sam/same70/soc.c
+++ b/soc/arm/atmel_sam/same70/soc.c
@@ -16,7 +16,6 @@
 #include <soc.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/irq.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
@@ -234,11 +233,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_same70_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SCB_EnableICache();
 
 	if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
@@ -256,13 +250,6 @@ static int atmel_same70_init(void)
 	/* Setup system clocks */
 	clock_init();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Check that the CHIP CIDR matches the HAL one */
 	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
 		LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c
index 7f04c0bbb3c..94eeb7b07a8 100644
--- a/soc/arm/atmel_sam/samv71/soc.c
+++ b/soc/arm/atmel_sam/samv71/soc.c
@@ -17,7 +17,6 @@
 #include <soc.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/irq.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
@@ -235,11 +234,6 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int atmel_samv71_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SCB_EnableICache();
 
 	if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
@@ -257,13 +251,6 @@ static int atmel_samv71_init(void)
 	/* Setup system clocks */
 	clock_init();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Check that the CHIP CIDR matches the HAL one */
 	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
 		LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
diff --git a/soc/arm/atmel_sam0/common/soc_samc2x.c b/soc/arm/atmel_sam0/common/soc_samc2x.c
index 4eefe27af4d..6a0528309a5 100644
--- a/soc/arm/atmel_sam0/common/soc_samc2x.c
+++ b/soc/arm/atmel_sam0/common/soc_samc2x.c
@@ -9,7 +9,6 @@
  * @brief Atmel SAMC MCU series initialization code
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
@@ -45,23 +44,11 @@ static void gclks_init(void)
 
 static int atmel_samc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	flash_waitstates_init();
 	osc48m_init();
 	mclk_init();
 	gclks_init();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam0/common/soc_samd2x.c b/soc/arm/atmel_sam0/common/soc_samd2x.c
index 90c0d1b008d..33ef01192e5 100644
--- a/soc/arm/atmel_sam0/common/soc_samd2x.c
+++ b/soc/arm/atmel_sam0/common/soc_samd2x.c
@@ -21,7 +21,6 @@
  * GCLK Gen 3 -> ADC @ 8 MHz
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
@@ -257,11 +256,6 @@ static inline void osc8m_disable(void)
 
 static int atmel_samd_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	osc8m_init();
 	osc32k_init();
 	xosc_init();
@@ -272,13 +266,6 @@ static int atmel_samd_init(void)
 	gclk_adc_configure();
 	osc8m_disable();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam0/common/soc_samd5x.c b/soc/arm/atmel_sam0/common/soc_samd5x.c
index 557b4e55999..d50191f3c3f 100644
--- a/soc/arm/atmel_sam0/common/soc_samd5x.c
+++ b/soc/arm/atmel_sam0/common/soc_samd5x.c
@@ -9,7 +9,6 @@
  * @brief Atmel SAMD MCU series initialization code
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
@@ -107,7 +106,6 @@ static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
 
 static int atmel_samd_init(void)
 {
-	uint32_t key;
 	uint8_t dfll_div;
 
 	if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < SAM0_DFLL_FREQ_HZ) {
@@ -118,9 +116,6 @@ static int atmel_samd_init(void)
 		dfll_div = 1;
 	}
 
-
-	key = irq_lock();
-
 	/* enable the Cortex M Cache Controller */
 	CMCC->CTRL.bit.CEN = 1;
 
@@ -135,13 +130,6 @@ static int atmel_samd_init(void)
 	/* connect GCLK2 to 48 MHz DFLL for USB */
 	gclk_connect(2, GCLK_SOURCE_DFLL48M, 0);
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/arm/atmel_sam0/common/soc_saml2x.c
index 5e8d0a8061c..1914b221433 100644
--- a/soc/arm/atmel_sam0/common/soc_saml2x.c
+++ b/soc/arm/atmel_sam0/common/soc_saml2x.c
@@ -9,7 +9,6 @@
  * @brief Atmel SAML MCU series initialization code
  */
 
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
@@ -245,11 +244,6 @@ static inline void pause_for_debug(void) {}
 
 static int atmel_saml_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	pause_for_debug();
 
 	gclk_reset();
@@ -262,13 +256,6 @@ static int atmel_saml_init(void)
 	gclk_main_configure();
 	gclk_adc_configure();
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/bcm_vk/valkyrie/CMakeLists.txt b/soc/arm/bcm_vk/valkyrie/CMakeLists.txt
index 3b465dc7da8..f75aec6b311 100644
--- a/soc/arm/bcm_vk/valkyrie/CMakeLists.txt
+++ b/soc/arm/bcm_vk/valkyrie/CMakeLists.txt
@@ -1,6 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
-zephyr_sources(
-	soc.c
-)
diff --git a/soc/arm/bcm_vk/valkyrie/soc.c b/soc/arm/bcm_vk/valkyrie/soc.c
deleted file mode 100644
index bd5e025107c..00000000000
--- a/soc/arm/bcm_vk/valkyrie/soc.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: Apache-2.0 */
-/*
- * Copyright 2018 Broadcom.
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/arch/cpu.h>
-#include <zephyr/irq.h>
-
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
- */
-static int valkyrie_init(void)
-{
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	NMI_INIT();
-
-	irq_unlock(key);
-
-	return 0;
-}
-
-SYS_INIT(valkyrie_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/bcm_vk/viper/soc.c b/soc/arm/bcm_vk/viper/soc.c
index 49ee4a78ebe..d18d13ce884 100644
--- a/soc/arm/bcm_vk/viper/soc.c
+++ b/soc/arm/bcm_vk/viper/soc.c
@@ -8,7 +8,6 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -20,14 +19,8 @@
  */
 static int viper_init(void)
 {
-	uint32_t key;
 	uint32_t data;
 
-
-	key = irq_lock();
-
-	NMI_INIT();
-
 	/* pcie pmon lite init */
 	data = sys_read32(LS_ICFG_PMON_LITE_CLK_CTRL);
 	data |= PCIE_PMON_LITE_CLK_ENABLE;
@@ -37,8 +30,6 @@ static int viper_init(void)
 	data |= PCIE_PMON_LITE_SW_RESETN;
 	sys_write32(data, LS_ICFG_PMON_LITE_SW_RESETN);
 
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/gigadevice/gd32a50x/soc.c b/soc/arm/gigadevice/gd32a50x/soc.c
index 0a5033796c6..5f8024f7fd6 100644
--- a/soc/arm/gigadevice/gd32a50x/soc.c
+++ b/soc/arm/gigadevice/gd32a50x/soc.c
@@ -5,7 +5,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
+#include <soc.h>
 
 /* initial ecc memory */
 void z_arm_platform_init(void)
@@ -21,15 +21,7 @@ void z_arm_platform_init(void)
 
 static int gd32a50x_soc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32e10x/soc.c b/soc/arm/gigadevice/gd32e10x/soc.c
index 6958f5bb1c1..939af3492c8 100644
--- a/soc/arm/gigadevice/gd32e10x/soc.c
+++ b/soc/arm/gigadevice/gd32e10x/soc.c
@@ -5,20 +5,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <soc.h>
 
 static int gd32e10x_soc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32e50x/soc.c b/soc/arm/gigadevice/gd32e50x/soc.c
index e8731171d58..0bd63afaff5 100644
--- a/soc/arm/gigadevice/gd32e50x/soc.c
+++ b/soc/arm/gigadevice/gd32e50x/soc.c
@@ -4,19 +4,11 @@
  */
 
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
+#include <soc.h>
 
 static int gd32e50x_soc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32f3x0/soc.c b/soc/arm/gigadevice/gd32f3x0/soc.c
index 1f160d49595..ebf0e3fea35 100644
--- a/soc/arm/gigadevice/gd32f3x0/soc.c
+++ b/soc/arm/gigadevice/gd32f3x0/soc.c
@@ -5,20 +5,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <soc.h>
 
 static int gd32f3x0_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32f403/soc.c b/soc/arm/gigadevice/gd32f403/soc.c
index 2c5c0c5e037..2e52dd08508 100644
--- a/soc/arm/gigadevice/gd32f403/soc.c
+++ b/soc/arm/gigadevice/gd32f403/soc.c
@@ -13,7 +13,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
+#include <soc.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -25,15 +25,7 @@
  */
 static int gigadevice_gd32_soc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32f4xx/soc.c b/soc/arm/gigadevice/gd32f4xx/soc.c
index d7b189530a9..e096ba64b0b 100644
--- a/soc/arm/gigadevice/gd32f4xx/soc.c
+++ b/soc/arm/gigadevice/gd32f4xx/soc.c
@@ -5,19 +5,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
+#include <soc.h>
 
 static int gd32f4xx_soc_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/gigadevice/gd32l23x/soc.c b/soc/arm/gigadevice/gd32l23x/soc.c
index 89e8821be5a..38194133739 100644
--- a/soc/arm/gigadevice/gd32l23x/soc.c
+++ b/soc/arm/gigadevice/gd32l23x/soc.c
@@ -5,20 +5,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <soc.h>
 
 static int gd32l23x_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SystemInit();
-	NMI_INIT();
-
-	irq_unlock(key);
 
 	return 0;
 }
diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.c b/soc/arm/intel_socfpga_std/cyclonev/soc.c
index 3ae336ebe67..c00964600a4 100644
--- a/soc/arm/intel_socfpga_std/cyclonev/soc.c
+++ b/soc/arm/intel_socfpga_std/cyclonev/soc.c
@@ -13,7 +13,6 @@
 #include <mmu.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "soc.h"
 
 void arch_reserved_pages_update(void)
@@ -72,7 +71,6 @@ const struct arm_mmu_config mmu_config = {
  */
 static int soc_intel_cyclonev_init(void)
 {
-	NMI_INIT();
 	unsigned int sctlr = __get_SCTLR(); /* modifying some registers prior to initialization */
 
 	sctlr &= ~SCTLR_A_Msk;
diff --git a/soc/arm/nordic_nrf/nrf51/soc.c b/soc/arm/nordic_nrf/nrf51/soc.c
index a3cfe2ededf..078a422c06b 100644
--- a/soc/arm/nordic_nrf/nrf51/soc.c
+++ b/soc/arm/nordic_nrf/nrf51/soc.c
@@ -14,8 +14,6 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/init.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <hal/nrf_power.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
@@ -36,23 +34,6 @@ void sys_arch_reboot(int type)
 }
 #endif
 
-static int nordicsemi_nrf51_init(void)
-{
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
-	return 0;
-}
-
 #define DELAY_CALL_OVERHEAD_US 2
 
 void arch_busy_wait(uint32_t time_us)
@@ -64,5 +45,3 @@ void arch_busy_wait(uint32_t time_us)
 	time_us -= DELAY_CALL_OVERHEAD_US;
 	nrfx_coredep_delay_us(time_us);
 }
-
-SYS_INIT(nordicsemi_nrf51_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/arm/nordic_nrf/nrf52/soc.c
index 2c8bd51c657..fe610a1aa45 100644
--- a/soc/arm/nordic_nrf/nrf52/soc.c
+++ b/soc/arm/nordic_nrf/nrf52/soc.c
@@ -15,7 +15,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <hal/nrf_power.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
@@ -38,11 +37,6 @@ void sys_arch_reboot(int type)
 
 static int nordicsemi_nrf52_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 #ifdef CONFIG_NRF_ENABLE_ICACHE
 	/* Enable the instruction cache */
 	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
@@ -55,13 +49,6 @@ static int nordicsemi_nrf52_init(void)
 	nrf_power_dcdcen_vddh_set(NRF_POWER, true);
 #endif
 
-	/* Install default handler that simply resets the CPU
-	* if configured in the kernel, NOP otherwise
-	*/
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/nordic_nrf/nrf53/soc.c b/soc/arm/nordic_nrf/nrf53/soc.c
index 7f8e1b5ba81..be2c36c3bbe 100644
--- a/soc/arm/nordic_nrf/nrf53/soc.c
+++ b/soc/arm/nordic_nrf/nrf53/soc.c
@@ -15,7 +15,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 #include <nrf_erratas.h>
@@ -144,10 +143,6 @@ bool z_arm_on_enter_cpu_idle(void)
 
 static int nordicsemi_nrf53_init(void)
 {
-	uint32_t key;
-
-	key = irq_lock();
-
 #if defined(CONFIG_SOC_NRF5340_CPUAPP) && defined(CONFIG_NRF_ENABLE_CACHE)
 #if !defined(CONFIG_BUILD_WITH_TFM)
 	/* Enable the instruction & data cache.
@@ -237,13 +232,6 @@ static int nordicsemi_nrf53_init(void)
 	enable_ram_retention();
 #endif /* CONFIG_PM_S2RAM */
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/arm/nordic_nrf/nrf91/soc.c
index e1938cbf9ce..500d26ee76b 100644
--- a/soc/arm/nordic_nrf/nrf91/soc.c
+++ b/soc/arm/nordic_nrf/nrf91/soc.c
@@ -15,7 +15,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <soc/nrfx_coredep.h>
 #include <zephyr/logging/log.h>
 
@@ -24,23 +23,11 @@ LOG_MODULE_REGISTER(soc);
 
 static int nordicsemi_nrf91_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 #ifdef CONFIG_NRF_ENABLE_ICACHE
 	/* Enable the instruction cache */
 	NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
 #endif
 
-	/* Install default handler that simply resets the CPU
-	* if configured in the kernel, NOP otherwise
-	*/
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
index 3e664176da7..e9a3b1d4df6 100644
--- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c
+++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c
@@ -5,12 +5,10 @@
  */
 
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "wdog_imx.h"
 
 /* Initialize Resource Domain Controller. */
@@ -288,12 +286,6 @@ static void SOC_ClockInit(void)
  */
 static int mcimx6x_m4_init(void)
 {
-
-	unsigned int oldLevel; /* Old interrupt lock level */
-
-	/* Disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Configure RDC */
 	SOC_RdcInit();
 
@@ -306,15 +298,6 @@ static int mcimx6x_m4_init(void)
 	/* Initialize clock */
 	SOC_ClockInit();
 
-	/*
-	 * Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* Restore interrupt state */
-	irq_unlock(oldLevel);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c
index 26d00952ffd..d02046884a1 100644
--- a/soc/arm/nxp_imx/rt/soc_rt10xx.c
+++ b/soc/arm/nxp_imx/rt/soc_rt10xx.c
@@ -11,7 +11,6 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
@@ -306,12 +305,6 @@ void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
 
 static int imxrt_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 #ifndef CONFIG_IMXRT1XXX_CODE_CACHE
 	/* SystemInit enables code cache, disable it here */
 	SCB_DisableICache();
@@ -333,14 +326,6 @@ static int imxrt_init(void)
 	/* Initialize system clock */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c
index 9a4ec19d9c9..a308c5ac994 100644
--- a/soc/arm/nxp_imx/rt/soc_rt11xx.c
+++ b/soc/arm/nxp_imx/rt/soc_rt11xx.c
@@ -14,7 +14,6 @@
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
 #include <fsl_dcdc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
 #include <fsl_flexspi_nor_boot.h>
@@ -630,13 +629,6 @@ void imxrt_post_init_display_interface(void)
 
 static int imxrt_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
-
 #if  defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7)
 	/**
 	 * Copy CM4 core from flash to memory. Note that depending on where the
@@ -684,14 +676,6 @@ static int imxrt_init(void)
 	/* Initialize system clock */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/rt5xx/soc.c b/soc/arm/nxp_imx/rt5xx/soc.c
index 5dba2a28481..2fbb7d609b3 100644
--- a/soc/arm/nxp_imx/rt5xx/soc.c
+++ b/soc/arm/nxp_imx/rt5xx/soc.c
@@ -12,10 +12,8 @@
  * hardware for the RT5XX platforms.
  */
 
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <zephyr/init.h>
 #include <zephyr/devicetree.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/sections.h>
 #include <soc.h>
 #include "fsl_power.h"
@@ -472,29 +470,13 @@ void imxrt_post_init_display_interface(void)
  */
 static int nxp_rt500_init(void)
 {
-
-	/* old interrupt lock level */
-	unsigned int oldLevel;
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Initialize clocks with tool generated code */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU if configured in
-	 * the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 #ifndef CONFIG_IMXRT5XX_CODE_CACHE
 	CACHE64_DisableCache(CACHE64_CTRL0);
 #endif
 
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c
index 6f07a8a7952..b691187c865 100644
--- a/soc/arm/nxp_imx/rt6xx/soc.c
+++ b/soc/arm/nxp_imx/rt6xx/soc.c
@@ -352,29 +352,13 @@ void imxrt_usdhc_dat3_pull(bool pullup)
 
 static int nxp_rt600_init(void)
 {
-
-	/* old interrupt lock level */
-	unsigned int oldLevel;
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Initialize clock */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU if configured in
-	 * the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 #ifndef CONFIG_IMXRT6XX_CODE_CACHE
 	CACHE64_DisableCache(CACHE64);
 #endif
 
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/k2x/soc.c b/soc/arm/nxp_kinetis/k2x/soc.c
index 657d58a2734..dedb1367060 100644
--- a/soc/arm/nxp_kinetis/k2x/soc.c
+++ b/soc/arm/nxp_kinetis/k2x/soc.c
@@ -118,26 +118,12 @@ static ALWAYS_INLINE void clock_init(void)
 
 static int fsl_frdm_k22f_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
 	/* Initialize PLL/system clock to 120 MHz */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/arm/nxp_kinetis/k6x/soc.c
index 75a179477ce..1464df9a327 100644
--- a/soc/arm/nxp_kinetis/k6x/soc.c
+++ b/soc/arm/nxp_kinetis/k6x/soc.c
@@ -20,7 +20,6 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 #define LPUART0SRC_OSCERCLK     (1)
@@ -129,15 +128,10 @@ static ALWAYS_INLINE void clock_init(void)
 
 static int k6x_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
 #if !defined(CONFIG_ARM_MPU)
 	uint32_t temp_reg;
 #endif /* !CONFIG_ARM_MPU */
 
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
@@ -168,14 +162,6 @@ static int k6x_init(void)
 	/* Initialize PLL/system clock up to 180 MHz */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/k8x/soc.c b/soc/arm/nxp_kinetis/k8x/soc.c
index 4f5c7c8f525..50fa7c1b109 100644
--- a/soc/arm/nxp_kinetis/k8x/soc.c
+++ b/soc/arm/nxp_kinetis/k8x/soc.c
@@ -94,15 +94,10 @@ static ALWAYS_INLINE void clk_init(void)
 
 static int k8x_init(void)
 {
-
-	unsigned int old_level; /* old interrupt lock level */
 #if !defined(CONFIG_ARM_MPU)
 	uint32_t temp_reg;
 #endif /* !CONFIG_ARM_MPU */
 
-	/* Disable interrupts */
-	old_level = irq_lock();
-
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
@@ -122,15 +117,6 @@ static int k8x_init(void)
 	/* Initialize system clocks and PLL */
 	clk_init();
 
-	/*
-	 * Install default handler that simply resets the CPU if
-	 * configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* Restore interrupt state */
-	irq_unlock(old_level);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.c b/soc/arm/nxp_kinetis/ke1xf/soc.c
index 40967fb5551..b48ed1a8886 100644
--- a/soc/arm/nxp_kinetis/ke1xf/soc.c
+++ b/soc/arm/nxp_kinetis/ke1xf/soc.c
@@ -240,15 +240,10 @@ static ALWAYS_INLINE void clk_init(void)
 static int ke1xf_init(void)
 
 {
-
-	unsigned int old_level; /* old interrupt lock level */
 #if !defined(CONFIG_ARM_MPU)
 	uint32_t temp_reg;
 #endif /* !CONFIG_ARM_MPU */
 
-	/* Disable interrupts */
-	old_level = irq_lock();
-
 #if !defined(CONFIG_ARM_MPU)
 	/*
 	 * Disable memory protection and clear slave port errors.
@@ -265,18 +260,10 @@ static int ke1xf_init(void)
 	/* Initialize system clocks and PLL */
 	clk_init();
 
-	/*
-	 * Install default handler that simply resets the CPU if
-	 * configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 #ifndef CONFIG_KINETIS_KE1XF_ENABLE_CODE_CACHE
 	/* SystemInit will have enabled the code cache. Disable it here */
 	L1CACHE_DisableCodeCache();
 #endif
-	/* Restore interrupt state */
-	irq_unlock(old_level);
 
 	return 0;
 }
diff --git a/soc/arm/nxp_kinetis/kl2x/soc.c b/soc/arm/nxp_kinetis/kl2x/soc.c
index 36224253781..3bb71d03e14 100644
--- a/soc/arm/nxp_kinetis/kl2x/soc.c
+++ b/soc/arm/nxp_kinetis/kl2x/soc.c
@@ -81,23 +81,9 @@ static ALWAYS_INLINE void clock_init(void)
 
 static int kl2x_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Initialize system clock to 48 MHz */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/kv5x/soc.c b/soc/arm/nxp_kinetis/kv5x/soc.c
index b8339344ad8..4c566dadcd0 100644
--- a/soc/arm/nxp_kinetis/kv5x/soc.c
+++ b/soc/arm/nxp_kinetis/kv5x/soc.c
@@ -79,12 +79,6 @@ static ALWAYS_INLINE void clk_init(void)
 
 static int kv5x_init(void)
 {
-
-	unsigned int old_level; /* old interrupt lock level */
-
-	/* Disable interrupts */
-	old_level = irq_lock();
-
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
@@ -96,12 +90,6 @@ static int kv5x_init(void)
 	/* Initialize system clocks and PLL */
 	clk_init();
 
-	/*
-	 * Install default handler that simply resets the CPU if
-	 * configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 #ifndef CONFIG_KINETIS_KV5X_ENABLE_CODE_CACHE
 	/* SystemInit will have enabled the code cache. Disable it here */
 	SCB_DisableICache();
@@ -111,9 +99,6 @@ static int kv5x_init(void)
 	SCB_DisableDCache();
 #endif
 
-	/* Restore interrupt state */
-	irq_unlock(old_level);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
index c872e95e7fb..eaecced4ae1 100644
--- a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
+++ b/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c
@@ -13,7 +13,6 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 
 #define PLLFLLSEL_MCGFLLCLK	(0)
@@ -149,26 +148,12 @@ static ALWAYS_INLINE void clock_init(void)
  */
 static int kw2xd_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* release I/O power hold to allow normal run state */
 	PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
 
 	/* Initialize PLL/system clock to 48 MHz */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c b/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c
index b178a30004b..f9d4845eb27 100644
--- a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c
+++ b/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c
@@ -11,7 +11,6 @@
 #include <zephyr/drivers/uart.h>
 #include <fsl_common.h>
 #include <fsl_clock.h>
-#include <zephyr/arch/cpu.h>
 
 #define LPUART0SRC_OSCERCLK	(1)
 #define TPMSRC_MCGPLLCLK	(1)
@@ -82,23 +81,9 @@ static ALWAYS_INLINE void clock_init(void)
 
 static int kwx_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Initialize system clock to 40 MHz */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt b/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt
index 88cafc9bc72..84686ad59cd 100644
--- a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt
+++ b/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt
@@ -3,11 +3,3 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 #
-zephyr_library()
-
-zephyr_library_sources(soc.c)
-
-zephyr_library_include_directories(
-  ${ZEPHYR_BASE}/kernel/include
-  ${ZEPHYR_BASE}/arch/${ARCH}/include
-  )
diff --git a/soc/arm/nxp_lpc/lpc11u6x/soc.c b/soc/arm/nxp_lpc/lpc11u6x/soc.c
deleted file mode 100644
index 8e2b8d3984b..00000000000
--- a/soc/arm/nxp_lpc/lpc11u6x/soc.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2020, Seagate
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief System/hardware module for nxp_lpc11u6x platform
- *
- * This module provides routines to initialize and support board-level
- * hardware for the nxp_lpc11u6x platform.
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/linker/sections.h>
-#include <zephyr/arch/cpu.h>
-#include <aarch32/cortex_m/exc.h>
-
-/**
- *
- * @brief Perform basic hardware initialization
- *
- * Initialize the interrupt controller device drivers.
- * Also initialize the timer device driver, if required.
- *
- * @return 0
- */
-
-static int nxp_lpc11u6x_init(void)
-{
-
-	/* old interrupt lock level */
-	unsigned int old_level;
-
-	/* disable interrupts */
-	old_level = irq_lock();
-
-	/* install default handler that simply resets the CPU if configured in
-	 * the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(old_level);
-
-	return 0;
-}
-SYS_INIT(nxp_lpc11u6x_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c
index 3625f580d4b..df7e5ac1c06 100644
--- a/soc/arm/nxp_lpc/lpc54xxx/soc.c
+++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c
@@ -18,7 +18,6 @@
 #include <soc.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/linker/sections.h>
-#include <zephyr/arch/cpu.h>
 #include <aarch32/cortex_m/exc.h>
 #include <fsl_power.h>
 #include <fsl_clock.h>
@@ -109,13 +108,6 @@ static ALWAYS_INLINE void clock_init(void)
 
 static int nxp_lpc54114_init(void)
 {
-
-	/* old interrupt lock level */
-	unsigned int oldLevel;
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* Initialize FRO/system clock to 48 MHz */
 	clock_init();
 
@@ -124,15 +116,6 @@ static int nxp_lpc54114_init(void)
 	PINT_Init(PINT);
 #endif
 
-	/*
-	 * install default handler that simply resets the CPU if configured in
-	 * the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c
index ba7a55a1335..45c51d18424 100644
--- a/soc/arm/nxp_lpc/lpc55xxx/soc.c
+++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c
@@ -297,13 +297,6 @@ DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
 
 static int nxp_lpc55xxx_init(void)
 {
-
-	/* old interrupt lock level */
-	unsigned int oldLevel;
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	z_arm_clear_faults();
 
 	/* Initialize FRO/system clock to 96 MHz */
@@ -314,15 +307,6 @@ static int nxp_lpc55xxx_init(void)
 	PINT_Init(PINT);
 #endif
 
-	/*
-	 * install default handler that simply resets the CPU if configured in
-	 * the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
-
 	return 0;
 }
 
diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/arm/nxp_s32/s32ze/soc.c
index 0c79067ce41..5e242d413ae 100644
--- a/soc/arm/nxp_s32/s32ze/soc.c
+++ b/soc/arm/nxp_s32/s32ze/soc.c
@@ -45,12 +45,6 @@ void z_arm_platform_init(void)
 
 static int soc_init(void)
 {
-
-	/* Install default handler that simply resets the CPU if configured in the
-	 * kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 	OsIf_Init(NULL);
 
 #ifdef CONFIG_INIT_CLOCK_AT_BOOT_TIME
diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/arm/quicklogic_eos_s3/soc.c
index 56f7323db99..81d070df427 100644
--- a/soc/arm/quicklogic_eos_s3/soc.c
+++ b/soc/arm/quicklogic_eos_s3/soc.c
@@ -66,9 +66,6 @@ static void eos_s3_cru_init(void)
 
 static int eos_s3_init(void)
 {
-	uint32_t key;
-
-
 	/* Clocks setup */
 	eos_s3_lock_enable();
 	eos_s3_cru_init();
@@ -82,12 +79,6 @@ static int eos_s3_init(void)
 	/* Enable UART interrupt */
 	INTR_CTRL->OTHER_INTR_EN_M4 = UART_INTR_EN_M4;
 
-	key = irq_lock();
-
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/renesas_rcar/gen3/soc.c b/soc/arm/renesas_rcar/gen3/soc.c
index 29b7acf0acb..9dc79e0394d 100644
--- a/soc/arm/renesas_rcar/gen3/soc.c
+++ b/soc/arm/renesas_rcar/gen3/soc.c
@@ -7,26 +7,8 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
-#include <zephyr/init.h>
 #include <zephyr/sys/barrier.h>
 
-/**
- *
- * @brief Perform basic hardware initialization
- *
- * @return 0
- */
-
-static int soc_init(void)
-{
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-	return 0;
-}
-
 void z_arm_platform_init(void)
 {
 	L1C_DisableCaches();
@@ -40,5 +22,3 @@ void z_arm_platform_init(void)
 	L1C_EnableCaches();
 	L1C_EnableBTAC();
 }
-
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/arm/renesas_smartbond/da1469x/soc.c
index b353b10ef1c..7bef1f9fdf2 100644
--- a/soc/arm/renesas_smartbond/da1469x/soc.c
+++ b/soc/arm/renesas_smartbond/da1469x/soc.c
@@ -6,7 +6,6 @@
 
 #include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
@@ -110,9 +109,6 @@ void z_arm_platform_init(void)
 
 static int renesas_da14699_init(void)
 {
-
-	NMI_INIT();
-
 	/* Freeze watchdog until configured */
 	GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
 	/* Reset clock dividers to 0 */
diff --git a/soc/arm/rpi_pico/rp2/soc.c b/soc/arm/rpi_pico/rp2/soc.c
index 8af2f884a52..d953436f77e 100644
--- a/soc/arm/rpi_pico/rp2/soc.c
+++ b/soc/arm/rpi_pico/rp2/soc.c
@@ -15,7 +15,6 @@
 
 #include <stdio.h>
 
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 #include <zephyr/logging/log.h>
@@ -29,8 +28,6 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
 static int rp2040_init(void)
 {
-	uint32_t key;
-
 	reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS |
 		      RESETS_RESET_PLL_USB_BITS | RESETS_RESET_PLL_SYS_BITS));
 
@@ -44,16 +41,6 @@ static int rp2040_init(void)
 
 	unreset_block_wait(RESETS_RESET_BITS);
 
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	return 0;
 }
 
diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c
index 9ce5ff859ca..c2e152aec08 100644
--- a/soc/arm/silabs_exx32/common/soc.c
+++ b/soc/arm/silabs_exx32/common/soc.c
@@ -10,7 +10,6 @@
  */
 
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -209,12 +208,6 @@ static void swo_init(void)
  */
 static int silabs_exx32_init(void)
 {
-
-	unsigned int oldLevel; /* old interrupt lock level */
-
-	/* disable interrupts */
-	oldLevel = irq_lock();
-
 	/* handle chip errata */
 	CHIP_Init();
 
@@ -242,20 +235,12 @@ static int silabs_exx32_init(void)
 	/* Initialize system clock according to CONFIG_CMU settings */
 	clock_init();
 
-	/*
-	 * install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
 #ifdef CONFIG_LOG_BACKEND_SWO
 	/* Configure SWO debug output */
 	swo_init();
 #endif
 #endif /* !CONFIG_SOC_GECKO_DEV_INIT */
 
-	/* restore interrupt state */
-	irq_unlock(oldLevel);
 	return 0;
 }
 
diff --git a/soc/arm/st_stm32/stm32c0/soc.c b/soc/arm/st_stm32/stm32c0/soc.c
index 4bff4d055e3..14ad99a278d 100644
--- a/soc/arm/st_stm32/stm32c0/soc.c
+++ b/soc/arm/st_stm32/stm32c0/soc.c
@@ -11,10 +11,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
@@ -28,18 +25,6 @@
  */
 static int stm32c0_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 48 MHz from HSI */
 	SystemCoreClock = 48000000;
diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/arm/st_stm32/stm32f0/soc.c
index c5bb64ece30..a59e9214203 100644
--- a/soc/arm/st_stm32/stm32f0/soc.c
+++ b/soc/arm/st_stm32/stm32f0/soc.c
@@ -12,10 +12,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
@@ -69,18 +66,6 @@ void relocate_vector_table(void)
  */
 static int stm32f0_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/arm/st_stm32/stm32f1/soc.c
index e5f77d47234..b4f034dbc25 100644
--- a/soc/arm/st_stm32/stm32f1/soc.c
+++ b/soc/arm/st_stm32/stm32f1/soc.c
@@ -11,10 +11,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -26,18 +23,6 @@
  */
 static int stm32f1_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/arm/st_stm32/stm32f2/soc.c
index 4f6b1a39735..89e711b62c4 100644
--- a/soc/arm/st_stm32/stm32f2/soc.c
+++ b/soc/arm/st_stm32/stm32f2/soc.c
@@ -13,12 +13,9 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <stm32_ll_system.h>
 #include <zephyr/linker/linker-defs.h>
-#include <zephyr/irq.h>
 #include <string.h>
 
 /**
@@ -31,22 +28,10 @@
  */
 static int stm32f2_init(void)
 {
-	uint32_t key;
-
-
 	/* Enable ART Flash cache accelerator for both Instruction and Data */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
 
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/arm/st_stm32/stm32f3/soc.c
index dd357e6c182..97a29e35a8d 100644
--- a/soc/arm/st_stm32/stm32f3/soc.c
+++ b/soc/arm/st_stm32/stm32f3/soc.c
@@ -12,10 +12,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -27,18 +24,6 @@
  */
 static int stm32f3_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/arm/st_stm32/stm32f4/soc.c
index 616a513caee..66f1bb7e795 100644
--- a/soc/arm/st_stm32/stm32f4/soc.c
+++ b/soc/arm/st_stm32/stm32f4/soc.c
@@ -12,10 +12,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 #include <stm32_ll_system.h>
 
@@ -29,22 +26,10 @@
  */
 static int st_stm32f4_init(void)
 {
-	uint32_t key;
-
-
 	/* Enable ART Flash cache accelerator for both instruction and data */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
 
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/arm/st_stm32/stm32f7/soc.c
index c1768a884be..2f42610403c 100644
--- a/soc/arm/st_stm32/stm32f7/soc.c
+++ b/soc/arm/st_stm32/stm32f7/soc.c
@@ -13,10 +13,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <stm32_ll_system.h>
 
 /**
@@ -29,14 +26,9 @@
  */
 static int st_stm32f7_init(void)
 {
-	uint32_t key;
-
-
 	/* Enable ART Flash cache accelerator */
 	LL_FLASH_EnableART();
 
-	key = irq_lock();
-
 	SCB_EnableICache();
 
 	if (IS_ENABLED(CONFIG_DCACHE)) {
@@ -45,13 +37,6 @@ static int st_stm32f7_init(void)
 		}
 	}
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
diff --git a/soc/arm/st_stm32/stm32g0/soc.c b/soc/arm/st_stm32/stm32g0/soc.c
index 854737cb2d9..15a3f9b27fc 100644
--- a/soc/arm/st_stm32/stm32g0/soc.c
+++ b/soc/arm/st_stm32/stm32g0/soc.c
@@ -12,10 +12,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
@@ -83,18 +80,6 @@ static void stm32g0_disable_dead_battery(void)
  */
 static int stm32g0_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
diff --git a/soc/arm/st_stm32/stm32g4/soc.c b/soc/arm/st_stm32/stm32g4/soc.c
index 1ab0e8de383..ddc48c801f4 100644
--- a/soc/arm/st_stm32/stm32g4/soc.c
+++ b/soc/arm/st_stm32/stm32g4/soc.c
@@ -12,10 +12,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 #if defined(PWR_CR3_UCPD_DBDIS)
 #include <stm32_ll_bus.h>
@@ -32,18 +29,6 @@
  */
 static int stm32g4_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
diff --git a/soc/arm/st_stm32/stm32h5/soc.c b/soc/arm/st_stm32/stm32h5/soc.c
index 6b2b72ac73f..67a5075024e 100644
--- a/soc/arm/st_stm32/stm32h5/soc.c
+++ b/soc/arm/st_stm32/stm32h5/soc.c
@@ -14,10 +14,7 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -33,18 +30,6 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32h5_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Enable instruction cache in 1-way (direct mapped cache) */
 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
 	LL_ICACHE_Enable();
diff --git a/soc/arm/st_stm32/stm32h7/soc_m4.c b/soc/arm/st_stm32/stm32h7/soc_m4.c
index a7543a13171..7bd4a9ec0ec 100644
--- a/soc/arm/st_stm32/stm32h7/soc_m4.c
+++ b/soc/arm/st_stm32/stm32h7/soc_m4.c
@@ -12,16 +12,13 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "stm32_hsem.h"
 
 /**
@@ -34,22 +31,11 @@
  */
 static int stm32h7_m4_init(void)
 {
-	uint32_t key;
-
 	/* Enable ART Flash cache accelerator */
 	LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART);
 	LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash)));
 	LL_ART_Enable();
 
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* In case CM4 has not been forced boot by CM7,
 	 * CM4 needs to wait until CM7 has setup clock configuration
 	 */
diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/arm/st_stm32/stm32h7/soc_m7.c
index 2898fb3e109..46b871dfb90 100644
--- a/soc/arm/st_stm32/stm32h7/soc_m7.c
+++ b/soc/arm/st_stm32/stm32h7/soc_m7.c
@@ -12,15 +12,12 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/irq.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "stm32_hsem.h"
 
 #if defined(CONFIG_STM32H7_DUAL_CORE)
@@ -56,11 +53,6 @@ static int stm32h7_m4_wakeup(void)
  */
 static int stm32h7_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
 	SCB_EnableICache();
 
 	if (IS_ENABLED(CONFIG_DCACHE)) {
@@ -69,13 +61,6 @@ static int stm32h7_init(void)
 		}
 	}
 
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 64 MHz from HSI */
 	SystemCoreClock = 64000000;
diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/arm/st_stm32/stm32l0/soc.c
index e8f2bc81a1e..247a61d1333 100644
--- a/soc/arm/st_stm32/stm32l0/soc.c
+++ b/soc/arm/st_stm32/stm32l0/soc.c
@@ -11,10 +11,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
@@ -31,18 +28,6 @@
  */
 static int stm32l0_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 2.1 MHz from MSI */
 	SystemCoreClock = 2097152;
diff --git a/soc/arm/st_stm32/stm32l1/soc.c b/soc/arm/st_stm32/stm32l1/soc.c
index 00d9f662ff4..20b3af7f3d7 100644
--- a/soc/arm/st_stm32/stm32l1/soc.c
+++ b/soc/arm/st_stm32/stm32l1/soc.c
@@ -11,10 +11,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 #include <stm32_ll_bus.h>
@@ -30,18 +27,6 @@
  */
 static int stm32l1_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 2.1 MHz from MSI */
 	SystemCoreClock = 2097000;
diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/arm/st_stm32/stm32l4/soc.c
index 7bb37722384..61cf5e6d36a 100644
--- a/soc/arm/st_stm32/stm32l4/soc.c
+++ b/soc/arm/st_stm32/stm32l4/soc.c
@@ -12,10 +12,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -32,18 +29,6 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32l4_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
diff --git a/soc/arm/st_stm32/stm32l5/soc.c b/soc/arm/st_stm32/stm32l5/soc.c
index 1db1bf0411a..fb7b956d72d 100644
--- a/soc/arm/st_stm32/stm32l5/soc.c
+++ b/soc/arm/st_stm32/stm32l5/soc.c
@@ -13,10 +13,7 @@
 #include <zephyr/init.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <stm32l5xx_ll_icache.h>
 #include <zephyr/logging/log.h>
 
@@ -33,23 +30,11 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32l5_init(void)
 {
-	uint32_t key;
-
-
 	/* Enable ICACHE */
 	while (LL_ICACHE_IsActiveFlag_BUSY()) {
 	}
 	LL_ICACHE_Enable();
 
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
diff --git a/soc/arm/st_stm32/stm32mp1/soc.c b/soc/arm/st_stm32/stm32mp1/soc.c
index 35d8155ab88..fc95eab56ad 100644
--- a/soc/arm/st_stm32/stm32mp1/soc.c
+++ b/soc/arm/st_stm32/stm32mp1/soc.c
@@ -14,10 +14,7 @@
 #include <zephyr/init.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -29,18 +26,6 @@
  */
 static int stm32m4_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/*HW semaphore Clock enable*/
 	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
 
diff --git a/soc/arm/st_stm32/stm32u5/soc.c b/soc/arm/st_stm32/stm32u5/soc.c
index ddd1f304a8f..a775a1d2000 100644
--- a/soc/arm/st_stm32/stm32u5/soc.c
+++ b/soc/arm/st_stm32/stm32u5/soc.c
@@ -14,10 +14,7 @@
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_icache.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -33,18 +30,6 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32u5_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Enable instruction cache in 1-way (direct mapped cache) */
 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
 	LL_ICACHE_Enable();
diff --git a/soc/arm/st_stm32/stm32wb/soc.c b/soc/arm/st_stm32/stm32wb/soc.c
index af45930da29..3fd07aefb97 100644
--- a/soc/arm/st_stm32/stm32wb/soc.c
+++ b/soc/arm/st_stm32/stm32wb/soc.c
@@ -11,11 +11,8 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/irq.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
@@ -30,18 +27,6 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32wb_init(void)
 {
-	uint32_t key;
-
-
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
diff --git a/soc/arm/st_stm32/stm32wl/soc.c b/soc/arm/st_stm32/stm32wl/soc.c
index 4524a726626..928f97429c5 100644
--- a/soc/arm/st_stm32/stm32wl/soc.c
+++ b/soc/arm/st_stm32/stm32wl/soc.c
@@ -11,10 +11,7 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
-#include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
-#include <zephyr/irq.h>
 
 #include <stm32wlxx_ll_system.h>
 
@@ -34,22 +31,10 @@ LOG_MODULE_REGISTER(soc);
  */
 static int stm32wl_init(void)
 {
-	uint32_t key;
-
-
 	/* Enable CPU data and instruction cache */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
 
-	key = irq_lock();
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-
-	irq_unlock(key);
-
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
diff --git a/soc/arm/ti_lm3s6965/CMakeLists.txt b/soc/arm/ti_lm3s6965/CMakeLists.txt
index 1701f41c83f..c5f6f41f49a 100644
--- a/soc/arm/ti_lm3s6965/CMakeLists.txt
+++ b/soc/arm/ti_lm3s6965/CMakeLists.txt
@@ -3,7 +3,6 @@
 zephyr_library()
 
 zephyr_library_sources(
-  soc.c
   soc_config.c
   reboot.S
   sys_arch_reboot.c
diff --git a/soc/arm/ti_lm3s6965/soc.c b/soc/arm/ti_lm3s6965/soc.c
deleted file mode 100644
index 596dd9d7569..00000000000
--- a/soc/arm/ti_lm3s6965/soc.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2013-2015 Wind River Systems, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief System/hardware module for ti_lm3s6965 platform
- *
- * This module provides routines to initialize and support board-level hardware
- * for the ti_lm3s6965 platform.
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-
-#include <zephyr/arch/cpu.h>
-
-/**
- *
- * @brief Perform basic hardware initialization
- *
- * Initialize the interrupt controller device drivers and the
- * integrated 16550-compatible UART device driver.
- * Also initialize the timer device driver, if required.
- *
- * @return 0
- */
-
-static int ti_lm3s6965_init(void)
-{
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-	return 0;
-}
-
-SYS_INIT(ti_lm3s6965_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
index ef00fda9c09..253bd31c83c 100644
--- a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
+++ b/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c
@@ -6,13 +6,11 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
-#include <zephyr/init.h>
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "soc.h"
 
 /* System Level Control Registers (SLCR) */
@@ -71,23 +69,6 @@ const struct arm_mmu_config mmu_config = {
 	.mmu_regions = mmu_regions,
 };
 
-/**
- * @brief Basic hardware initialization of the Zynq-7000 SoC
- *
- * Performs the basic initialization of the Zynq-7000 SoC.
- *
- * @return 0
- */
-static int soc_xlnx_zynq7000_init(void)
-{
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(soc_xlnx_zynq7000_init, PRE_KERNEL_1,
-	CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
 /* Platform-specific early initialization */
 
 void z_arm_platform_init(void)
diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
index 1d3c24d1e73..f3b1137cb28 100644
--- a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
+++ b/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c
@@ -6,13 +6,11 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
-#include <zephyr/init.h>
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
-#include <zephyr/arch/arm/aarch32/nmi.h>
 #include "soc.h"
 
 /* System Level Configuration Registers */
@@ -71,23 +69,6 @@ const struct arm_mmu_config mmu_config = {
 	.mmu_regions = mmu_regions,
 };
 
-/**
- * @brief Basic hardware initialization of the Zynq-7000 SoC
- *
- * Performs the basic initialization of the Zynq-7000 SoC.
- *
- * @return 0
- */
-static int soc_xlnx_zynq7000s_init(void)
-{
-	NMI_INIT();
-
-	return 0;
-}
-
-SYS_INIT(soc_xlnx_zynq7000s_init, PRE_KERNEL_1,
-	CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
 /* Platform-specific early initialization */
 
 void z_arm_platform_init(void)
diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/arm/xilinx_zynqmp/soc.c
index 3073869e084..f84dc48f74e 100644
--- a/soc/arm/xilinx_zynqmp/soc.c
+++ b/soc/arm/xilinx_zynqmp/soc.c
@@ -7,28 +7,8 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
-#include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 
-/**
- *
- * @brief Perform basic hardware initialization
- *
- * @return 0
- */
-
-static int soc_init(void)
-{
-
-	/* Install default handler that simply resets the CPU
-	 * if configured in the kernel, NOP otherwise
-	 */
-	NMI_INIT();
-	return 0;
-}
-
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-
 void z_arm_platform_init(void)
 {
 	/*