soc: renesas: Add support for Renesas RZ/N2L

Add support for Renesas RZ/N2L

Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "renesas,r9a07g084";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+				<0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(128)>;
+		};
+
+		sram: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 (DT_SIZE_M(1) + DT_SIZE_K(512))>;
+		};
+
+		xspi0_cs0: memory@60000000 {
+			compatible = "mmio-sram";
+			reg = <0x60000000 DT_SIZE_M(64)>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				loader_param: partition@0 {
+					label = "loader-param";
+					reg = <0x00000000 0x4C>;
+					read-only;
+				};
+
+				loader_program: partition@4C {
+					label = "loader-program";
+					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
+					read-only;
+				};
+
+				slot0_partition: partition@E000 {
+					label = "image-0";
+					reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+					read-only;
+				};
+			};
+		};
+	};
+};

soc/renesas/rz/common/loader_program.S

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+
+#define ROM_START	(CONFIG_FLASH_BASE_ADDRESS + DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
+#define RAM_START	_image_ram_start // Require CONFIG_XIP=n
+#define APP_SIZE	_image_ram_size
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(loader_program)
+
+/*
+ * Loader program
+ */
+SECTION_FUNC(loader_text, loader_program)
+	ldr r0, =ROM_START         // Src in ROM
+	ldr r1, =RAM_START         // Des in RAM
+	ldr r2, =APP_SIZE
+
+	cmp r2, #0
+	beq exit
+
+loop:
+	ldrb r3, [r0], #1    // Load byte from src and increment src pointer
+	strb r3, [r1], #1    // Store byte to des and increment des pointer
+	subs r2, r2, #1      // Decrement size and updates the condition flags
+	bne loop             // If size is not 0, repeat loop
+
+done:
+	dsb sy
+	ldr pc, =__start
+
+exit:
+	wfi

soc/renesas/rz/rzn2l/CMakeLists.txt

@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  loader_param.c
+  ../common/loader_program.S
+)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/rz/rzn2l/Kconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZN2L
+	select ARM
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RZ_FSP
+	select ARM_ARCH_TIMER
+	select GIC_SINGLE_SECURITY_STATE
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER

soc/renesas/rz/rzn2l/Kconfig.defconfig

@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZN2L
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZN2L

soc/renesas/rz/rzn2l/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZN2L
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/N2L series
+
+config SOC_SERIES
+	default "rzn2l" if SOC_SERIES_RZN2L
+
+config SOC_R9A07G084M04GBG
+	bool
+	select SOC_SERIES_RZN2L
+	help
+	  R9A07G084M04GBG
+
+config SOC
+	default "r9a07g084m04gbg" if SOC_R9A07G084M04GBG

soc/renesas/rz/rzn2l/loader_param.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/linker/section_tags.h>
+
+#define CACHE_FLG            (0x00000000)
+#define CS0BCR_V_WRAPCFG_V   (0x00000000)
+#define CS0WCR_V_COMCFG_V    (0x00000000)
+#define DUMMY0_BMCFG_V       (0x00000000)
+#define BSC_FLG_xSPI_FLG     (0x00000000)
+#define LDR_ADDR_NML         (0x6000004C)
+#define LDR_SIZE_NML         (0x00006000)
+#define DEST_ADDR_NML        (0x00102000)
+#define DUMMY1               (0x00000000)
+#define DUMMY2               (0x00000000)
+#define DUMMY3_CSSCTL_V      (0x0000003F)
+#define DUMMY4_LIOCFGCS0_V   (0x00070000)
+#define DUMMY5               (0x00000000)
+#define DUMMY6               (0x00000000)
+#define DUMMY7               (0x00000000)
+#define DUMMY8               (0x00000000)
+#define DUMMY9               (0x00000000)
+#define DUMMY10_ACCESS_SPEED (0x00000006)
+#define CHECK_SUM            (0xE0A8)
+#define LOADER_PARAM_MAX     (19)
+
+#define __loader_param Z_GENERIC_SECTION(.loader_param)
+
+const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = {
+	CACHE_FLG,
+	CS0BCR_V_WRAPCFG_V,
+	CS0WCR_V_COMCFG_V,
+	DUMMY0_BMCFG_V,
+	BSC_FLG_xSPI_FLG,
+	LDR_ADDR_NML,
+	LDR_SIZE_NML,
+	DEST_ADDR_NML,
+	DUMMY1,
+	DUMMY2,
+	DUMMY3_CSSCTL_V,
+	DUMMY4_LIOCFGCS0_V,
+	DUMMY5,
+	DUMMY6,
+	DUMMY7,
+	DUMMY8,
+	DUMMY9,
+	DUMMY10_ACCESS_SPEED,
+	CHECK_SUM,
+};

soc/renesas/rz/rzn2l/sections.ld

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_param_start = .;
+	KEEP(*(.loader_param))
+	__loader_param_end = .;
+	. = DT_REG_ADDR(DT_NODELABEL(loader_program));
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)

soc/renesas/rz/rzn2l/soc.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/N2L Group
+ */
+
+#include <bsp_api.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/irq.h>
+
+extern void bsp_global_system_counter_init(void);
+
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+IRQn_Type g_current_interrupt_num[32];
+uint8_t g_current_interrupt_pointer;
+
+void soc_reset_hook(void)
+{
+	/* Enable peripheral port access at EL1 and EL0 */
+	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
+	__asm__ volatile("orr r0, #1\n");
+	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+}
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* Initialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+
+	/* Initialize global system counter. The counter is enabled and is incrementing. */
+	bsp_global_system_counter_init();
+}
+
+unsigned int z_soc_irq_get_active(void)
+{
+	int intid = arm_gic_get_active();
+
+	g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
+
+	return intid;
+}
+
+void z_soc_irq_eoi(unsigned int intid)
+{
+	g_current_interrupt_pointer--;
+	arm_gic_eoi(intid);
+}
+
+void z_soc_irq_enable(unsigned int irq)
+{
+	arm_gic_irq_enable(irq);
+}
+
+void z_soc_irq_disable(unsigned int irq)
+{
+	arm_gic_irq_disable(irq);
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	return arm_gic_irq_is_enabled(irq);
+}
+
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+{
+	arm_gic_irq_set_priority(irq, prio, flags);
+}
+
+void z_soc_irq_init(void)
+{
+	g_current_interrupt_pointer = 0;
+}
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void)
+{
+	/* Do nothing */
+}

soc/renesas/rz/rzn2l/soc.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_
+
+typedef enum IRQn {
+	SoftwareGeneratedInt0 = 0,
+	SoftwareGeneratedInt1,
+	SoftwareGeneratedInt2,
+	SoftwareGeneratedInt3,
+	SoftwareGeneratedInt4,
+	SoftwareGeneratedInt5,
+	SoftwareGeneratedInt6,
+	SoftwareGeneratedInt7,
+	SoftwareGeneratedInt8,
+	SoftwareGeneratedInt9,
+	SoftwareGeneratedInt10,
+	SoftwareGeneratedInt11,
+	SoftwareGeneratedInt12,
+	SoftwareGeneratedInt13,
+	SoftwareGeneratedInt14,
+	SoftwareGeneratedInt15,
+	DebugCommunicationsChannelInt = 22,
+	PerformanceMonitorCounterOverflowInt = 23,
+	CrossTriggerInterfaceInt = 24,
+	VritualCPUInterfaceMaintenanceInt = 25,
+	HypervisorTimerInt = 26,
+	VirtualTimerInt = 27,
+	NonSecurePhysicalTimerInt = 30,
+	SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
+} IRQn_Type;
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+#define __FPU_PRESENT 1
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void);
+
+#endif /* ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_ */

soc/renesas/rz/soc.yml

@@ -6,3 +6,6 @@ family:
           - name: r9a08g045s33gbg
             cpuclusters:
               - name: cm33
+      - name: rzn2l
+        socs:
+          - name: r9a07g084m04gbg