From fc9b66bd66369eeba339240dbb4a8941306c67a2 Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Tue, 22 Oct 2019 16:47:00 +0300 Subject: [PATCH] dts: nxp_lpc55S6x_ns.dtsi added Added non-secure mappings for LPC55S6x SoC family. Signed-off-by: Andrei Gansari --- dts/arm/nxp/nxp_lpc55S6x.dtsi | 28 +++---- dts/arm/nxp/nxp_lpc55S6x_ns.dtsi | 140 +++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 14 deletions(-) create mode 100644 dts/arm/nxp/nxp_lpc55S6x_ns.dtsi diff --git a/dts/arm/nxp/nxp_lpc55S6x.dtsi b/dts/arm/nxp/nxp_lpc55S6x.dtsi index e60f723dfa9..5a7edc992d1 100644 --- a/dts/arm/nxp/nxp_lpc55S6x.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x.dtsi @@ -9,7 +9,7 @@ #include / { - aliases{ + aliases { gpio-0 = &gpio0; gpio-1 = &gpio1; gpio-2 = &gpio2; @@ -32,33 +32,33 @@ }; }; - sram0:memory@30000000 { + sram0: memory@30000000 { compatible = "mmio-sram"; reg = <0x30000000 DT_SIZE_K(64)>; }; - sram1:memory@30010000 { + sram1: memory@30010000 { compatible = "mmio-sram"; reg = <0x30010000 DT_SIZE_K(64)>; }; - sram2:memory@30020000 { + sram2: memory@30020000 { compatible = "mmio-sram"; reg = <0x30020000 DT_SIZE_K(64)>; }; - sram3:memory@30030000 { + sram3: memory@30030000 { compatible = "mmio-sram"; reg = <0x30030000 DT_SIZE_K(64)>; }; - sram4:memory@30040000 { + sram4: memory@30040000 { /* Conencted to USB bus*/ compatible = "mmio-sram"; reg = <0x30040000 DT_SIZE_K(16)>; }; - sramx:memory@14000000{ + sramx: memory@14000000 { /* connected to code bus */ compatible = "mmio-sram"; reg = <0x14000000 DT_SIZE_K(32)>; @@ -81,19 +81,19 @@ write-block-size = <512>; }; - flash_reserved:flash@1009D800 { + flash_reserved: flash@1009D800 { compatible = "soc-nv-flash"; reg = <0x1009D800 DT_SIZE_K(10)>; status = "disabled"; }; - boot_rom:flash@13000000 { + boot_rom: flash@13000000 { compatible = "soc-nv-flash"; reg = <0x13000000 DT_SIZE_K(128)>; }; }; - usart0:usart@50086000 { + usart0: usart@50086000 { compatible = "nxp,lpc-usart"; reg = <0x50086000 0xE44>; interrupts = <14 0>; @@ -101,7 +101,7 @@ status = "disabled"; }; - gpio0:gpio@0 { + gpio0: gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; interrupts = <4 2>,<5 2>,<6 2>,<7 2>; @@ -110,7 +110,7 @@ #gpio-cells = <2>; }; - gpio1:gpio@1 { + gpio1: gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; interrupts = <32 2>,<33 2>,<34 2>,<35 2>; @@ -119,7 +119,7 @@ #gpio-cells = <2>; }; - gpio2:gpio@2 { + gpio2: gpio@2 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; label = "GPIO_2"; @@ -127,7 +127,7 @@ #gpio-cells = <2>; }; - gpio3:gpio@3 { + gpio3: gpio@3 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; label = "GPIO_3"; diff --git a/dts/arm/nxp/nxp_lpc55S6x_ns.dtsi b/dts/arm/nxp/nxp_lpc55S6x_ns.dtsi new file mode 100644 index 00000000000..9dff0e4a2db --- /dev/null +++ b/dts/arm/nxp/nxp_lpc55S6x_ns.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2019, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + aliases { + gpio-0 = &gpio0; + gpio-1 = &gpio1; + gpio-2 = &gpio2; + gpio-3 = &gpio3; + spi-8 = &spi8; + usart-0 = &usart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + }; + cpu@1 { + compatible = "arm,cortex-m33"; + reg = <1>; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(64)>; + }; + + sram1: memory@20010000 { + compatible = "mmio-sram"; + reg = <0x20010000 DT_SIZE_K(64)>; + }; + + sram2: memory@20020000 { + compatible = "mmio-sram"; + reg = <0x20020000 DT_SIZE_K(64)>; + }; + + sram3: memory@20030000 { + compatible = "mmio-sram"; + reg = <0x20030000 DT_SIZE_K(64)>; + }; + + sram4: memory@20040000 { + /* Conencted to USB bus*/ + compatible = "mmio-sram"; + reg = <0x20040000 DT_SIZE_K(16)>; + }; + + sramx: memory@04000000 { + compatible = "mmio-sram"; + reg = <0x04000000 DT_SIZE_K(32)>; + }; + + soc { + + flash-controller@40034000 { + compatible = "nxp,lpc-iap"; + label = "FLASH_IAP"; + reg = <0x40034000 0x18>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@00000000 { + compatible = "soc-nv-flash"; + label = "MCUX_FLASH"; + reg = <0x00000000 DT_SIZE_K(630)>; + erase-block-size = <512>; + write-block-size = <512>; + }; + }; + + usart0: usart@40086000 { + compatible = "nxp,lpc-usart"; + reg = <0x40086000 0xe44>; + interrupts = <14 0>; + label = "USART_0"; + status = "disabled"; + }; + + gpio0: gpio@0 { + compatible = "nxp,kinetis-gpio"; + reg = <0x4008c000 0x2488>; + interrupts = <2 2>; + label = "GPIO_0"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@1 { + compatible = "nxp,kinetis-gpio"; + reg = <0x4008c000 0x2488>; + interrupts = <3 2>; + label = "GPIO_1"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio@2 { + compatible = "nxp,lpc-gpio"; + reg = <0x5008c000 0x2488>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + compatible = "nxp,lpc-gpio"; + reg = <0x5008c000 0x2488>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; + + spi8: spi@4009f000 { + compatible = "nxp,lpc-spi"; + reg = <0x4009f000 0x1000>; + interrupts = <59 0>; + label = "SPI_8"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +};