diff --git a/dts/arm/nxp/nxp_kl25z.dtsi b/dts/arm/nxp/nxp_kl25z.dtsi
index 21d22a807b5..548ad725a67 100644
--- a/dts/arm/nxp/nxp_kl25z.dtsi
+++ b/dts/arm/nxp/nxp_kl25z.dtsi
@@ -3,6 +3,7 @@
 #include <mem.h>
 #include "armv6-m.dtsi"
 #include <dt-bindings/clock/kinetis_sim.h>
+#include <dt-bindings/clock/kinetis_mcg.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/i2c/i2c.h>
 
@@ -46,6 +47,13 @@
 			};
 		};
 
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,kinetis-mcg";
+			reg = <0x40064000 0xd>;
+			label = "MCG";
+			#clock-cells = <1>;
+		};
+
 		i2c0: i2c@40066000 {
 			compatible = "nxp,kinetis-i2c";
 			clock-frequency = <I2C_BITRATE_STANDARD>;
@@ -74,8 +82,21 @@
 			compatible = "nxp,kinetis-sim";
 			reg = <0x40047000 0x1060>;
 			label = "SIM";
-
 			#clock-cells = <3>;
+
+			core_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <10>;
+				#clock-cells = <0>;
+			};
+
+			flash_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <1>;
+				#clock-cells = <0>;
+			};
 		};
 
 		uart0: uart@4006a000 {
diff --git a/soc/arm/nxp_kinetis/kl2x/soc.c b/soc/arm/nxp_kinetis/kl2x/soc.c
index 608329a0eab..abc3e16fe67 100644
--- a/soc/arm/nxp_kinetis/kl2x/soc.c
+++ b/soc/arm/nxp_kinetis/kl2x/soc.c
@@ -14,6 +14,12 @@
 
 #define LPSCI0SRC_MCGFLLCLK	(1)
 
+#define CLOCK_NODEID(clk) \
+	DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
+
+#define CLOCK_DIVIDER(clk) \
+	DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -30,7 +36,8 @@ static ALWAYS_INLINE void clock_init(void)
 	const sim_clock_config_t simConfig = {
 		.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
 		.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
-		.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1. */
+		.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
+			   SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
 	};
 
 	const osc_config_t oscConfig = {.freq = CONFIG_OSC_XTAL0_FREQ,