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drivers: clock_control: stm32: Add HSE CSS support

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Add support for enabling the clock security system, which can detect
failures of the HSE clock.

Includes tests for nucleo_h743zi and nucleo_g474re.

Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
This commit is contained in:
Kevin ORourke 2023-11-24 12:16:11 +01:00 • committed by Carles Cufí
commit fbfd36e81e
11 changed files with 125 additions and 0 deletions
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14
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/hse_css.overlay Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2023 Ferroamp AB (publ)
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay assumes the HSE clock has already been enabled,
* for example by hse_24.overlay.
*/
&clk_hse {
css-enabled;
};

13
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/test_stm32_clock_configuration.c
View file

@ -105,4 +105,17 @@ ZTEST(stm32_sysclck_config, test_pll_src)
#endif
}
#if STM32_HSE_ENABLED
ZTEST(stm32_sysclck_config, test_hse_css)
{
/* there is no function to read CSS status, so read directly from the register */
#if STM32_HSE_CSS
zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled");
#else
zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled");
#endif /* STM32_HSE_CSS */
}
#endif /* STM32_HSE_ENABLED */
ZTEST_SUITE(stm32_sysclck_config, NULL, NULL, NULL, NULL, NULL);

4
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/testcase.yaml
View file

@ -114,6 +114,10 @@ tests:
drivers.clock.stm32_clock_configuration.common_core.g4.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re
drivers.clock.stm32_clock_configuration.common_core.g4.sysclksrc_hse_24.css:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay;boards/hse_css.overlay"
platform_allow: nucleo_g474re
drivers.clock.stm32_clock_configuration.common_core.l0_l1.sysclksrc_hse_8:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_msi.overlay;boards/hse_8.overlay"

14
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/hse_css.overlay Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2023 Ferroamp AB (publ)
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay assumes the HSE clock has already been enabled,
* for example by hse_8.overlay.
*/
&clk_hse {
css-enabled;
};

13
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/test_stm32_clock_configuration.c
View file

@ -76,4 +76,17 @@ ZTEST(stm32_syclck_config, test_pll_src)
#endif
}
#if STM32_HSE_ENABLED
ZTEST(stm32_syclck_config, test_hse_css)
{
/* there is no function to read CSS status, so read directly from the register */
#if STM32_HSE_CSS
zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS is not enabled");
#else
zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS unexpectedly enabled");
#endif /* STM32_HSE_CSS */
}
#endif /* STM32_HSE_ENABLED */
ZTEST_SUITE(stm32_syclck_config, NULL, NULL, NULL, NULL, NULL);

6
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml
View file

@ -28,6 +28,12 @@ tests:
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_hse_8_css:
extra_args:
DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay;boards/hse_css.overlay"
platform_allow: nucleo_h743zi
integration_platforms:
- nucleo_h743zi
drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_csi_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_96.overlay"
platform_allow: nucleo_h743zi