dts: pcc: npcx: add properties of pcc node to configure clock settings
This CL introduces six properties, clock-frequency, core-prescaler, apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to configure clock settings. It also removed the original Kconfig options used for the same purpose. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao
Anas Nashif
parent
6885afe432
commit
fbf5b8e8de
9 changed files with 239 additions and 119 deletions
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@ -23,12 +23,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
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# Clock configuration
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CONFIG_CLOCK_CONTROL=y
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# PLL configuration
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CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
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CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
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CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
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CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
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# UART Driver
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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@ -20,13 +20,6 @@ CONFIG_ARM_MPU=y
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# Clock configuration
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CONFIG_CLOCK_CONTROL=y
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# PLL configuration
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CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
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CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
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CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
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CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
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CONFIG_CLOCK_NPCX_APB4_PRESCALER=6
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# General Kernel Options
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
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@ -8,83 +8,3 @@ config CLOCK_CONTROL_NPCX
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depends on SOC_FAMILY_NPCX
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help
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Enable support for NPCX clock controller driver.
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config CLOCK_NPCX_OSC_CYCLES_PER_SEC
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int "CDCG PLL frequency"
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default 48000000
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range 10000000 100000000
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depends on SOC_FAMILY_NPCX
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help
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Core Domain Clock (OFMCLK) Generator PLL frequency,
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allowed values: From 10Mhz to 100Mhz.
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config CLOCK_NPCX_APB1_PRESCALER
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int "APB1 prescaler"
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default 4
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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This sets the APB1 prescaler which changes the frequency of APB1_CLK.
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APB1_CLK frequency = OFMCLK / APB1_PRE. The APB1 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB1_CLK should comply with the following
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requirements:
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- The frequency of APB1_CLK must be set to:
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4MHz <= APB1_CLK <= 50MHz.
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- The frequency of APB1_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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config CLOCK_NPCX_APB2_PRESCALER
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int "APB2 prescaler"
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default 8
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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This sets the APB2 prescaler which changes the frequency of APB2_CLK.
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APB2_CLK frequency = OFMCLK / APB2_PRE. The APB2 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB2_CLK should comply with the following
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requirements:
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- The frequency of APB2_CLK must be set to:
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8MHz <= APB2_CLK <= 50MHz.
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- The frequency of APB2_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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config CLOCK_NPCX_APB3_PRESCALER
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int "APB3 prescaler"
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default 2
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range 1 10
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depends on SOC_FAMILY_NPCX
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help
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This sets the APB3 prescaler which changes the frequency of APB3_CLK.
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APB3_CLK frequency = OFMCLK / APB3_PRE. The APB3 prescaler allowed
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value is from 1 to 10.
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The generated frequency of APB3_CLK should comply with the following
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requirements:
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- The frequency of APB3_CLK must be set to:
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12.5MHz <= APB3_CLK <= 50MHz.
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- The frequency of APB3_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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APB3 prescaler, allowed values: From 1 to 10.
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config CLOCK_NPCX_APB4_PRESCALER
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int "APB4 prescaler"
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default 4
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range 1 10
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depends on SOC_SERIES_NPCX9
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help
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This sets the APB4 prescaler which changes the frequency of APB4_CLK.
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APB4_CLK frequency = OFMCLK / APB4_PRE. The APB4 prescaler allowed
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value is from 1 to 10. Please notice only npcx9 and later series
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support this feature.
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The generated frequency of APB4_CLK should comply with the following
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requirements:
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- The frequency of APB4_CLK must be set to:
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8MHz <= APB4_CLK <= 100MHz.
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- The frequency of APB4_CLK must be an integer division (including 1)
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of the frequency of the Core clock.
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APB4 prescaler, allowed values: From 1 to 10.
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@ -79,7 +79,7 @@ static int npcx_clock_control_get_subsys_rate(const struct device *dev,
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case NPCX_CLOCK_BUS_APB3:
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*rate = NPCX_APB_CLOCK(3);
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break;
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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#if defined(APB4DIV_VAL)
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case NPCX_CLOCK_BUS_APB4:
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*rate = NPCX_APB_CLOCK(4);
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break;
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@ -166,7 +166,7 @@ BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
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APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
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(APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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"Invalid APB3_CLK setting");
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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#if defined(APB4DIV_VAL)
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BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MHZ(100) &&
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APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
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(APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
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@ -204,7 +204,7 @@ static int npcx_clock_control_init(const struct device *dev)
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inst_cdcg->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
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inst_cdcg->HFCBCD = (FIUDIV_VAL << 4);
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inst_cdcg->HFCBCD1 = (APB1DIV_VAL | (APB2DIV_VAL << 4));
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#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
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#if defined(APB4DIV_VAL)
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inst_cdcg->HFCBCD2 = (APB3DIV_VAL | (APB4DIV_VAL << 4));
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#else
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inst_cdcg->HFCBCD2 = APB3DIV_VAL;
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@ -13,6 +13,7 @@
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#include <dt-bindings/pinctrl/npcx-pinctrl.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/sensor/npcx_tach.h>
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#include <freq.h>
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/ {
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cpus {
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@ -92,9 +92,14 @@
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label = "UART_2";
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};
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/* Valid bit-depth of RAM_PDn registers in npcx7 series */
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/* Default clock and power settings in npcx9 series */
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pcc: clock-controller@4000d000 {
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ram-pd-depth = <12>;
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clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
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core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
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apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
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apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */
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};
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/* Wake-up input source mapping for GPIOs in npcx7 series */
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@ -115,9 +115,15 @@
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label = "UART_4";
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};
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/* Valid bit-depth of RAM_PDn registers in npcx9 series */
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/* Default clock and power settings in npcx9 series */
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pcc: clock-controller@4000d000 {
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ram-pd-depth = <15>;
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clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
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core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
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apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
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apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
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ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
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};
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/* Wake-up input source mapping for GPIOs in npcx9 series */
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@ -1,7 +1,22 @@
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# Copyright (c) 2020 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: Nuvoton, NPCX PCC (Power and Clock Controller) node
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description: |
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Nuvoton, NPCX PCC (Power and Clock Controller) node.
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Besides power management, this node is also in charge of configuring the
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Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
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High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
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and most of NPCX hardware modules.
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Here is an example of configuring OFMCLK and the other clock sources derived
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from it in board dts file.
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&pcc {
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clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
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core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
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apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
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apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
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apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
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};
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compatible: "nuvoton,npcx-pcc"
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@ -11,6 +26,186 @@ properties:
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reg:
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required: true
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clock-frequency:
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required: true
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type: int
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description: |
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Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
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only the following values are allowed:
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100000000, 100 MHz
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96000000, 96 MHz
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90000000, 90 MHz
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80000000, 80 MHz
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66000000, 66 MHz
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50000000, 50 MHz
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48000000, 48 MHz
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40000000, 40 MHz (default value after reset)
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33000000, 33 MHz
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enum:
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- 100000000
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- 96000000
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- 90000000
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- 80000000
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- 66000000
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- 50000000
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- 48000000
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- 40000000
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- 33000000
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core-prescaler:
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type: int
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required: true
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description: |
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Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
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dividing OFMCLK(MCLK) and needs to meet the following requirements.
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- CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
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= Only the following values are allowed:
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1, CORE_CLK = OFMCLK
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2, CORE_CLK = OFMCLK / 2
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3, CORE_CLK = OFMCLK / 3
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4, CORE_CLK = OFMCLK / 4
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5, CORE_CLK = OFMCLK / 5
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6, CORE_CLK = OFMCLK / 6
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7, CORE_CLK = OFMCLK / 7
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8, CORE_CLK = OFMCLK / 8
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9, CORE_CLK = OFMCLK / 9
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10, CORE_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb1-prescaler:
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type: int
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required: true
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description: |
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APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
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- APB1_CLK must be an integer division (including 1) of CORE_CLK.
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= Only the following values are allowed:
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1, APB1_CLK = OFMCLK
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2, APB1_CLK = OFMCLK / 2
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3, APB1_CLK = OFMCLK / 3
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4, APB1_CLK = OFMCLK / 4
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5, APB1_CLK = OFMCLK / 5
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6, APB1_CLK = OFMCLK / 6
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7, APB1_CLK = OFMCLK / 7
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8, APB1_CLK = OFMCLK / 8
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9, APB1_CLK = OFMCLK / 9
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10, APB1_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb2-prescaler:
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type: int
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required: true
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description: |
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APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
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- APB2_CLK must be an integer division (including 1) of CORE_CLK.
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= Only the following values are allowed:
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1, APB2_CLK = OFMCLK
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2, APB2_CLK = OFMCLK / 2
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3, APB2_CLK = OFMCLK / 3
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4, APB2_CLK = OFMCLK / 4
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5, APB2_CLK = OFMCLK / 5
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6, APB2_CLK = OFMCLK / 6
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7, APB2_CLK = OFMCLK / 7
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8, APB2_CLK = OFMCLK / 8
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9, APB2_CLK = OFMCLK / 9
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10, APB2_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb3-prescaler:
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type: int
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required: true
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description: |
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APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
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- APB3_CLK must be an integer division (including 1) of CORE_CLK.
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= Only the following values are allowed:
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1, APB3_CLK = OFMCLK
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2, APB3_CLK = OFMCLK / 2
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3, APB3_CLK = OFMCLK / 3
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4, APB3_CLK = OFMCLK / 4
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5, APB3_CLK = OFMCLK / 5
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6, APB3_CLK = OFMCLK / 6
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7, APB3_CLK = OFMCLK / 7
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8, APB3_CLK = OFMCLK / 8
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9, APB3_CLK = OFMCLK / 9
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10, APB3_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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apb4-prescaler:
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type: int
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required: false
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description: |
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APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
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OFMCLK(MCLK) and needs to meet the following requirements.
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- APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
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- APB4_CLK must be an integer division (including 1) of CORE_CLK.
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= Only the following values are allowed:
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1, APB4_CLK = OFMCLK
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2, APB4_CLK = OFMCLK / 2
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3, APB4_CLK = OFMCLK / 3
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4, APB4_CLK = OFMCLK / 4
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5, APB4_CLK = OFMCLK / 5
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6, APB4_CLK = OFMCLK / 6
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7, APB4_CLK = OFMCLK / 7
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8, APB4_CLK = OFMCLK / 8
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9, APB4_CLK = OFMCLK / 9
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10, APB4_CLK = OFMCLK / 10
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enum:
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- 1
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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ram-pd-depth:
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required: false
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type: int
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@ -26,6 +26,26 @@ struct npcx_clk_cfg {
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uint16_t bit:3;
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};
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/* Clock settings from pcc node */
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/* Target OFMCLK freq */
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#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
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/* Core clock prescaler */
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#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
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/* APB1 clock divider */
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#define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
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/* APB2 clock divider */
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#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
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/* APB3 clock divider */
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#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
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/* APB4 clock divider if supported */
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
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#else
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#error "APB4 clock divider is not supported but defined in pcc node!"
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#endif
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#endif
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/*
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* NPCX7 and later series clock tree macros:
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* (Please refer Figure 58. for more information.)
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@ -36,14 +56,10 @@ struct npcx_clk_cfg {
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* - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
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*/
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/* Target OFMCLK freq */
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#define OFMCLK CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC
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/* Core domain clock */
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#define CORE_CLK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
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||||
/* Low Frequency clock */
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||||
#define LFCLK 32768
|
||||
/* Core clock prescaler */
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||||
#define FPRED_VAL ((OFMCLK / CORE_CLK) - 1)
|
||||
|
||||
/* FMUL clock */
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||||
#if (OFMCLK > 50000000)
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|
|
@ -54,16 +70,6 @@ struct npcx_clk_cfg {
|
|||
|
||||
/* APBs source clock */
|
||||
#define APBSRC_CLK OFMCLK
|
||||
/* APB1 clock divider, default value (APB1 clock = OFMCLK/4) */
|
||||
#define APB1DIV_VAL (CONFIG_CLOCK_NPCX_APB1_PRESCALER - 1)
|
||||
/* APB2 clock divider, default value (APB2 clock = OFMCLK/8) */
|
||||
#define APB2DIV_VAL (CONFIG_CLOCK_NPCX_APB2_PRESCALER - 1)
|
||||
/* APB3 clock divider, default value (APB3 clock = OFMCLK/2) */
|
||||
#define APB3DIV_VAL (CONFIG_CLOCK_NPCX_APB3_PRESCALER - 1)
|
||||
/* APB4 clock divider, default value (APB4 clock = OFMCLK/6) */
|
||||
#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
|
||||
#define APB4DIV_VAL (CONFIG_CLOCK_NPCX_APB4_PRESCALER - 1)
|
||||
#endif
|
||||
|
||||
/* AHB6 clock */
|
||||
#if (CORE_CLK > 50000000)
|
||||
|
|
|
|||
Loading…
Add table
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Reference in a new issue