dts: pcc: npcx: add properties of pcc node to configure clock settings

This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>

boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig

@@ -23,12 +23,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
 
-# PLL configuration
-CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
-CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
-
 # UART Driver
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y

boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig

@@ -20,13 +20,6 @@ CONFIG_ARM_MPU=y
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
 
-# PLL configuration
-CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
-CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
-CONFIG_CLOCK_NPCX_APB4_PRESCALER=6
-
 # General Kernel Options
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
 

drivers/clock_control/Kconfig.npcx

@@ -8,83 +8,3 @@ config CLOCK_CONTROL_NPCX
 	depends on SOC_FAMILY_NPCX
 	help
 	  Enable support for NPCX clock controller driver.
-
-config CLOCK_NPCX_OSC_CYCLES_PER_SEC
-	int "CDCG PLL frequency"
-	default 48000000
-	range 10000000 100000000
-	depends on SOC_FAMILY_NPCX
-	help
-	  Core Domain Clock (OFMCLK) Generator PLL frequency,
-	  allowed values: From 10Mhz to 100Mhz.
-
-config CLOCK_NPCX_APB1_PRESCALER
-	int "APB1 prescaler"
-	default 4
-	range 1 10
-	depends on SOC_FAMILY_NPCX
-	help
-	  This sets the APB1 prescaler which changes the frequency of APB1_CLK.
-	  APB1_CLK frequency = OFMCLK / APB1_PRE. The APB1 prescaler allowed
-	  value is from 1 to 10.
-
-	  The generated frequency of APB1_CLK should comply with the following
-	  requirements:
-	  - The frequency of APB1_CLK must be set to:
-	  4MHz <= APB1_CLK <= 50MHz.
-	  - The frequency of APB1_CLK must be an integer division (including 1)
-	  of the frequency of the Core clock.
-
-config CLOCK_NPCX_APB2_PRESCALER
-	int "APB2 prescaler"
-	default 8
-	range 1 10
-	depends on SOC_FAMILY_NPCX
-	help
-	  This sets the APB2 prescaler which changes the frequency of APB2_CLK.
-	  APB2_CLK frequency = OFMCLK / APB2_PRE. The APB2 prescaler allowed
-	  value is from 1 to 10.
-
-	  The generated frequency of APB2_CLK should comply with the following
-	  requirements:
-	  - The frequency of APB2_CLK must be set to:
-	  8MHz <= APB2_CLK <= 50MHz.
-	  - The frequency of APB2_CLK must be an integer division (including 1)
-	  of the frequency of the Core clock.
-
-config CLOCK_NPCX_APB3_PRESCALER
-	int "APB3 prescaler"
-	default 2
-	range 1 10
-	depends on SOC_FAMILY_NPCX
-	help
-	  This sets the APB3 prescaler which changes the frequency of APB3_CLK.
-	  APB3_CLK frequency = OFMCLK / APB3_PRE. The APB3 prescaler allowed
-	  value is from 1 to 10.
-
-	  The generated frequency of APB3_CLK should comply with the following
-	  requirements:
-	  - The frequency of APB3_CLK must be set to:
-	  12.5MHz <= APB3_CLK <= 50MHz.
-	  - The frequency of APB3_CLK must be an integer division (including 1)
-	  of the frequency of the Core clock.
-	  APB3 prescaler, allowed values: From 1 to 10.
-
-config CLOCK_NPCX_APB4_PRESCALER
-	int "APB4 prescaler"
-	default 4
-	range 1 10
-	depends on SOC_SERIES_NPCX9
-	help
-	  This sets the APB4 prescaler which changes the frequency of APB4_CLK.
-	  APB4_CLK frequency = OFMCLK / APB4_PRE. The APB4 prescaler allowed
-	  value is from 1 to 10. Please notice only npcx9 and later series
-	  support this feature.
-
-	  The generated frequency of APB4_CLK should comply with the following
-	  requirements:
-	  - The frequency of APB4_CLK must be set to:
-	  8MHz <= APB4_CLK <= 100MHz.
-	  - The frequency of APB4_CLK must be an integer division (including 1)
-	  of the frequency of the Core clock.
-	  APB4 prescaler, allowed values: From 1 to 10.

drivers/clock_control/clock_control_npcx.c

@@ -79,7 +79,7 @@ static int npcx_clock_control_get_subsys_rate(const struct device *dev,
 	case NPCX_CLOCK_BUS_APB3:
 		*rate = NPCX_APB_CLOCK(3);
 		break;
-#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
+#if defined(APB4DIV_VAL)
 	case NPCX_CLOCK_BUS_APB4:
 		*rate = NPCX_APB_CLOCK(4);
 		break;
@@ -166,7 +166,7 @@ BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
 	     APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
 	     (APB3DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
 	     "Invalid APB3_CLK setting");
-#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
+#if defined(APB4DIV_VAL)
 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MHZ(100) &&
 	     APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
 	     (APB4DIV_VAL + 1) % (FPRED_VAL + 1) == 0,
@@ -204,7 +204,7 @@ static int npcx_clock_control_init(const struct device *dev)
 	inst_cdcg->HFCGP   = ((FPRED_VAL << 4) | AHB6DIV_VAL);
 	inst_cdcg->HFCBCD  = (FIUDIV_VAL << 4);
 	inst_cdcg->HFCBCD1 = (APB1DIV_VAL | (APB2DIV_VAL << 4));
-#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
+#if defined(APB4DIV_VAL)
 	inst_cdcg->HFCBCD2 = (APB3DIV_VAL | (APB4DIV_VAL << 4));
 #else
 	inst_cdcg->HFCBCD2 = APB3DIV_VAL;

dts/arm/nuvoton/npcx.dtsi

@@ -13,6 +13,7 @@
 #include <dt-bindings/pinctrl/npcx-pinctrl.h>
 #include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/sensor/npcx_tach.h>
+#include <freq.h>
 
 / {
 	cpus {

dts/arm/nuvoton/npcx7.dtsi

@@ -92,9 +92,14 @@
 			label = "UART_2";
 		};
 
-		/* Valid bit-depth of RAM_PDn registers in npcx7 series */
+		/* Default clock and power settings in npcx9 series */
 		pcc: clock-controller@4000d000 {
-			ram-pd-depth = <12>;
+			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
+			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
+			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
+			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
+			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
+			ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */
 		};
 
 		/* Wake-up input source mapping for GPIOs in npcx7 series */

dts/arm/nuvoton/npcx9.dtsi

@@ -115,9 +115,15 @@
 			label = "UART_4";
 		};
 
-		/* Valid bit-depth of RAM_PDn registers in npcx9 series */
+		/* Default clock and power settings in npcx9 series */
 		pcc: clock-controller@4000d000 {
-			ram-pd-depth = <15>;
+			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
+			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
+			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
+			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
+			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
+			apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
+			ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
 		};
 
 		/* Wake-up input source mapping for GPIOs in npcx9 series */

dts/bindings/clock/nuvoton,npcx-pcc.yaml

@@ -1,7 +1,22 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX PCC (Power and Clock Controller) node
+description: |
+  Nuvoton, NPCX PCC (Power and Clock Controller) node.
+  Besides power management, this node is also in charge of configuring the
+  Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
+  High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
+  and most of NPCX hardware modules.
+
+  Here is an example of configuring OFMCLK and the other clock sources derived
+  from it in board dts file.
+  &pcc {
+      clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
+      core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
+      apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
+      apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
+      apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
+  };
 
 compatible: "nuvoton,npcx-pcc"
 
@@ -11,12 +26,192 @@ properties:
     reg:
         required: true
 
+    clock-frequency:
+        required: true
+        type: int
+        description: |
+          Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
+          only the following values are allowed:
+            100000000, 100 MHz
+            96000000, 96 MHz
+            90000000, 90 MHz
+            80000000, 80 MHz
+            66000000, 66 MHz
+            50000000, 50 MHz
+            48000000, 48 MHz
+            40000000, 40 MHz (default value after reset)
+            33000000, 33 MHz
+        enum:
+          - 100000000
+          - 96000000
+          - 90000000
+          - 80000000
+          - 66000000
+          - 50000000
+          - 48000000
+          - 40000000
+          - 33000000
+
+    core-prescaler:
+        type: int
+        required: true
+        description: |
+          Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
+          dividing OFMCLK(MCLK) and needs to meet the following requirements.
+          - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
+          = Only the following values are allowed:
+            1, CORE_CLK = OFMCLK
+            2, CORE_CLK = OFMCLK / 2
+            3, CORE_CLK = OFMCLK / 3
+            4, CORE_CLK = OFMCLK / 4
+            5, CORE_CLK = OFMCLK / 5
+            6, CORE_CLK = OFMCLK / 6
+            7, CORE_CLK = OFMCLK / 7
+            8, CORE_CLK = OFMCLK / 8
+            9, CORE_CLK = OFMCLK / 9
+            10, CORE_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb1-prescaler:
+        type: int
+        required: true
+        description: |
+          APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
+          - APB1_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB1_CLK = OFMCLK
+            2, APB1_CLK = OFMCLK / 2
+            3, APB1_CLK = OFMCLK / 3
+            4, APB1_CLK = OFMCLK / 4
+            5, APB1_CLK = OFMCLK / 5
+            6, APB1_CLK = OFMCLK / 6
+            7, APB1_CLK = OFMCLK / 7
+            8, APB1_CLK = OFMCLK / 8
+            9, APB1_CLK = OFMCLK / 9
+            10, APB1_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb2-prescaler:
+        type: int
+        required: true
+        description: |
+          APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
+          - APB2_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB2_CLK = OFMCLK
+            2, APB2_CLK = OFMCLK / 2
+            3, APB2_CLK = OFMCLK / 3
+            4, APB2_CLK = OFMCLK / 4
+            5, APB2_CLK = OFMCLK / 5
+            6, APB2_CLK = OFMCLK / 6
+            7, APB2_CLK = OFMCLK / 7
+            8, APB2_CLK = OFMCLK / 8
+            9, APB2_CLK = OFMCLK / 9
+            10, APB2_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb3-prescaler:
+        type: int
+        required: true
+        description: |
+          APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
+          - APB3_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB3_CLK = OFMCLK
+            2, APB3_CLK = OFMCLK / 2
+            3, APB3_CLK = OFMCLK / 3
+            4, APB3_CLK = OFMCLK / 4
+            5, APB3_CLK = OFMCLK / 5
+            6, APB3_CLK = OFMCLK / 6
+            7, APB3_CLK = OFMCLK / 7
+            8, APB3_CLK = OFMCLK / 8
+            9, APB3_CLK = OFMCLK / 9
+            10, APB3_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
+    apb4-prescaler:
+        type: int
+        required: false
+        description: |
+          APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
+          OFMCLK(MCLK) and needs to meet the following requirements.
+          - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
+          - APB4_CLK must be an integer division (including 1) of CORE_CLK.
+          = Only the following values are allowed:
+            1, APB4_CLK = OFMCLK
+            2, APB4_CLK = OFMCLK / 2
+            3, APB4_CLK = OFMCLK / 3
+            4, APB4_CLK = OFMCLK / 4
+            5, APB4_CLK = OFMCLK / 5
+            6, APB4_CLK = OFMCLK / 6
+            7, APB4_CLK = OFMCLK / 7
+            8, APB4_CLK = OFMCLK / 8
+            9, APB4_CLK = OFMCLK / 9
+            10, APB4_CLK = OFMCLK / 10
+        enum:
+          - 1
+          - 2
+          - 3
+          - 4
+          - 5
+          - 6
+          - 7
+          - 8
+          - 9
+          - 10
+
     ram-pd-depth:
         required: false
         type: int
         enum:
-        - 12
+          - 12
-        - 15
+          - 15
         description: |
           Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
           Each bit in RAM_PDn can power down the relevant RAM block by setting

soc/arm/nuvoton_npcx/common/soc_clock.h

@@ -26,6 +26,26 @@ struct npcx_clk_cfg {
 	uint16_t bit:3;
 };
 
+/* Clock settings from pcc node */
+/* Target OFMCLK freq */
+#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
+/* Core clock prescaler */
+#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
+/* APB1 clock divider */
+#define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
+/* APB2 clock divider */
+#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
+/* APB3 clock divider */
+#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
+/* APB4 clock divider if supported */
+#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
+#if defined(CONFIG_SOC_SERIES_NPCX9)
+#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
+#else
+#error "APB4 clock divider is not supported but defined in pcc node!"
+#endif
+#endif
+
 /*
  * NPCX7 and later series clock tree macros:
  * (Please refer Figure 58. for more information.)
@@ -36,14 +56,10 @@ struct npcx_clk_cfg {
  * - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
  */
 
-/* Target OFMCLK freq */
-#define OFMCLK   CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC
 /* Core domain clock */
-#define CORE_CLK  CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
 /* Low Frequency clock */
-#define LFCLK     32768
+#define LFCLK 32768
-/* Core clock prescaler */
-#define FPRED_VAL ((OFMCLK / CORE_CLK) - 1)
 
 /* FMUL clock */
 #if (OFMCLK > 50000000)
@@ -54,16 +70,6 @@ struct npcx_clk_cfg {
 
 /* APBs source clock */
 #define APBSRC_CLK OFMCLK
-/* APB1 clock divider, default value (APB1 clock = OFMCLK/4) */
-#define APB1DIV_VAL (CONFIG_CLOCK_NPCX_APB1_PRESCALER - 1)
-/* APB2 clock divider, default value (APB2 clock = OFMCLK/8) */
-#define APB2DIV_VAL (CONFIG_CLOCK_NPCX_APB2_PRESCALER - 1)
-/* APB3 clock divider, default value (APB3 clock = OFMCLK/2) */
-#define APB3DIV_VAL (CONFIG_CLOCK_NPCX_APB3_PRESCALER - 1)
-/* APB4 clock divider, default value (APB4 clock = OFMCLK/6) */
-#ifdef CONFIG_CLOCK_NPCX_APB4_PRESCALER
-#define APB4DIV_VAL (CONFIG_CLOCK_NPCX_APB4_PRESCALER - 1)
-#endif
 
 /* AHB6 clock */
 #if (CORE_CLK > 50000000)