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adsp: dmic: Moved registers definitions to a separate file

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Moved dmic register definitions to a separate file dmic_regs.h and added
their description. Platform-dependent registers definitions are placed in
separate files. Used standard macros FIELD_PREP, FIELD_GET in operations on
registers.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki 2023-04-19 13:45:07 +02:00 • committed by Anas Nashif
commit fbb55d1d5e
6 changed files with 742 additions and 511 deletions
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126
drivers/dai/intel/dmic/dmic.c
View file

@ -22,6 +22,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/irq.h> #include <zephyr/irq.h>
#include "dmic.h" #include "dmic.h"
#include "dmic_regs.h"
/* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */ /* Base addresses (in PDM scope) of 2ch PDM controllers and coefficient RAM. */
static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3}; static const uint32_t base[4] = {PDM0, PDM1, PDM2, PDM3};
@ -139,14 +140,14 @@ static inline void dai_dmic_claim_ownership(const struct dai_intel_dmic *dmic)
{ {
/* DMIC Owner Select to DSP */ /* DMIC Owner Select to DSP */
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) |
DMICLCTL_OSEL(0x3), dmic->shim_base + DMICLCTL_OFFSET); FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET);
} }
static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic) static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
{ {
/* DMIC Owner Select back to Host CPU + DSP */ /* DMIC Owner Select back to Host CPU + DSP */
sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & sys_write32(sys_read32(dmic->shim_base + DMICLCTL_OFFSET) &
~DMICLCTL_OSEL(0x0), dmic->shim_base + DMICLCTL_OFFSET); ~DMICLCTL_OSEL, dmic->shim_base + DMICLCTL_OFFSET);
} }
#else /* CONFIG_DAI_DMIC_HAS_OWNERSHIP */ #else /* CONFIG_DAI_DMIC_HAS_OWNERSHIP */
@ -172,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
uint32_t base = dai_dmic_base(dmic); uint32_t base = dai_dmic_base(dmic);
/* DMIC Change sync period */ /* DMIC Change sync period */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL #ifdef CONFIG_SOC_INTEL_ACE20_LNL
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPRD(val), sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU, sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
@ -182,7 +183,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
#else /* All other CAVS and ACE platforms */ #else /* All other CAVS and ACE platforms */
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPRD(val), sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC, sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
@ -193,7 +194,7 @@ static inline void dai_dmic_clear_sync_period(const struct dai_intel_dmic *dmic)
{ {
uint32_t base = dai_dmic_base(dmic); uint32_t base = dai_dmic_base(dmic);
/* DMIC Clean sync period */ /* DMIC Clean sync period */
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD(0x0000), sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_SYNCPRD,
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_CMDSYNC, sys_write32(sys_read32(base + DMICSYNC_OFFSET) & ~DMICSYNC_CMDSYNC,
base + DMICSYNC_OFFSET); base + DMICSYNC_OFFSET);
@ -239,13 +240,13 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
switch (fifo_index) { switch (fifo_index) {
case 0: case 0:
dai_dmic_update_bits(dmic, OUTCONTROL0, dai_dmic_update_bits(dmic, OUTCONTROL0,
OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT, OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL0_FINIT_BIT); OUTCONTROL_FINIT);
break; break;
case 1: case 1:
dai_dmic_update_bits(dmic, OUTCONTROL1, dai_dmic_update_bits(dmic, OUTCONTROL1,
OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT, OUTCONTROL_SIP | OUTCONTROL_FINIT,
OUTCONTROL1_FINIT_BIT); OUTCONTROL_FINIT);
break; break;
} }
} }
@ -264,13 +265,13 @@ static void dai_dmic_irq_handler(const void *data)
val1 = dai_dmic_read(dmic, OUTSTAT1); val1 = dai_dmic_read(dmic, OUTSTAT1);
LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1); LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1);
if (val0 & OUTSTAT0_ROR_BIT) { if (val0 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun"); LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun");
dai_dmic_write(dmic, OUTSTAT0, val0); dai_dmic_write(dmic, OUTSTAT0, val0);
dai_dmic_stop_fifo_packers(dmic, 0); dai_dmic_stop_fifo_packers(dmic, 0);
} }
if (val1 & OUTSTAT1_ROR_BIT) { if (val1 & OUTSTAT_ROR) {
LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun"); LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun");
dai_dmic_write(dmic, OUTSTAT1, val1); dai_dmic_write(dmic, OUTSTAT1, val1);
dai_dmic_stop_fifo_packers(dmic, 1); dai_dmic_stop_fifo_packers(dmic, 1);
@ -281,10 +282,10 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{ {
/* Disable DMIC clock gating */ /* Disable DMIC clock gating */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */ #ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
sys_write32((sys_read32(dmic->vshim_base + DMICLCTL_OFFSET) | DMIC_DCGD), sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLCTL_OFFSET); dmic->vshim_base + DMICLVSCTL_OFFSET);
#else #else
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMIC_DCGD), sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_DCGD),
dmic->shim_base + DMICLCTL_OFFSET); dmic->shim_base + DMICLCTL_OFFSET);
#endif #endif
} }
@ -293,10 +294,10 @@ static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{ {
/* Enable DMIC clock gating */ /* Enable DMIC clock gating */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */ #ifdef CONFIG_SOC_INTEL_ACE20_LNL /* Ace 2.0 */
sys_write32((sys_read32(dmic->vshim_base + DMICLCTL_OFFSET) & ~DMIC_DCGD), sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
dmic->vshim_base + DMICLCTL_OFFSET); dmic->vshim_base + DMICLVSCTL_OFFSET);
#else #else
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMIC_DCGD), sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMICLCTL_DCGD),
dmic->shim_base + DMICLCTL_OFFSET); dmic->shim_base + DMICLCTL_OFFSET);
#endif #endif
@ -413,12 +414,12 @@ static int dai_timestamp_dmic_start(const struct device *dev, struct dai_ts_cfg
/* First point CDMAS to GPDMA channel that is used by DMIC /* First point CDMAS to GPDMA channel that is used by DMIC
* also clear NTK to be sure there is no old timestamp. * also clear NTK to be sure there is no old timestamp.
*/ */
cdmas = TS_LOCAL_TSCTRL_CDMAS(cfg->dma_chan_index + cdmas = FIELD_PREP(TS_LOCAL_TSCTRL_CDMAS, cfg->dma_chan_index +
cfg->dma_chan_count * cfg->dma_id); cfg->dma_chan_count * cfg->dma_id);
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT | cdmas, addr); sys_write32(TS_LOCAL_TSCTRL_NTK | cdmas, addr);
/* Request on demand timestamp */ /* Request on demand timestamp */
sys_write32(TS_LOCAL_TSCTRL_ODTS_BIT | cdmas, addr); sys_write32(TS_LOCAL_TSCTRL_ODTS | cdmas, addr);
return 0; return 0;
} }
@ -426,8 +427,7 @@ static int dai_timestamp_dmic_start(const struct device *dev, struct dai_ts_cfg
static int dai_timestamp_dmic_stop(const struct device *dev, struct dai_ts_cfg *cfg) static int dai_timestamp_dmic_stop(const struct device *dev, struct dai_ts_cfg *cfg)
{ {
/* Clear NTK and write zero to CDMAS */ /* Clear NTK and write zero to CDMAS */
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT, sys_write32(TS_LOCAL_TSCTRL_NTK, TS_DMIC_LOCAL_TSCTRL);
TS_DMIC_LOCAL_TSCTRL);
return 0; return 0;
} }
@ -439,7 +439,7 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
uint32_t ntk; uint32_t ntk;
/* Read SSP timestamp registers */ /* Read SSP timestamp registers */
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK_BIT; ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
if (!ntk) if (!ntk)
goto out; goto out;
@ -450,7 +450,7 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
tsd->sample = sys_read64(TS_DMIC_LOCAL_SAMPLE); tsd->sample = sys_read64(TS_DMIC_LOCAL_SAMPLE);
/* Clear NTK to enable successive timestamps */ /* Clear NTK to enable successive timestamps */
sys_write32(TS_LOCAL_TSCTRL_NTK_BIT, tsctrl); sys_write32(TS_LOCAL_TSCTRL_NTK, tsctrl);
out: out:
tsd->walclk_rate = cfg->walclk_rate; tsd->walclk_rate = cfg->walclk_rate;
@ -514,28 +514,28 @@ static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
if (dmic->startcount == DMIC_UNMUTE_CIC) if (dmic->startcount == DMIC_UNMUTE_CIC)
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_MIC_MUTE_BIT, 0); CIC_CONTROL_MIC_MUTE, 0);
if (dmic->startcount == DMIC_UNMUTE_FIR) { if (dmic->startcount == DMIC_UNMUTE_FIR) {
switch (dmic->dai_config_params.dai_index) { switch (dmic->dai_config_params.dai_index) {
case 0: case 0:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
FIR_CONTROL_A_MUTE_BIT, 0); FIR_CONTROL_MUTE, 0);
break; break;
case 1: case 1:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
FIR_CONTROL_B_MUTE_BIT, 0); FIR_CONTROL_MUTE, 0);
break; break;
} }
} }
switch (dmic->dai_config_params.dai_index) { switch (dmic->dai_config_params.dai_index) {
case 0: case 0:
val = OUT_GAIN_LEFT_A_GAIN(gval); val = FIELD_PREP(OUT_GAIN, gval);
dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_A, val); dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_A, val);
dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_A, val); dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_A, val);
break; break;
case 1: case 1:
val = OUT_GAIN_LEFT_B_GAIN(gval); val = FIELD_PREP(OUT_GAIN, gval);
dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_B, val); dai_dmic_write(dmic, base[i] + OUT_GAIN_LEFT_B, val);
dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_B, val); dai_dmic_write(dmic, base[i] + OUT_GAIN_RIGHT_B, val);
break; break;
@ -576,8 +576,8 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
dai_dmic_update_bits( dai_dmic_update_bits(
dmic, dmic,
OUTCONTROL0, OUTCONTROL0,
OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT, OUTCONTROL_FINIT | OUTCONTROL_SIP,
OUTCONTROL0_SIP_BIT); OUTCONTROL_SIP);
break; break;
case 1: case 1:
LOG_INF("dmic_start(), dmic->fifo_b"); LOG_INF("dmic_start(), dmic->fifo_b");
@ -585,14 +585,14 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
* Start FIFO B packer. * Start FIFO B packer.
*/ */
dai_dmic_update_bits(dmic, OUTCONTROL1, dai_dmic_update_bits(dmic, OUTCONTROL1,
OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT, OUTCONTROL_FINIT | OUTCONTROL_SIP,
OUTCONTROL1_SIP_BIT); OUTCONTROL_SIP);
} }
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) { for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
#ifdef CONFIG_SOC_SERIES_INTEL_ACE #ifdef CONFIG_SOC_SERIES_INTEL_ACE
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_SOFT_RESET_BIT, 0); CIC_CONTROL_SOFT_RESET, 0);
LOG_INF("dmic_start(), cic 0x%08x", LOG_INF("dmic_start(), cic 0x%08x",
dai_dmic_read(dmic, base[i] + CIC_CONTROL)); dai_dmic_read(dmic, base[i] + CIC_CONTROL));
@ -611,41 +611,41 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
*/ */
if (mic_a && mic_b) { if (mic_a && mic_b) {
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_A_BIT | CIC_CONTROL_CIC_START_A |
CIC_CONTROL_CIC_START_B_BIT, CIC_CONTROL_CIC_START_B,
CIC_CONTROL_CIC_START_A(1) | FIELD_PREP(CIC_CONTROL_CIC_START_A, 1) |
CIC_CONTROL_CIC_START_B(1)); FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_A_BIT | MIC_CONTROL_PDM_EN_A |
MIC_CONTROL_PDM_EN_B_BIT, MIC_CONTROL_PDM_EN_B,
MIC_CONTROL_PDM_EN_A(1) | FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1) |
MIC_CONTROL_PDM_EN_B(1)); FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
} else if (mic_a) { } else if (mic_a) {
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_A_BIT, CIC_CONTROL_CIC_START_A,
CIC_CONTROL_CIC_START_A(1)); FIELD_PREP(CIC_CONTROL_CIC_START_A, 1));
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_A_BIT, MIC_CONTROL_PDM_EN_A,
MIC_CONTROL_PDM_EN_A(1)); FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1));
} else if (mic_b) { } else if (mic_b) {
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_CIC_START_B_BIT, CIC_CONTROL_CIC_START_B,
CIC_CONTROL_CIC_START_B(1)); FIELD_PREP(CIC_CONTROL_CIC_START_B, 1));
dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + MIC_CONTROL,
MIC_CONTROL_PDM_EN_B_BIT, MIC_CONTROL_PDM_EN_B,
MIC_CONTROL_PDM_EN_B(1)); FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
} }
switch (dmic->dai_config_params.dai_index) { switch (dmic->dai_config_params.dai_index) {
case 0: case 0:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
FIR_CONTROL_A_START_BIT, FIR_CONTROL_START,
FIR_CONTROL_A_START(fir_a)); FIELD_PREP(FIR_CONTROL_START, fir_a));
break; break;
case 1: case 1:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
FIR_CONTROL_B_START_BIT, FIR_CONTROL_START,
FIR_CONTROL_B_START(fir_b)); FIELD_PREP(FIR_CONTROL_START, fir_b));
break; break;
} }
} }
@ -656,7 +656,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
*/ */
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) { for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_SOFT_RESET_BIT, 0); CIC_CONTROL_SOFT_RESET, 0);
LOG_INF("dmic_start(), cic 0x%08x", LOG_INF("dmic_start(), cic 0x%08x",
dai_dmic_read(dmic, base[i] + CIC_CONTROL)); dai_dmic_read(dmic, base[i] + CIC_CONTROL));
@ -704,21 +704,21 @@ static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
/* Don't stop CIC yet if one FIFO remains active */ /* Don't stop CIC yet if one FIFO remains active */
if (dai_dmic_global.active_fifos_mask == 0) { if (dai_dmic_global.active_fifos_mask == 0) {
dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL, dai_dmic_update_bits(dmic, base[i] + CIC_CONTROL,
CIC_CONTROL_SOFT_RESET_BIT | CIC_CONTROL_SOFT_RESET |
CIC_CONTROL_MIC_MUTE_BIT, CIC_CONTROL_MIC_MUTE,
CIC_CONTROL_SOFT_RESET_BIT | CIC_CONTROL_SOFT_RESET |
CIC_CONTROL_MIC_MUTE_BIT); CIC_CONTROL_MIC_MUTE);
} }
switch (dmic->dai_config_params.dai_index) { switch (dmic->dai_config_params.dai_index) {
case 0: case 0:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_A,
FIR_CONTROL_A_MUTE_BIT, FIR_CONTROL_MUTE,
FIR_CONTROL_A_MUTE_BIT); FIR_CONTROL_MUTE);
break; break;
case 1: case 1:
dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B, dai_dmic_update_bits(dmic, base[i] + FIR_CONTROL_B,
FIR_CONTROL_B_MUTE_BIT, FIR_CONTROL_MUTE,
FIR_CONTROL_B_MUTE_BIT); FIR_CONTROL_MUTE);
break; break;
} }
} }

362
drivers/dai/intel/dmic/dmic.h
View file

@ -9,21 +9,6 @@
#include <zephyr/sys/util_macro.h> #include <zephyr/sys/util_macro.h>
/* bit operations macros */
#define MASK(b_hi, b_lo) \
(((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
#define SET_BIT(b, x) (((x) & 1) << (b))
#define SET_BITS(b_hi, b_lo, x) \
(((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
#define GET_BIT(b, x) \
(((x) & (1ULL << (b))) >> (b))
#define GET_BITS(b_hi, b_lo, x) \
(((x) & MASK(b_hi, b_lo)) >> (b_lo))
/* The microphones create a low frequecy thump sound when clock is enabled. /* The microphones create a low frequecy thump sound when clock is enabled.
* The unmute linear gain ramp chacteristic is defined here. * The unmute linear gain ramp chacteristic is defined here.
* NOTE: Do not set any of these to 0. * NOTE: Do not set any of these to 0.
@ -32,71 +17,6 @@
#define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */ #define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */
#define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */ #define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */
/* DMIC timestamping registers */
#define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000
#define TS_DMIC_LOCAL_OFFS_OFFSET 0x004
#define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008
#define TS_DMIC_LOCAL_WALCLK_OFFSET 0x010
#define TS_DMIC_TSCC_OFFSET 0x018
/* Timestamping */
#define TIMESTAMP_BASE 0x00071800
#define TS_DMIC_LOCAL_TSCTRL (TIMESTAMP_BASE + TS_DMIC_LOCAL_TSCTRL_OFFSET)
#define TS_DMIC_LOCAL_OFFS (TIMESTAMP_BASE + TS_DMIC_LOCAL_OFFS_OFFSET)
#define TS_DMIC_LOCAL_SAMPLE (TIMESTAMP_BASE + TS_DMIC_LOCAL_SAMPLE_OFFSET)
#define TS_DMIC_LOCAL_WALCLK (TIMESTAMP_BASE + TS_DMIC_LOCAL_WALCLK_OFFSET)
#define TS_DMIC_TSCC (TIMESTAMP_BASE + TS_DMIC_TSCC_OFFSET)
#define TS_LOCAL_TSCTRL_NTK_BIT BIT(31)
#define TS_LOCAL_TSCTRL_IONTE_BIT BIT(30)
#define TS_LOCAL_TSCTRL_SIP_BIT BIT(8)
#define TS_LOCAL_TSCTRL_HHTSE_BIT BIT(7)
#define TS_LOCAL_TSCTRL_ODTS_BIT BIT(5)
#define TS_LOCAL_TSCTRL_CDMAS(x) SET_BITS(4, 0, x)
#define TS_LOCAL_OFFS_FRM GET_BITS(15, 12)
#define TS_LOCAL_OFFS_CLK GET_BITS(11, 0)
/* Digital Mic Shim Registers */
#define DMICLCTL_OFFSET 0x04
#define DMICIPPTR_OFFSET 0x08
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
#define DMICSYNC_OFFSET 0x1C
#define DMICLCTL_SPA BIT(16)
#define DMICLCTL_CPA BIT(23)
#define DMICLCTL_OFLEN BIT(4)
/* DMIC disable clock gating */
#define DMIC_DCGD BIT(30)
/* DMIC Command Sync */
#define DMICSYNC_CMDSYNC BIT(24)
/* DMIC Sync Go */
#define DMICSYNC_SYNCGO BIT(23)
#define DMICSYNC_SYNCPU BIT(20)
/* DMIC Sync Period */
#define DMICSYNC_SYNCPRD(x) SET_BITS(19, 0, x)
#define DMICXPCMSyCM_OFFSET 0x16
#else /* All other CAVS and ACE platforms */
#define DMICSYNC_OFFSET 0x0C
/* DMIC power ON bit */
#define DMICLCTL_SPA BIT(0)
#define DMICLCTL_CPA BIT(8)
/* DMIC Owner Select */
#define DMICLCTL_OSEL(x) SET_BITS(25, 24, x)
/* DMIC disable clock gating */
#define DMIC_DCGD BIT(30)
/* DMIC Command Sync */
#define DMICSYNC_CMDSYNC BIT(16)
/* DMIC Sync Go */
#define DMICSYNC_SYNCGO BIT(24)
/* DMIC Sync Period */
#define DMICSYNC_SYNCPRD(x) SET_BITS(14, 0, x)
#endif
/* Parameters used in modes computation */ /* Parameters used in modes computation */
#define DMIC_HW_BITS_CIC 26 #define DMIC_HW_BITS_CIC 26
#define DMIC_HW_BITS_FIR_COEF 20 #define DMIC_HW_BITS_FIR_COEF 20
@ -119,232 +39,6 @@
#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */ #define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */ #define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
/* DMIC register offsets */
/* Global registers */
#define OUTCONTROL0 0x0000
#define OUTSTAT0 0x0004
#define OUTDATA0 0x0008
#define OUTCONTROL1 0x0100
#define OUTSTAT1 0x0104
#define OUTDATA1 0x0108
#define PDM0 0x1000
#define PDM0_COEFFICIENT_A 0x1400
#define PDM0_COEFFICIENT_B 0x1800
#define PDM1 0x2000
#define PDM1_COEFFICIENT_A 0x2400
#define PDM1_COEFFICIENT_B 0x2800
#define PDM2 0x3000
#define PDM2_COEFFICIENT_A 0x3400
#define PDM2_COEFFICIENT_B 0x3800
#define PDM3 0x4000
#define PDM3_COEFFICIENT_A 0x4400
#define PDM3_COEFFICIENT_B 0x4800
#define PDM_COEF_RAM_A_LENGTH 0x0400
#define PDM_COEF_RAM_B_LENGTH 0x0400
/* Local registers in each PDMx */
#define CIC_CONTROL 0x000
#define CIC_CONFIG 0x004
#define MIC_CONTROL 0x00c
#define FIR_CONTROL_A 0x020
#define FIR_CONFIG_A 0x024
#define DC_OFFSET_LEFT_A 0x028
#define DC_OFFSET_RIGHT_A 0x02c
#define OUT_GAIN_LEFT_A 0x030
#define OUT_GAIN_RIGHT_A 0x034
#define FIR_CONTROL_B 0x040
#define FIR_CONFIG_B 0x044
#define DC_OFFSET_LEFT_B 0x048
#define DC_OFFSET_RIGHT_B 0x04c
#define OUT_GAIN_LEFT_B 0x050
#define OUT_GAIN_RIGHT_B 0x054
#define PDM_REG_END 0x058
/* Register bits */
/* OUTCONTROLx IPM bit fields style */
#define OUTCONTROL0_BFTH_MAX 4 /* Max depth 16 */
/* OUTCONTROL0 bits */
#define OUTCONTROL0_TIE_BIT BIT(27)
#define OUTCONTROL0_SIP_BIT BIT(26)
#define OUTCONTROL0_FINIT_BIT BIT(25)
#define OUTCONTROL0_FCI_BIT BIT(24)
#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTCONTROL0_IPM(x) SET_BITS(17, 15, x)
#else
#define OUTCONTROL0_IPM(x) SET_BITS(17, 16, x)
#endif
#define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
#define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
#define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
#define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
#define OUTCONTROL0_IPM_SOURCE_MODE(x) SET_BIT(6, x)
#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
#define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
#define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
#define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
#define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
#define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
#define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 15, x)
#else
#define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 16, x)
#endif
#define OUTCONTROL0_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
#define OUTCONTROL0_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
#define OUTCONTROL0_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
#define OUTCONTROL0_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
#define OUTCONTROL0_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
#define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
/* OUTCONTROL1 bits */
#define OUTCONTROL1_TIE_BIT BIT(27)
#define OUTCONTROL1_SIP_BIT BIT(26)
#define OUTCONTROL1_FINIT_BIT BIT(25)
#define OUTCONTROL1_FCI_BIT BIT(24)
#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTCONTROL1_IPM(x) SET_BITS(17, 15, x)
#else
#define OUTCONTROL1_IPM(x) SET_BITS(17, 16, x)
#endif
#define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
#define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
#define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
#define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
#define OUTCONTROL1_IPM_SOURCE_MODE(x) SET_BIT(6, x)
#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
#define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
#define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
#define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
#define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
#define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
#define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 15, x)
#else
#define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 16, x)
#endif
#define OUTCONTROL1_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
#define OUTCONTROL1_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
#define OUTCONTROL1_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
#define OUTCONTROL1_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
#define OUTCONTROL1_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
#define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
#define OUTCONTROLX_IPM_NUMSOURCES 4
/* OUTSTAT0 bits */
#define OUTSTAT0_AFE_BIT BIT(31)
#define OUTSTAT0_ASNE_BIT BIT(29)
#define OUTSTAT0_RFS_BIT BIT(28)
#define OUTSTAT0_ROR_BIT BIT(27)
#define OUTSTAT0_FL_MASK MASK(6, 0)
/* OUTSTAT1 bits */
#define OUTSTAT1_AFE_BIT BIT(31)
#define OUTSTAT1_ASNE_BIT BIT(29)
#define OUTSTAT1_RFS_BIT BIT(28)
#define OUTSTAT1_ROR_BIT BIT(27)
#define OUTSTAT1_FL_MASK MASK(6, 0)
/* CIC_CONTROL bits */
#define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
#define CIC_CONTROL_CIC_START_B_BIT BIT(15)
#define CIC_CONTROL_CIC_START_A_BIT BIT(14)
#define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
#define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
#define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
#define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
#define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
#define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
#define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
#define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
#define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
#define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
#define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
#define CIC_CONTROL_SOFT_RESET_GET(x) GET_BIT(16, x)
#define CIC_CONTROL_CIC_START_B_GET(x) GET_BIT(15, x)
#define CIC_CONTROL_CIC_START_A_GET(x) GET_BIT(14, x)
#define CIC_CONTROL_MIC_B_POLARITY_GET(x) GET_BIT(3, x)
#define CIC_CONTROL_MIC_A_POLARITY_GET(x) GET_BIT(2, x)
#define CIC_CONTROL_MIC_MUTE_GET(x) GET_BIT(1, x)
#define CIC_CONTROL_STEREO_MODE_GET(x) GET_BIT(0, x)
/* CIC_CONFIG bits */
#define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
#define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
/* CIC_CONFIG masks */
#define CIC_CONFIG_CIC_SHIFT_MASK MASK(27, 24)
#define CIC_CONFIG_COMB_COUNT_MASK MASK(15, 8)
#define CIC_CONFIG_CIC_SHIFT_GET(x) GET_BITS(27, 24, x)
#define CIC_CONFIG_COMB_COUNT_GET(x) GET_BITS(15, 8, x)
/* MIC_CONTROL bits */
#define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
#define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
#define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
#define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
#define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
#define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
#define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
/* MIC_CONTROL masks */
#define MIC_CONTROL_PDM_CLKDIV_MASK MASK(15, 8)
#define MIC_CONTROL_PDM_CLKDIV_GET(x) GET_BITS(15, 8, x)
#define MIC_CONTROL_PDM_SKEW_GET(x) GET_BITS(7, 4, x)
#define MIC_CONTROL_PDM_CLK_EDGE_GET(x) GET_BIT(3, x)
#define MIC_CONTROL_PDM_EN_B_GET(x) GET_BIT(1, x)
#define MIC_CONTROL_PDM_EN_A_GET(x) GET_BIT(0, x)
/* FIR_CONTROL_A bits */
#define FIR_CONTROL_A_START_BIT BIT(7)
#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
#define FIR_CONTROL_A_PERIODIC_START_EN_BIT BIT(5)
#define FIR_CONTROL_A_MUTE_BIT BIT(1)
#define FIR_CONTROL_A_START(x) SET_BIT(7, x)
#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
#define FIR_CONTROL_A_PERIODIC_START_EN(x) SET_BIT(5, x)
#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
#define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x)
#define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x)
#define FIR_CONTROL_A_PERIODIC_START_EN_GET(x) GET_BIT(5, x)
#define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x)
#define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x)
#define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x)
/* FIR_CONFIG_A bits */
#define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
#define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
#define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
#define FIR_CONFIG_A_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
#define FIR_CONFIG_A_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
#define FIR_CONFIG_A_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
/* DC offset compensation time constants */ /* DC offset compensation time constants */
#define DCCOMP_TC0 0 #define DCCOMP_TC0 0
#define DCCOMP_TC1 1 #define DCCOMP_TC1 1
@ -355,62 +49,6 @@
#define DCCOMP_TC6 6 #define DCCOMP_TC6 6
#define DCCOMP_TC7 7 #define DCCOMP_TC7 7
/* DC_OFFSET_LEFT_A bits */
#define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
/* DC_OFFSET_RIGHT_A bits */
#define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
/* OUT_GAIN_LEFT_A bits */
#define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
/* OUT_GAIN_RIGHT_A bits */
#define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
/* FIR_CONTROL_B bits */
#define FIR_CONTROL_B_START_BIT BIT(7)
#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
#define FIR_CONTROL_B_PERIODIC_START_EN_BIT BIT(5)
#define FIR_CONTROL_B_MUTE_BIT BIT(1)
#define FIR_CONTROL_B_START(x) SET_BIT(7, x)
#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
#define FIR_CONTROL_B_PERIODIC_START_EN(x) SET_BIT(5, x)
#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
#define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x)
#define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x)
#define FIR_CONTROL_B_PERIODIC_START_EN_GET(x) GET_BIT(5, x)
#define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x)
#define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x)
#define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x)
/* FIR_CONFIG_B bits */
#define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
#define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
#define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
#define FIR_CONFIG_B_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
#define FIR_CONFIG_B_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
#define FIR_CONFIG_B_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
/* DC_OFFSET_LEFT_B bits */
#define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
/* DC_OFFSET_RIGHT_B bits */
#define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
/* OUT_GAIN_LEFT_B bits */
#define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
/* OUT_GAIN_RIGHT_B bits */
#define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
/* FIR coefficients */
#define FIR_COEF_A(x) SET_BITS(19, 0, x)
#define FIR_COEF_B(x) SET_BITS(19, 0, x)
/* Used for scaling FIR coefficients for HW */ /* Used for scaling FIR coefficients for HW */
#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1) #define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1) #define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)

203
drivers/dai/intel/dmic/dmic_nhlt.c
View file

@ -14,6 +14,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/drivers/dai.h> #include <zephyr/drivers/dai.h>
#include "dmic.h" #include "dmic.h"
#include "dmic_regs.h"
extern struct dai_dmic_global_shared dai_dmic_global; extern struct dai_dmic_global_shared dai_dmic_global;
@ -43,7 +44,7 @@ static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic,
if (*count < pdm_count) { if (*count < pdm_count) {
(*count)++; (*count)++;
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[source_pdm]->mic_control); mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[source_pdm]->mic_control);
if (stereo) if (stereo)
dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */ dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */
else else
@ -65,7 +66,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
int n; int n;
bool stereo_pdm; bool stereo_pdm;
switch (OUTCONTROL0_OF_GET(outcontrol_val)) { switch (FIELD_GET(OUTCONTROL_OF, outcontrol_val)) {
case 0: case 0:
case 1: case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE; dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
@ -80,42 +81,42 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
return -EINVAL; return -EINVAL;
} }
num_pdm = OUTCONTROL0_IPM_GET(outcontrol_val); num_pdm = FIELD_GET(OUTCONTROL_IPM, outcontrol_val);
if (num_pdm > CONFIG_DAI_DMIC_HW_CONTROLLERS) { if (num_pdm > CONFIG_DAI_DMIC_HW_CONTROLLERS) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM PDM controllers count %d", LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM PDM controllers count %d",
num_pdm); num_pdm);
return -EINVAL; return -EINVAL;
} }
stereo_pdm = OUTCONTROL0_IPM_SOURCE_MODE_GET(outcontrol_val); stereo_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, outcontrol_val);
dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm; dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm;
for (n = 0; n < CONFIG_DAI_DMIC_HW_CONTROLLERS; n++) for (n = 0; n < CONFIG_DAI_DMIC_HW_CONTROLLERS; n++)
dmic->enable[n] = 0; dmic->enable[n] = 0;
n = 0; n = 0;
source_pdm = OUTCONTROL0_IPM_SOURCE_1_GET(outcontrol_val); source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm); ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) { if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_1"); LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_1");
return -EINVAL; return -EINVAL;
} }
source_pdm = OUTCONTROL0_IPM_SOURCE_2_GET(outcontrol_val); source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm); ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) { if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_2"); LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_2");
return -EINVAL; return -EINVAL;
} }
source_pdm = OUTCONTROL0_IPM_SOURCE_3_GET(outcontrol_val); source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm); ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) { if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_3"); LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_3");
return -EINVAL; return -EINVAL;
} }
source_pdm = OUTCONTROL0_IPM_SOURCE_4_GET(outcontrol_val); source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm); ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) { if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_4"); LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_4");
@ -133,7 +134,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
int fir_stereo[2]; int fir_stereo[2];
int mic_swap; int mic_swap;
switch (OUTCONTROL0_OF_GET(outcontrol[dmic->dai_config_params.dai_index])) { switch (FIELD_GET(OUTCONTROL_OF, outcontrol[dmic->dai_config_params.dai_index])) {
case 0: case 0:
case 1: case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE; dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
@ -146,12 +147,12 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
return -EINVAL; return -EINVAL;
} }
switch (OUTCONTROL0_IPM_GET(outcontrol[dmic->dai_config_params.dai_index])) { switch (FIELD_GET(OUTCONTROL_IPM, outcontrol[dmic->dai_config_params.dai_index])) {
case 0: case 0:
if (!fir_cfg[0]) if (!fir_cfg[0])
return -EINVAL; return -EINVAL;
fir_stereo[0] = FIR_CONTROL_A_STEREO_GET(fir_cfg[0]->fir_control); fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[0]->fir_control);
if (fir_stereo[0]) { if (fir_stereo[0]) {
dmic->dai_config_params.channels = 2; dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */ dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
@ -159,7 +160,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
} else { } else {
dmic->dai_config_params.channels = 1; dmic->dai_config_params.channels = 1;
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[0]->mic_control); mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[0]->mic_control);
dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */ dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */
dmic->enable[1] = 0x0; /* PDM1 */ dmic->enable[1] = 0x0; /* PDM1 */
} }
@ -168,7 +169,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
if (!fir_cfg[1]) if (!fir_cfg[1])
return -EINVAL; return -EINVAL;
fir_stereo[1] = FIR_CONTROL_A_STEREO_GET(fir_cfg[1]->fir_control); fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[1]->fir_control);
if (fir_stereo[1]) { if (fir_stereo[1]) {
dmic->dai_config_params.channels = 2; dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x0; /* PDM0 none */ dmic->enable[0] = 0x0; /* PDM0 none */
@ -176,7 +177,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
} else { } else {
dmic->dai_config_params.channels = 1; dmic->dai_config_params.channels = 1;
dmic->enable[0] = 0x0; /* PDM0 none */ dmic->enable[0] = 0x0; /* PDM0 none */
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[1]->mic_control); mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[1]->mic_control);
dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */ dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */
} }
break; break;
@ -184,8 +185,8 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
if (!fir_cfg[0] || !fir_cfg[0]) if (!fir_cfg[0] || !fir_cfg[0])
return -EINVAL; return -EINVAL;
fir_stereo[0] = FIR_CONTROL_A_STEREO_GET(fir_cfg[0]->fir_control); fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[0]->fir_control);
fir_stereo[1] = FIR_CONTROL_A_STEREO_GET(fir_cfg[1]->fir_control); fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[1]->fir_control);
if (fir_stereo[0] == fir_stereo[1]) { if (fir_stereo[0] == fir_stereo[1]) {
dmic->dai_config_params.channels = 4; dmic->dai_config_params.channels = 4;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */ dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
@ -269,40 +270,43 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
val = *(uint32_t *)p; val = *(uint32_t *)p;
out_control[n] = val; out_control[n] = val;
bf1 = OUTCONTROL0_TIE_GET(val); bf1 = FIELD_GET(OUTCONTROL_TIE, val);
bf2 = OUTCONTROL0_SIP_GET(val); bf2 = FIELD_GET(OUTCONTROL_SIP, val);
bf3 = OUTCONTROL0_FINIT_GET(val); bf3 = FIELD_GET(OUTCONTROL_FINIT, val);
bf4 = OUTCONTROL0_FCI_GET(val); bf4 = FIELD_GET(OUTCONTROL_FCI, val);
bf5 = OUTCONTROL0_BFTH_GET(val); bf5 = FIELD_GET(OUTCONTROL_BFTH, val);
bf6 = OUTCONTROL0_OF_GET(val); bf6 = FIELD_GET(OUTCONTROL_OF, val);
bf7 = OUTCONTROL0_IPM_GET(val); bf7 = FIELD_GET(OUTCONTROL_IPM, val);
bf8 = OUTCONTROL0_TH_GET(val); bf8 = FIELD_GET(OUTCONTROL_TH, val);
LOG_INF("dmic_set_config_nhlt(): OUTCONTROL%d = %08x", n, out_control[n]); LOG_INF("dmic_set_config_nhlt(): OUTCONTROL%d = %08x", n, out_control[n]);
LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4); LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4);
LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8); LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8);
if (bf5 > OUTCONTROL0_BFTH_MAX) { if (bf5 > OUTCONTROL_BFTH_MAX) {
LOG_ERR("dmic_set_config_nhlt(): illegal BFTH value"); LOG_ERR("dmic_set_config_nhlt(): illegal BFTH value");
return -EINVAL; return -EINVAL;
} }
#ifdef CONFIG_SOC_SERIES_INTEL_ACE #ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf9 = OUTCONTROL0_IPM_SOURCE_1_GET(val); bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
bf10 = OUTCONTROL0_IPM_SOURCE_2_GET(val); bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
bf11 = OUTCONTROL0_IPM_SOURCE_3_GET(val); bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
bf12 = OUTCONTROL0_IPM_SOURCE_4_GET(val); bf12 = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, val);
bf13 = OUTCONTROL0_IPM_SOURCE_MODE_GET(val); bf13 = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, val);
LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12); LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12);
LOG_INF(" ipms_mode=%d", bf13); LOG_INF(" ipms_mode=%d", bf13);
ref = OUTCONTROL0_TIE(bf1) | OUTCONTROL0_SIP(bf2) | OUTCONTROL0_FINIT(bf3) | ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
OUTCONTROL0_FCI(bf4) | OUTCONTROL0_BFTH(bf5) | OUTCONTROL0_OF(bf6) | FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
OUTCONTROL0_IPM(bf7) | OUTCONTROL0_IPM_SOURCE_1(bf9) | FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
OUTCONTROL0_IPM_SOURCE_2(bf10) | OUTCONTROL0_IPM_SOURCE_3(bf11) | FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) |
OUTCONTROL0_IPM_SOURCE_4(bf12) | OUTCONTROL0_TH(bf8) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) |
OUTCONTROL0_IPM_SOURCE_MODE(bf13); FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13);
#else #else
ref = OUTCONTROL0_TIE(bf1) | OUTCONTROL0_SIP(bf2) | OUTCONTROL0_FINIT(bf3) | ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
OUTCONTROL0_FCI(bf4) | OUTCONTROL0_BFTH(bf5) | OUTCONTROL0_OF(bf6) | FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
OUTCONTROL0_IPM(bf7) | OUTCONTROL0_TH(bf8); FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_TH, bf8);
#endif #endif
if (ref != val) { if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal OUTCONTROL%d = 0x%08x", LOG_ERR("dmic_set_config_nhlt(): illegal OUTCONTROL%d = 0x%08x",
@ -318,8 +322,8 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
*/ */
/* Clear TIE, SIP, FCI, set FINIT, the rest of bits as such */ /* Clear TIE, SIP, FCI, set FINIT, the rest of bits as such */
val = (out_control[dmic->dai_config_params.dai_index] & val = (out_control[dmic->dai_config_params.dai_index] &
~(OUTCONTROL0_TIE_BIT | OUTCONTROL0_SIP_BIT | OUTCONTROL0_FCI_BIT)) | ~(OUTCONTROL_TIE | OUTCONTROL_SIP | OUTCONTROL_FCI)) |
OUTCONTROL0_FINIT_BIT; OUTCONTROL_FINIT;
if (dmic->dai_config_params.dai_index == 0) if (dmic->dai_config_params.dai_index == 0)
dai_dmic_write(dmic, OUTCONTROL0, val); dai_dmic_write(dmic, OUTCONTROL0, val);
else else
@ -331,7 +335,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
/* Pass 2^BFTH to plat_data fifo depth. It will be used later in DMA /* Pass 2^BFTH to plat_data fifo depth. It will be used later in DMA
* configuration * configuration
*/ */
bfth = OUTCONTROL0_BFTH_GET(val); bfth = FIELD_GET(OUTCONTROL_BFTH, val);
dmic->fifo.depth = 1 << bfth; dmic->fifo.depth = 1 << bfth;
/* Get PDMx registers */ /* Get PDMx registers */
@ -350,7 +354,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
if (!(pdm_ctrl_mask & (1 << n))) { if (!(pdm_ctrl_mask & (1 << n))) {
/* Set MIC_MUTE bit to unused PDM */ /* Set MIC_MUTE bit to unused PDM */
dai_dmic_write(dmic, base[n] + CIC_CONTROL, CIC_CONTROL_MIC_MUTE(1)); dai_dmic_write(dmic, base[n] + CIC_CONTROL, CIC_CONTROL_MIC_MUTE);
continue; continue;
} }
@ -360,28 +364,38 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
pdm_cfg[n] = (struct nhlt_pdm_ctrl_cfg *)p; pdm_cfg[n] = (struct nhlt_pdm_ctrl_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_cfg); p += sizeof(struct nhlt_pdm_ctrl_cfg);
comb_count = CIC_CONFIG_COMB_COUNT_GET(pdm_cfg[n]->cic_config); comb_count = FIELD_GET(CIC_CONFIG_COMB_COUNT, pdm_cfg[n]->cic_config);
p_mcic = comb_count + 1; p_mcic = comb_count + 1;
clk_div = MIC_CONTROL_PDM_CLKDIV_GET(pdm_cfg[n]->mic_control); clk_div = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, pdm_cfg[n]->mic_control);
p_clkdiv = clk_div + 2; p_clkdiv = clk_div + 2;
if (dai_dmic_global.active_fifos_mask == 0) { if (dai_dmic_global.active_fifos_mask == 0) {
val = pdm_cfg[n]->cic_control; val = pdm_cfg[n]->cic_control;
bf1 = CIC_CONTROL_SOFT_RESET_GET(val); bf1 = FIELD_GET(CIC_CONTROL_SOFT_RESET, val);
bf2 = CIC_CONTROL_CIC_START_B_GET(val); bf2 = FIELD_GET(CIC_CONTROL_CIC_START_B, val);
bf3 = CIC_CONTROL_CIC_START_A_GET(val); bf3 = FIELD_GET(CIC_CONTROL_CIC_START_A, val);
bf4 = CIC_CONTROL_MIC_B_POLARITY_GET(val); bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
bf5 = CIC_CONTROL_MIC_A_POLARITY_GET(val); bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
bf6 = CIC_CONTROL_MIC_MUTE_GET(val); bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
bf7 = CIC_CONTROL_STEREO_MODE_GET(val); #ifndef CONFIG_SOC_SERIES_INTEL_ACE
bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
#else
bf7 = -1;
#endif
LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val); LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d", LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d",
bf1, bf2, bf3); bf1, bf2, bf3);
LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d", LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d",
bf4, bf5, bf6); bf4, bf5, bf6);
ref = CIC_CONTROL_SOFT_RESET(bf1) | CIC_CONTROL_CIC_START_B(bf2) | ref = FIELD_PREP(CIC_CONTROL_SOFT_RESET, bf1) |
CIC_CONTROL_CIC_START_A(bf3) | CIC_CONTROL_MIC_B_POLARITY(bf4) | FIELD_PREP(CIC_CONTROL_CIC_START_B, bf2) |
CIC_CONTROL_MIC_A_POLARITY(bf5) | CIC_CONTROL_MIC_MUTE(bf6) | FIELD_PREP(CIC_CONTROL_CIC_START_A, bf3) |
CIC_CONTROL_STEREO_MODE(bf7); FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
#endif
;
LOG_DBG(" stereo_mode=%d", bf7); LOG_DBG(" stereo_mode=%d", bf7);
if (ref != val) { if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal CIC_CONTROL = 0x%08x", LOG_ERR("dmic_set_config_nhlt(): illegal CIC_CONTROL = 0x%08x",
@ -390,12 +404,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
} }
/* Clear CIC_START_A and CIC_START_B */ /* Clear CIC_START_A and CIC_START_B */
val = (val & ~(CIC_CONTROL_CIC_START_A_BIT | CIC_CONTROL_CIC_START_B_BIT)); val = (val & ~(CIC_CONTROL_CIC_START_A | CIC_CONTROL_CIC_START_B));
dai_dmic_write(dmic, base[n] + CIC_CONTROL, val); dai_dmic_write(dmic, base[n] + CIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val); LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
val = pdm_cfg[n]->cic_config; val = pdm_cfg[n]->cic_config;
bf1 = CIC_CONFIG_CIC_SHIFT_GET(val); bf1 = FIELD_GET(CIC_CONFIG_CIC_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val); LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, comb_count); LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, comb_count);
@ -404,16 +418,20 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val); LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
val = pdm_cfg[n]->mic_control; val = pdm_cfg[n]->mic_control;
bf1 = MIC_CONTROL_PDM_SKEW_GET(val); #ifndef CONFIG_SOC_SERIES_INTEL_ACE
bf2 = MIC_CONTROL_PDM_CLK_EDGE_GET(val); bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
bf3 = MIC_CONTROL_PDM_EN_B_GET(val); #else
bf4 = MIC_CONTROL_PDM_EN_A_GET(val); bf1 = -1;
#endif
bf2 = FIELD_GET(MIC_CONTROL_CLK_EDGE, val);
bf3 = FIELD_GET(MIC_CONTROL_PDM_EN_B, val);
bf4 = FIELD_GET(MIC_CONTROL_PDM_EN_A, val);
LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val); LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", clk_div, bf1, bf2); LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", clk_div, bf1, bf2);
LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4); LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4);
/* Clear PDM_EN_A and PDM_EN_B */ /* Clear PDM_EN_A and PDM_EN_B */
val &= ~(MIC_CONTROL_PDM_EN_A_BIT | MIC_CONTROL_PDM_EN_B_BIT); val &= ~(MIC_CONTROL_PDM_EN_A | MIC_CONTROL_PDM_EN_B);
dai_dmic_write(dmic, base[n] + MIC_CONTROL, val); dai_dmic_write(dmic, base[n] + MIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val); LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
} }
@ -422,12 +440,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
fir_cfg_a[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p; fir_cfg_a[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_fir_cfg); p += sizeof(struct nhlt_pdm_ctrl_fir_cfg);
val = fir_cfg_a[n]->fir_config; val = fir_cfg_a[n]->fir_config;
fir_length = FIR_CONFIG_A_FIR_LENGTH_GET(val); fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
fir_length_a = fir_length + 1; /* Need for parsing */ fir_length_a = fir_length + 1; /* Need for parsing */
fir_decimation = FIR_CONFIG_A_FIR_DECIMATION_GET(val); fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
p_mfira = fir_decimation + 1; p_mfira = fir_decimation + 1;
if (dmic->dai_config_params.dai_index == 0) { if (dmic->dai_config_params.dai_index == 0) {
fir_shift = FIR_CONFIG_A_FIR_SHIFT_GET(val); fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_A = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_A = %08x", val);
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d", LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
fir_decimation, fir_shift, fir_length); fir_decimation, fir_shift, fir_length);
@ -437,19 +455,28 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("configure_registers(), FIR_CONFIG_A = %08x", val); LOG_DBG("configure_registers(), FIR_CONFIG_A = %08x", val);
val = fir_cfg_a[n]->fir_control; val = fir_cfg_a[n]->fir_control;
bf1 = FIR_CONTROL_A_START_GET(val); bf1 = FIELD_GET(FIR_CONTROL_START, val);
bf2 = FIR_CONTROL_A_ARRAY_START_EN_GET(val); bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
bf3 = FIR_CONTROL_A_PERIODIC_START_EN_GET(val); #ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf4 = FIR_CONTROL_A_DCCOMP_GET(val); bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
bf5 = FIR_CONTROL_A_MUTE_GET(val); #else
bf6 = FIR_CONTROL_A_STEREO_GET(val); bf3 = -1;
#endif
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d", LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
bf1, bf2, bf3); bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6); LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
ref = FIR_CONTROL_A_START(bf1) | FIR_CONTROL_A_ARRAY_START_EN(bf2) | ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
FIR_CONTROL_A_PERIODIC_START_EN(bf3) | FIR_CONTROL_A_DCCOMP(bf4) | FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
FIR_CONTROL_A_MUTE(bf5) | FIR_CONTROL_A_STEREO(bf6); #ifdef CONFIG_SOC_SERIES_INTEL_ACE
FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
#endif
FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
FIELD_PREP(FIR_CONTROL_MUTE, bf5) |
FIELD_PREP(FIR_CONTROL_STEREO, bf6);
if (ref != val) { if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x", LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x",
@ -458,7 +485,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
} }
/* Clear START, set MUTE */ /* Clear START, set MUTE */
fir_control = (val & ~FIR_CONTROL_A_START_BIT) | FIR_CONTROL_A_MUTE_BIT; fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
dai_dmic_write(dmic, base[n] + FIR_CONTROL_A, fir_control); dai_dmic_write(dmic, base[n] + FIR_CONTROL_A, fir_control);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", fir_control); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", fir_control);
@ -484,12 +511,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
fir_cfg_b[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p; fir_cfg_b[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_fir_cfg); p += sizeof(struct nhlt_pdm_ctrl_fir_cfg);
val = fir_cfg_b[n]->fir_config; val = fir_cfg_b[n]->fir_config;
fir_length = FIR_CONFIG_B_FIR_LENGTH_GET(val); fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
fir_length_b = fir_length + 1; /* Need for parsing */ fir_length_b = fir_length + 1; /* Need for parsing */
fir_decimation = FIR_CONFIG_B_FIR_DECIMATION_GET(val); fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
p_mfirb = fir_decimation + 1; p_mfirb = fir_decimation + 1;
if (dmic->dai_config_params.dai_index == 1) { if (dmic->dai_config_params.dai_index == 1) {
fir_shift = FIR_CONFIG_B_FIR_SHIFT_GET(val); fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_B = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_B = %08x", val);
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d", LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
fir_decimation, fir_shift, fir_length); fir_decimation, fir_shift, fir_length);
@ -499,19 +526,23 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("configure_registers(), FIR_CONFIG_B = %08x", val); LOG_DBG("configure_registers(), FIR_CONFIG_B = %08x", val);
val = fir_cfg_b[n]->fir_control; val = fir_cfg_b[n]->fir_control;
bf1 = FIR_CONTROL_B_START_GET(val); bf1 = FIELD_GET(FIR_CONTROL_START, val);
bf2 = FIR_CONTROL_B_ARRAY_START_EN_GET(val); bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
bf3 = FIR_CONTROL_B_PERIODIC_START_EN_GET(val); #ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf4 = FIR_CONTROL_B_DCCOMP_GET(val); bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
bf5 = FIR_CONTROL_B_MUTE_GET(val); #else
bf6 = FIR_CONTROL_B_STEREO_GET(val); bf3 = -1;
#endif
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d", LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
bf1, bf2, bf3); bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6); LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
/* Clear START, set MUTE */ /* Clear START, set MUTE */
fir_control = (val & ~FIR_CONTROL_B_START_BIT) | FIR_CONTROL_B_MUTE_BIT; fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
dai_dmic_write(dmic, base[n] + FIR_CONTROL_B, fir_control); dai_dmic_write(dmic, base[n] + FIR_CONTROL_B, fir_control);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", fir_control); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", fir_control);

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/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2023 Intel Corporation
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_H__
/* DMIC timestamping registers */
#define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000
#define TS_DMIC_LOCAL_OFFS_OFFSET 0x004
#define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008
#define TS_DMIC_LOCAL_WALCLK_OFFSET 0x010
#define TS_DMIC_TSCC_OFFSET 0x018
/* Timestamping */
#define TIMESTAMP_BASE 0x00071800
/* Time Stamp Control Register */
#define TS_DMIC_LOCAL_TSCTRL (TIMESTAMP_BASE + TS_DMIC_LOCAL_TSCTRL_OFFSET)
/* Intersample offset Register */
#define TS_DMIC_LOCAL_OFFS (TIMESTAMP_BASE + TS_DMIC_LOCAL_OFFS_OFFSET)
#define TS_DMIC_LOCAL_SAMPLE (TIMESTAMP_BASE + TS_DMIC_LOCAL_SAMPLE_OFFSET)
#define TS_DMIC_LOCAL_WALCLK (TIMESTAMP_BASE + TS_DMIC_LOCAL_WALCLK_OFFSET)
/* Time Stamp Counter Captured 64 bits */
#define TS_DMIC_TSCC (TIMESTAMP_BASE + TS_DMIC_TSCC_OFFSET)
/* New Timestamp Taken */
#define TS_LOCAL_TSCTRL_NTK BIT(31)
/* Interrupt on New Timestamp Enable */
#define TS_LOCAL_TSCTRL_IONTE BIT(30)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
/* DMA Type Select */
#define TS_LOCAL_TSCTRL_DMATS GENMASK(13, 12)
/* Capture Link Select - select which link wall clock to time stamp. */
#define TS_LOCAL_TSCTRL_CLNKS GENMASK(11, 10)
#else /* CONFIG_SOC_SERIES_INTEL_ACE */
/* Automatically capture the local timestamp when the stream is started. */
#define TS_LOCAL_TSCTRL_SIP BIT(8)
#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
/* Hammock Harbor Time Stamp Enable */
#define TS_LOCAL_TSCTRL_HHTSE BIT(7)
/* Link Wall Clock Select */
#define TS_LOCAL_TSCTRL_LWCS BIT(6)
/* On Demand Time Stamp */
#define TS_LOCAL_TSCTRL_ODTS BIT(5)
/* Capture DMA Select */
#define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0)
/* Snapshot of Audio Wall Clock Offset counter (frame offset). */
#define TS_LOCAL_OFFS_FRM GENMASK(15, 12)
/* Snapshot of Audio Wall Clock Offset counter (clock offset). */
#define TS_LOCAL_OFFS_CLK GENMASK(11, 0)
/* DMIC register offsets */
/* Global registers */
/* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
* PDM Primary Channel
*/
/* Control registers for packers */
#define OUTCONTROL0 0x0000
/* Status Register for FIFO interface */
#define OUTSTAT0 0x0004
/* Data read/Write port for FIFO */
#define OUTDATA0 0x0008
/* (crossed out) 000Ch LOCAL_OFFS Offset Counter
* (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
* (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
* 001Ch - 00FFh Reserved space for extensions
*/
/* PDM Secondary Channel */
/* Control registers for packers */
#define OUTCONTROL1 0x0100
/* Status Register for FIFO interface */
#define OUTSTAT1 0x0104
/* Data read/Write port for FIFO */
#define OUTDATA1 0x0108
/* (crossed out) 010Ch LOCAL_OFFS Offset Counter
* (crossed out) 0110h LOCAL_TSC0 64-bit Wall Clock timestamp
* (crossed out) 0118h LOCAL_SAMPLE0 64-bit Sample Count
* 011Ch - 0FFFh Reserved space for extensions
*/
#define GLOBAL_CAPABILITIES 0x200
#define PDM0 0x1000
#define PDM0_COEFFICIENT_A 0x1400
#define PDM0_COEFFICIENT_B 0x1800
#define PDM1 0x2000
#define PDM1_COEFFICIENT_A 0x2400
#define PDM1_COEFFICIENT_B 0x2800
#define PDM2 0x3000
#define PDM2_COEFFICIENT_A 0x3400
#define PDM2_COEFFICIENT_B 0x3800
#define PDM3 0x4000
#define PDM3_COEFFICIENT_A 0x4400
#define PDM3_COEFFICIENT_B 0x4800
#define PDM_COEF_RAM_A_LENGTH 0x0400
#define PDM_COEF_RAM_B_LENGTH 0x0400
/* Local registers in each PDMx */
/* Control register for CIC configuration and decimator setting */
#define CIC_CONTROL 0x000
/* Control of the CIC filter plus voice channel (B) FIR decimation factor */
#define CIC_CONFIG 0x004
/* Microphone interface control register */
#define MIC_CONTROL 0x00c
/* FIR config */
/* Control for the FIR decimator (channel A) */
#define FIR_CONTROL_A 0x020
/* Configuration of FIR decimator parameters (channel A) */
#define FIR_CONFIG_A 0x024
/* DC offset for left channel */
#define DC_OFFSET_LEFT_A 0x028
/* DC offset for right channel */
#define DC_OFFSET_RIGHT_A 0x02c
/* Gain for left channel */
#define OUT_GAIN_LEFT_A 0x030
/* Gain for right channel */
#define OUT_GAIN_RIGHT_A 0x034
/* Control for the FIR decimator (channel B) */
#define FIR_CONTROL_B 0x040
/* Configuration of FIR decimator parameters (channel B) */
#define FIR_CONFIG_B 0x044
/* DC offset for left channel */
#define DC_OFFSET_LEFT_B 0x048
/* DC offset for right channel */
#define DC_OFFSET_RIGHT_B 0x04c
/* Gain for left channel */
#define OUT_GAIN_LEFT_B 0x050
/* Gain for right channel */
#define OUT_GAIN_RIGHT_B 0x054
#define PDM_COEFFICIENT_A 0x400
#define PDM_COEFFICIENT_B 0x800
/* Digital Mic Shim Registers */
/* Digital Microphone Link Control */
#define DMICLCTL 0x04
/* Digital Microphone IP Pointer */
#define DMICIPPTR 0x08
/* OUTCONTROL0 and OUTCONTROL1 */
/* OUTCONTROLx IPM bit fields style */
#define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
/* Threshold Interrupt Enable */
#define OUTCONTROL_TIE BIT(27)
/* Start Input Packer */
#define OUTCONTROL_SIP BIT(26)
/* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */
#define OUTCONTROL_FINIT BIT(25)
/* Input Format Change Indicator */
#define OUTCONTROL_FCI BIT(24)
/* Burst FIFO Threshold */
#define OUTCONTROL_BFTH GENMASK(23, 20)
/* Output Format */
#define OUTCONTROL_OF GENMASK(19, 18)
/* This field decides the packer mode */
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTCONTROL_IPM GENMASK(17, 15)
#else
#define OUTCONTROL_IPM GENMASK(17, 16)
#endif
/* Source decimator for 1st stereo/mono data placeholder. */
#define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13)
/* Source decimator for 2nd stereo/mono data placeholder. */
#define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11)
/* Source decimator for 3rd stereo/mono data placeholder. */
#define OUTCONTROL_IPM_SOURCE_3 GENMASK(10, 9)
/* Source decimator for 4th stereo/mono data placeholder. */
#define OUTCONTROL_IPM_SOURCE_4 GENMASK(8, 7)
/* Defines the mode of operation for all source decimator. */
#define OUTCONTROL_IPM_SOURCE_MODE BIT(6)
/* FIFO Trigger Threshold */
#define OUTCONTROL_TH GENMASK(5, 0)
/* OUTSTAT0 and OUTSTAT1 bits */
/* Asynchronous FIFO is empty */
#define OUTSTAT_AFE BIT(31)
/* Asynchronous FIFO Not Empty */
#define OUTSTAT_ASNE BIT(29)
/* FIFO Service Request */
#define OUTSTAT_RFS BIT(28)
/* Overrun */
#define OUTSTAT_ROR BIT(27)
/* FIFO Level (FL): Current FIFO Level in the Asynchronous FIFO. */
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#define OUTSTAT_FL_MASK GENMASK(8, 0)
#else
#define OUTSTAT_FL_MASK GENMASK(6, 0)
#endif
/* CIC_CONTROL bits */
/* Microphone interface reset. */
#define CIC_CONTROL_SOFT_RESET BIT(16)
/* When set to 1, the CIC channel B (right) is started, otherwise it is muted and idle. */
#define CIC_CONTROL_CIC_START_B BIT(15)
/* When set to 1, the CIC channel A (left) is started, otherwise it is muted and idle. */
#define CIC_CONTROL_CIC_START_A BIT(14)
/* Polarity of the microphone output. */
#define CIC_CONTROL_MIC_B_POLARITY BIT(3)
/* Polarity of the microphone output. */
#define CIC_CONTROL_MIC_A_POLARITY BIT(2)
/* Mute currently active microphones */
#define CIC_CONTROL_MIC_MUTE BIT(1)
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
/* When set, the microphone input operates in the stereo mode */
#define CIC_CONTROL_STEREO_MODE BIT(0)
#endif
/* CIC_CONFIG masks */
/* Number of bits for shift right in the output stage of the CIC filter to compensate the gain
* accumulated due to decimation.
*/
#define CIC_CONFIG_CIC_SHIFT GENMASK(27, 24)
/* Period of activation of comb section in the microphone clocks minus 1 */
#define CIC_CONFIG_COMB_COUNT GENMASK(15, 8)
/* MIC_CONTROL */
/* Clock divider used for producing the microphone clock from audio IO clock with approximately 50%
* duty cycle.
*/
#define MIC_CONTROL_PDM_CLKDIV GENMASK(15, 8)
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
/* Selects the delay of the clocks output for microphones to align the sampling point of the data
* and clock edge.
*/
#define MIC_CONTROL_PDM_SKEW GENMASK(7, 4)
#endif
/* Inverts the clock edge that will be used to sample microphone data stream. */
#define MIC_CONTROL_CLK_EDGE BIT(3)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
/* Indicates the PDM DMIC clock for the decimator will be sourced from external component instead
* of using the PDM DMIC clock generator output
*/
#define MIC_CONTROL_SLAVE_MODE BIT(2)
#endif
/* Enable clock on microphone B (Right) */
#define MIC_CONTROL_PDM_EN_B BIT(1)
/* Enable clock on microphone A (left) */
#define MIC_CONTROL_PDM_EN_A BIT(0)
/* FIR_CONTROL_A bits */
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
/* Enable the power gating capability of the coefficient. */
#define FIR_CONTROL_CRFPGE BIT(28)
/* Power gating capability of the left channel */
#define FIR_CONTROL_LDRFPGE BIT(29)
/* Enable the power gating capability of the right channel */
#define FIR_CONTROL_RDRFPGE BIT(30)
#endif
/* FIR decimation filter is started. */
#define FIR_CONTROL_START BIT(7)
/* Array microphone control bit for synchronous start of multiple interfaces. */
#define FIR_CONTROL_ARRAY_START_EN BIT(6)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
/* Periodic synchronous start control of multiple PDM */
#define FIR_CONTROL_PERIODIC_START_EN BIT(5)
#endif
/* Automatic DC compensation enable */
#define FIR_CONTROL_DCCOMP BIT(4)
/* Write in the coefficient memory will mute the output for the N audio clocks */
#define FIR_CONTROL_AUTO_MUTE BIT(2)
/* Mute outputs of this filter and set it to zero. */
#define FIR_CONTROL_MUTE BIT(1)
/* Filter operates in stereo mode */
#define FIR_CONTROL_STEREO BIT(0)
/* FIR_CONFIG bits */
/* Decimation factor of the FIR filter minus 1. */
#define FIR_CONFIG_FIR_DECIMATION GENMASK(20, 16)
/* Number of bits for shift right in the output stage of the CIC filter to compensate the gain
* accumulated due to decimation.
*/
#define FIR_CONFIG_FIR_SHIFT GENMASK(11, 8)
/* The number of active taps of the FIR filter minus 1. */
#define FIR_CONFIG_FIR_LENGTH GENMASK(7, 0)
/* DC_OFFSET_LEFT and DC_OFFSET_RIGHT */
/* Value added to the output of the FIR filter. */
#define DC_OFFSET_DC_OFFS GENMASK(21, 0)
/* OUT_GAIN_LEFT and OUT_GAIN_RIGHT */
/* Value added to the output of the FIR filter. */
#define OUT_GAIN GENMASK(19, 0)
/* FIR coefficients */
#define FIR_COEF GENMASK(19, 0)
/* GLOBAL_CAPABILITIES */
/* Nnumber of data entries supported in the PCM XCLK FIFO per FIR output. */
#define GLOBAL_CAP_PCM_XCLK_FIFO_DEPTH GENMASK(5, 0)
/* Port Count */
#define GLOBAL_CAP_PORT_COUNT GENMASK(7, 6)
/* FIR Count */
#define GLOBAL_CAP_FIR_COUNT BIT(8)
/* FIR max gain configuration. */
#define GLOBAL_CAP_FIR_MAX_GAIN BIT(9)
/* FIR A RF Depth */
#define GLOBAL_CAP_FIR_A_RF_DEPTH GENMASK(23, 16)
/* FIR B RF Depth */
#define GLOBAL_CAP_FIR_B_RF_DEPTH GENMASK(31, 24)
/* Digital Mic Shim Registers */
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
#include "dmic_regs_ace2x.h"
#else /* All other CAVS and ACE platforms */
/* DMIC Link Control
*
* This register controls the specific link.
*/
#define DMICLCTL_OFFSET 0x04
/* Set Power Active */
#define DMICLCTL_SPA BIT(0)
/* Current Power Active */
#define DMICLCTL_CPA BIT(8)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
/* Owner Select */
#define DMICLCTL_OSEL GENMASK(25, 24)
/* Force Clock Gating */
#define DMICLCTL_FCG BIT(26)
/* Master Link Clock Select */
#define DMICLCTL_MLCS GENMASK(29, 27)
#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
/* Dynamic Clock Gating Disable */
#define DMICLCTL_DCGD BIT(30)
/* Idle Clock Gating Disable */
#define DMICLCTL_ICGD BIT(31)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
#include "dmic_regs_ace1x.h"
#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
#endif /* !CONFIG_SOC_INTEL_ACE20_LNL */
#endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_H__ */

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drivers/dai/intel/dmic/dmic_regs_ace1x.h Normal file
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/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2023 Intel Corporation
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
/* Digital Microphone Synchronization */
#define DMICSYNC_OFFSET 0x0C
/* DMIC Sync Period */
#define DMICSYNC_SYNCPRD GENMASK(14, 0)
/* Sync Period Update */
#define DMICSYNC_SYNCPU BIT(15)
/* Command Sync */
#define DMICSYNC_CMDSYNC BIT(16)
/* Sync Go */
#define DMICSYNC_SYNCGO BIT(24)
/* Extended Sync Period */
#define DMICSYNC_ESYNCPRD BIT(25)
#endif /* ! __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__ */

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/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2023 Intel Corporation
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__
/* DMIC Link Synchronization */
#define DMICSYNC_OFFSET 0x1C
/* Sync Period */
#define DMICSYNC_SYNCPRD GENMASK(19, 0)
/* Sync Period Update */
#define DMICSYNC_SYNCPU BIT(20)
/* Sync Go */
#define DMICSYNC_SYNCGO BIT(23)
/* Command Sync */
#define DMICSYNC_CMDSYNC BIT(24)
/* DMIC Link Control */
#define DMICLCTL_OFFSET 0x04
/* Set Clock Frequency */
#define DMICLCTL_SCF GENMASK(3, 0)
/* Offload Enable */
#define DMICLCTL_OFLEN BIT(4)
/* Interrupt Enable */
#define DMICLCTL_INTEN BIT(5)
/* Set Power Active */
#define DMICLCTL_SPA BIT(16)
/* Current Power Active */
#define DMICLCTL_CPA BIT(23)
/* Interrupt Status */
#define DMICLCTL_INTSTS BIT(31)
/* Digital Microphone x Link Vendor Specific Control */
#define DMICLVSCTL_OFFSET 0x04
/* Force Clock Gating */
#define DMICLVSCTL_FCG BIT(26)
/* Host Link Clock Select */
#define DMICLVSCTL_MLCS GENMASK(29, 27)
/* Dynamic Clock Gating Disable */
#define DMICLVSCTL_DCGD BIT(30)
/* Idle Clock Gating Disable */
#define DMICLVSCTL_ICGD BIT(31)
/* Digital Microphone PCM Stream y Channel Map
*
* Offset: 12h + 02h * y
*/
#define DMICXPCMSyCM_OFFSET 0x16
#define DMICXPCMSyCM_SIZE 0x02
#endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__ */