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adsp: dmic: Moved registers definitions to a separate file

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Moved dmic register definitions to a separate file dmic_regs.h and added
their description. Platform-dependent registers definitions are placed in
separate files. Used standard macros FIELD_PREP, FIELD_GET in operations on
registers.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki 2023-04-19 13:45:07 +02:00 • committed by Anas Nashif
commit fbb55d1d5e
6 changed files with 742 additions and 511 deletions
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203
drivers/dai/intel/dmic/dmic_nhlt.c
View file

@ -14,6 +14,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/drivers/dai.h>
#include "dmic.h"
#include "dmic_regs.h"
extern struct dai_dmic_global_shared dai_dmic_global;
@ -43,7 +44,7 @@ static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic,
if (*count < pdm_count) {
(*count)++;
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[source_pdm]->mic_control);
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[source_pdm]->mic_control);
if (stereo)
dmic->enable[source_pdm] = 0x3; /* PDMi MIC A and B */
else
@ -65,7 +66,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
int n;
bool stereo_pdm;
switch (OUTCONTROL0_OF_GET(outcontrol_val)) {
switch (FIELD_GET(OUTCONTROL_OF, outcontrol_val)) {
case 0:
case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
@ -80,42 +81,42 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
return -EINVAL;
}
num_pdm = OUTCONTROL0_IPM_GET(outcontrol_val);
num_pdm = FIELD_GET(OUTCONTROL_IPM, outcontrol_val);
if (num_pdm > CONFIG_DAI_DMIC_HW_CONTROLLERS) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM PDM controllers count %d",
num_pdm);
return -EINVAL;
}
stereo_pdm = OUTCONTROL0_IPM_SOURCE_MODE_GET(outcontrol_val);
stereo_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, outcontrol_val);
dmic->dai_config_params.channels = (stereo_pdm + 1) * num_pdm;
for (n = 0; n < CONFIG_DAI_DMIC_HW_CONTROLLERS; n++)
dmic->enable[n] = 0;
n = 0;
source_pdm = OUTCONTROL0_IPM_SOURCE_1_GET(outcontrol_val);
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_1");
return -EINVAL;
}
source_pdm = OUTCONTROL0_IPM_SOURCE_2_GET(outcontrol_val);
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_2");
return -EINVAL;
}
source_pdm = OUTCONTROL0_IPM_SOURCE_3_GET(outcontrol_val);
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_3");
return -EINVAL;
}
source_pdm = OUTCONTROL0_IPM_SOURCE_4_GET(outcontrol_val);
source_pdm = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, outcontrol_val);
ret = dai_ipm_source_to_enable(dmic, pdm_cfg, &n, num_pdm, stereo_pdm, source_pdm);
if (ret) {
LOG_ERR("nhlt_dmic_dai_params_get(): Illegal IPM_SOURCE_4");
@ -133,7 +134,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
int fir_stereo[2];
int mic_swap;
switch (OUTCONTROL0_OF_GET(outcontrol[dmic->dai_config_params.dai_index])) {
switch (FIELD_GET(OUTCONTROL_OF, outcontrol[dmic->dai_config_params.dai_index])) {
case 0:
case 1:
dmic->dai_config_params.format = DAI_DMIC_FRAME_S16_LE;
@ -146,12 +147,12 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
return -EINVAL;
}
switch (OUTCONTROL0_IPM_GET(outcontrol[dmic->dai_config_params.dai_index])) {
switch (FIELD_GET(OUTCONTROL_IPM, outcontrol[dmic->dai_config_params.dai_index])) {
case 0:
if (!fir_cfg[0])
return -EINVAL;
fir_stereo[0] = FIR_CONTROL_A_STEREO_GET(fir_cfg[0]->fir_control);
fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[0]->fir_control);
if (fir_stereo[0]) {
dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
@ -159,7 +160,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
} else {
dmic->dai_config_params.channels = 1;
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[0]->mic_control);
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[0]->mic_control);
dmic->enable[0] = mic_swap ? 0x2 : 0x1; /* PDM0 MIC B or MIC A */
dmic->enable[1] = 0x0; /* PDM1 */
}
@ -168,7 +169,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
if (!fir_cfg[1])
return -EINVAL;
fir_stereo[1] = FIR_CONTROL_A_STEREO_GET(fir_cfg[1]->fir_control);
fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[1]->fir_control);
if (fir_stereo[1]) {
dmic->dai_config_params.channels = 2;
dmic->enable[0] = 0x0; /* PDM0 none */
@ -176,7 +177,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
} else {
dmic->dai_config_params.channels = 1;
dmic->enable[0] = 0x0; /* PDM0 none */
mic_swap = MIC_CONTROL_PDM_CLK_EDGE_GET(pdm_cfg[1]->mic_control);
mic_swap = FIELD_GET(MIC_CONTROL_CLK_EDGE, pdm_cfg[1]->mic_control);
dmic->enable[1] = mic_swap ? 0x2 : 0x1; /* PDM1 MIC B or MIC A */
}
break;
@ -184,8 +185,8 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic,
if (!fir_cfg[0] || !fir_cfg[0])
return -EINVAL;
fir_stereo[0] = FIR_CONTROL_A_STEREO_GET(fir_cfg[0]->fir_control);
fir_stereo[1] = FIR_CONTROL_A_STEREO_GET(fir_cfg[1]->fir_control);
fir_stereo[0] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[0]->fir_control);
fir_stereo[1] = FIELD_GET(FIR_CONTROL_STEREO, fir_cfg[1]->fir_control);
if (fir_stereo[0] == fir_stereo[1]) {
dmic->dai_config_params.channels = 4;
dmic->enable[0] = 0x3; /* PDM0 MIC A and B */
@ -269,40 +270,43 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
val = *(uint32_t *)p;
out_control[n] = val;
bf1 = OUTCONTROL0_TIE_GET(val);
bf2 = OUTCONTROL0_SIP_GET(val);
bf3 = OUTCONTROL0_FINIT_GET(val);
bf4 = OUTCONTROL0_FCI_GET(val);
bf5 = OUTCONTROL0_BFTH_GET(val);
bf6 = OUTCONTROL0_OF_GET(val);
bf7 = OUTCONTROL0_IPM_GET(val);
bf8 = OUTCONTROL0_TH_GET(val);
bf1 = FIELD_GET(OUTCONTROL_TIE, val);
bf2 = FIELD_GET(OUTCONTROL_SIP, val);
bf3 = FIELD_GET(OUTCONTROL_FINIT, val);
bf4 = FIELD_GET(OUTCONTROL_FCI, val);
bf5 = FIELD_GET(OUTCONTROL_BFTH, val);
bf6 = FIELD_GET(OUTCONTROL_OF, val);
bf7 = FIELD_GET(OUTCONTROL_IPM, val);
bf8 = FIELD_GET(OUTCONTROL_TH, val);
LOG_INF("dmic_set_config_nhlt(): OUTCONTROL%d = %08x", n, out_control[n]);
LOG_INF(" tie=%d, sip=%d, finit=%d, fci=%d", bf1, bf2, bf3, bf4);
LOG_INF(" bfth=%d, of=%d, ipm=%d, th=%d", bf5, bf6, bf7, bf8);
if (bf5 > OUTCONTROL0_BFTH_MAX) {
if (bf5 > OUTCONTROL_BFTH_MAX) {
LOG_ERR("dmic_set_config_nhlt(): illegal BFTH value");
return -EINVAL;
}
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf9 = OUTCONTROL0_IPM_SOURCE_1_GET(val);
bf10 = OUTCONTROL0_IPM_SOURCE_2_GET(val);
bf11 = OUTCONTROL0_IPM_SOURCE_3_GET(val);
bf12 = OUTCONTROL0_IPM_SOURCE_4_GET(val);
bf13 = OUTCONTROL0_IPM_SOURCE_MODE_GET(val);
bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
bf12 = FIELD_GET(OUTCONTROL_IPM_SOURCE_4, val);
bf13 = FIELD_GET(OUTCONTROL_IPM_SOURCE_MODE, val);
LOG_INF(" ipms1=%d, ipms2=%d, ipms3=%d, ipms4=%d", bf9, bf10, bf11, bf12);
LOG_INF(" ipms_mode=%d", bf13);
ref = OUTCONTROL0_TIE(bf1) | OUTCONTROL0_SIP(bf2) | OUTCONTROL0_FINIT(bf3) |
OUTCONTROL0_FCI(bf4) | OUTCONTROL0_BFTH(bf5) | OUTCONTROL0_OF(bf6) |
OUTCONTROL0_IPM(bf7) | OUTCONTROL0_IPM_SOURCE_1(bf9) |
OUTCONTROL0_IPM_SOURCE_2(bf10) | OUTCONTROL0_IPM_SOURCE_3(bf11) |
OUTCONTROL0_IPM_SOURCE_4(bf12) | OUTCONTROL0_TH(bf8) |
OUTCONTROL0_IPM_SOURCE_MODE(bf13);
ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) |
FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13);
#else
ref = OUTCONTROL0_TIE(bf1) | OUTCONTROL0_SIP(bf2) | OUTCONTROL0_FINIT(bf3) |
OUTCONTROL0_FCI(bf4) | OUTCONTROL0_BFTH(bf5) | OUTCONTROL0_OF(bf6) |
OUTCONTROL0_IPM(bf7) | OUTCONTROL0_TH(bf8);
ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) |
FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) |
FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) |
FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_TH, bf8);
#endif
if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal OUTCONTROL%d = 0x%08x",
@ -318,8 +322,8 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
*/
/* Clear TIE, SIP, FCI, set FINIT, the rest of bits as such */
val = (out_control[dmic->dai_config_params.dai_index] &
~(OUTCONTROL0_TIE_BIT | OUTCONTROL0_SIP_BIT | OUTCONTROL0_FCI_BIT)) |
OUTCONTROL0_FINIT_BIT;
~(OUTCONTROL_TIE | OUTCONTROL_SIP | OUTCONTROL_FCI)) |
OUTCONTROL_FINIT;
if (dmic->dai_config_params.dai_index == 0)
dai_dmic_write(dmic, OUTCONTROL0, val);
else
@ -331,7 +335,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
/* Pass 2^BFTH to plat_data fifo depth. It will be used later in DMA
* configuration
*/
bfth = OUTCONTROL0_BFTH_GET(val);
bfth = FIELD_GET(OUTCONTROL_BFTH, val);
dmic->fifo.depth = 1 << bfth;
/* Get PDMx registers */
@ -350,7 +354,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
if (!(pdm_ctrl_mask & (1 << n))) {
/* Set MIC_MUTE bit to unused PDM */
dai_dmic_write(dmic, base[n] + CIC_CONTROL, CIC_CONTROL_MIC_MUTE(1));
dai_dmic_write(dmic, base[n] + CIC_CONTROL, CIC_CONTROL_MIC_MUTE);
continue;
}
@ -360,28 +364,38 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
pdm_cfg[n] = (struct nhlt_pdm_ctrl_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_cfg);
comb_count = CIC_CONFIG_COMB_COUNT_GET(pdm_cfg[n]->cic_config);
comb_count = FIELD_GET(CIC_CONFIG_COMB_COUNT, pdm_cfg[n]->cic_config);
p_mcic = comb_count + 1;
clk_div = MIC_CONTROL_PDM_CLKDIV_GET(pdm_cfg[n]->mic_control);
clk_div = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, pdm_cfg[n]->mic_control);
p_clkdiv = clk_div + 2;
if (dai_dmic_global.active_fifos_mask == 0) {
val = pdm_cfg[n]->cic_control;
bf1 = CIC_CONTROL_SOFT_RESET_GET(val);
bf2 = CIC_CONTROL_CIC_START_B_GET(val);
bf3 = CIC_CONTROL_CIC_START_A_GET(val);
bf4 = CIC_CONTROL_MIC_B_POLARITY_GET(val);
bf5 = CIC_CONTROL_MIC_A_POLARITY_GET(val);
bf6 = CIC_CONTROL_MIC_MUTE_GET(val);
bf7 = CIC_CONTROL_STEREO_MODE_GET(val);
bf1 = FIELD_GET(CIC_CONTROL_SOFT_RESET, val);
bf2 = FIELD_GET(CIC_CONTROL_CIC_START_B, val);
bf3 = FIELD_GET(CIC_CONTROL_CIC_START_A, val);
bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
#else
bf7 = -1;
#endif
LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
LOG_DBG(" soft_reset=%d, cic_start_b=%d, cic_start_a=%d",
bf1, bf2, bf3);
LOG_DBG(" mic_b_polarity=%d, mic_a_polarity=%d, mic_mute=%d",
bf4, bf5, bf6);
ref = CIC_CONTROL_SOFT_RESET(bf1) | CIC_CONTROL_CIC_START_B(bf2) |
CIC_CONTROL_CIC_START_A(bf3) | CIC_CONTROL_MIC_B_POLARITY(bf4) |
CIC_CONTROL_MIC_A_POLARITY(bf5) | CIC_CONTROL_MIC_MUTE(bf6) |
CIC_CONTROL_STEREO_MODE(bf7);
ref = FIELD_PREP(CIC_CONTROL_SOFT_RESET, bf1) |
FIELD_PREP(CIC_CONTROL_CIC_START_B, bf2) |
FIELD_PREP(CIC_CONTROL_CIC_START_A, bf3) |
FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
#endif
;
LOG_DBG(" stereo_mode=%d", bf7);
if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal CIC_CONTROL = 0x%08x",
@ -390,12 +404,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
}
/* Clear CIC_START_A and CIC_START_B */
val = (val & ~(CIC_CONTROL_CIC_START_A_BIT | CIC_CONTROL_CIC_START_B_BIT));
val = (val & ~(CIC_CONTROL_CIC_START_A | CIC_CONTROL_CIC_START_B));
dai_dmic_write(dmic, base[n] + CIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): CIC_CONTROL = %08x", val);
val = pdm_cfg[n]->cic_config;
bf1 = CIC_CONFIG_CIC_SHIFT_GET(val);
bf1 = FIELD_GET(CIC_CONFIG_CIC_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
LOG_DBG(" cic_shift=%d, comb_count=%d", bf1, comb_count);
@ -404,16 +418,20 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("dmic_set_config_nhlt(): CIC_CONFIG = %08x", val);
val = pdm_cfg[n]->mic_control;
bf1 = MIC_CONTROL_PDM_SKEW_GET(val);
bf2 = MIC_CONTROL_PDM_CLK_EDGE_GET(val);
bf3 = MIC_CONTROL_PDM_EN_B_GET(val);
bf4 = MIC_CONTROL_PDM_EN_A_GET(val);
#ifndef CONFIG_SOC_SERIES_INTEL_ACE
bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
#else
bf1 = -1;
#endif
bf2 = FIELD_GET(MIC_CONTROL_CLK_EDGE, val);
bf3 = FIELD_GET(MIC_CONTROL_PDM_EN_B, val);
bf4 = FIELD_GET(MIC_CONTROL_PDM_EN_A, val);
LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
LOG_DBG(" clkdiv=%d, skew=%d, clk_edge=%d", clk_div, bf1, bf2);
LOG_DBG(" en_b=%d, en_a=%d", bf3, bf4);
/* Clear PDM_EN_A and PDM_EN_B */
val &= ~(MIC_CONTROL_PDM_EN_A_BIT | MIC_CONTROL_PDM_EN_B_BIT);
val &= ~(MIC_CONTROL_PDM_EN_A | MIC_CONTROL_PDM_EN_B);
dai_dmic_write(dmic, base[n] + MIC_CONTROL, val);
LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
}
@ -422,12 +440,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
fir_cfg_a[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_fir_cfg);
val = fir_cfg_a[n]->fir_config;
fir_length = FIR_CONFIG_A_FIR_LENGTH_GET(val);
fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
fir_length_a = fir_length + 1; /* Need for parsing */
fir_decimation = FIR_CONFIG_A_FIR_DECIMATION_GET(val);
fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
p_mfira = fir_decimation + 1;
if (dmic->dai_config_params.dai_index == 0) {
fir_shift = FIR_CONFIG_A_FIR_SHIFT_GET(val);
fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_A = %08x", val);
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
fir_decimation, fir_shift, fir_length);
@ -437,19 +455,28 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("configure_registers(), FIR_CONFIG_A = %08x", val);
val = fir_cfg_a[n]->fir_control;
bf1 = FIR_CONTROL_A_START_GET(val);
bf2 = FIR_CONTROL_A_ARRAY_START_EN_GET(val);
bf3 = FIR_CONTROL_A_PERIODIC_START_EN_GET(val);
bf4 = FIR_CONTROL_A_DCCOMP_GET(val);
bf5 = FIR_CONTROL_A_MUTE_GET(val);
bf6 = FIR_CONTROL_A_STEREO_GET(val);
bf1 = FIELD_GET(FIR_CONTROL_START, val);
bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
#else
bf3 = -1;
#endif
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
ref = FIR_CONTROL_A_START(bf1) | FIR_CONTROL_A_ARRAY_START_EN(bf2) |
FIR_CONTROL_A_PERIODIC_START_EN(bf3) | FIR_CONTROL_A_DCCOMP(bf4) |
FIR_CONTROL_A_MUTE(bf5) | FIR_CONTROL_A_STEREO(bf6);
ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
#endif
FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
FIELD_PREP(FIR_CONTROL_MUTE, bf5) |
FIELD_PREP(FIR_CONTROL_STEREO, bf6);
if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x",
@ -458,7 +485,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
}
/* Clear START, set MUTE */
fir_control = (val & ~FIR_CONTROL_A_START_BIT) | FIR_CONTROL_A_MUTE_BIT;
fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
dai_dmic_write(dmic, base[n] + FIR_CONTROL_A, fir_control);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", fir_control);
@ -484,12 +511,12 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
fir_cfg_b[n] = (struct nhlt_pdm_ctrl_fir_cfg *)p;
p += sizeof(struct nhlt_pdm_ctrl_fir_cfg);
val = fir_cfg_b[n]->fir_config;
fir_length = FIR_CONFIG_B_FIR_LENGTH_GET(val);
fir_length = FIELD_GET(FIR_CONFIG_FIR_LENGTH, val);
fir_length_b = fir_length + 1; /* Need for parsing */
fir_decimation = FIR_CONFIG_B_FIR_DECIMATION_GET(val);
fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
p_mfirb = fir_decimation + 1;
if (dmic->dai_config_params.dai_index == 1) {
fir_shift = FIR_CONFIG_B_FIR_SHIFT_GET(val);
fir_shift = FIELD_GET(FIR_CONFIG_FIR_SHIFT, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONFIG_B = %08x", val);
LOG_DBG(" fir_decimation=%d, fir_shift=%d, fir_length=%d",
fir_decimation, fir_shift, fir_length);
@ -499,19 +526,23 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
LOG_DBG("configure_registers(), FIR_CONFIG_B = %08x", val);
val = fir_cfg_b[n]->fir_control;
bf1 = FIR_CONTROL_B_START_GET(val);
bf2 = FIR_CONTROL_B_ARRAY_START_EN_GET(val);
bf3 = FIR_CONTROL_B_PERIODIC_START_EN_GET(val);
bf4 = FIR_CONTROL_B_DCCOMP_GET(val);
bf5 = FIR_CONTROL_B_MUTE_GET(val);
bf6 = FIR_CONTROL_B_STEREO_GET(val);
bf1 = FIELD_GET(FIR_CONTROL_START, val);
bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
#else
bf3 = -1;
#endif
bf4 = FIELD_GET(FIR_CONTROL_DCCOMP, val);
bf5 = FIELD_GET(FIR_CONTROL_MUTE, val);
bf6 = FIELD_GET(FIR_CONTROL_STEREO, val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
/* Clear START, set MUTE */
fir_control = (val & ~FIR_CONTROL_B_START_BIT) | FIR_CONTROL_B_MUTE_BIT;
fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
dai_dmic_write(dmic, base[n] + FIR_CONTROL_B, fir_control);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", fir_control);