diff --git a/soc/intel/intel_adsp/ace/multiprocessing.c b/soc/intel/intel_adsp/ace/multiprocessing.c index 5d65af42683..3616861ea0f 100644 --- a/soc/intel/intel_adsp/ace/multiprocessing.c +++ b/soc/intel/intel_adsp/ace/multiprocessing.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -147,6 +148,11 @@ void soc_start_core(int cpu_num) } else { *rom_jump_vector = (uint32_t) dsp_restore_vector; } + + /* The primary core cannot enter power gating if any of the secondary cores are + * active. + */ + pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); #else *rom_jump_vector = (uint32_t) z_soc_mp_asm_entry; #endif diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c index 34684e6756c..fc0f87570ec 100644 --- a/soc/intel/intel_adsp/ace/power.c +++ b/soc/intel/intel_adsp/ace/power.c @@ -5,6 +5,7 @@ */ #include #include +#include #include #include #include @@ -342,6 +343,10 @@ void pm_state_set(enum pm_state state, uint8_t substate_id) /* do power down - this function won't return */ power_down(true, IS_ENABLED(CONFIG_ADSP_POWER_DOWN_HPSRAM), true); } else { + /* When all secondary cores are turned off, power gating for the primary + * core will be re-enabled. + */ + pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES); power_gate_entry(cpu); } break;