soc: renesas: Add power management support for Renesas RA8
Updated `CMakeLists.txt` and `Kconfig` to integrate power management for RA8D1, RA8M1, and RA8T1. Modified `Kconfig.defconfig` to configure ULPT timer as the system timer when power management is enabled: - Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC` for ULPT timer. - Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer. Implemented power management logic in the new `power.c` file for: - RA8D1 (`soc/renesas/ra/ra8d1/power.c`) - RA8M1 (`soc/renesas/ra/ra8m1/power.c`) - RA8T1 (`soc/renesas/ra/ra8t1/power.c`) Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This commit is contained in:
Khanh Nguyen
Benjamin Cabé
parent
528153e245
commit
fb572d59a2
12 changed files with 358 additions and 16 deletions
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@ -7,6 +7,10 @@ zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_PM
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power.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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@ -15,3 +15,4 @@ config SOC_SERIES_RA8D1
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select HAS_RENESAS_RA_FSP
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select SOC_EARLY_INIT_HOOK
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select GPIO_RA_HAS_VBTICTLR
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select HAS_PM
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@ -6,11 +6,6 @@ if SOC_SERIES_RA8D1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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@ -27,4 +22,20 @@ config DCACHE
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config CACHE_MANAGEMENT
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default n
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config CORTEX_M_SYSTICK
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default n if RENESAS_RA_ULPT_TIMER
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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DT_LOCO_PATH := $(dt_nodelabel_path,loco)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 4096 if RENESAS_RA_ULPT_TIMER
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config PM_DEVICE
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default y if PM
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endif # SOC_SERIES_RA8D1
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98
soc/renesas/ra/ra8d1/power.c
Normal file
98
soc/renesas/ra/ra8d1/power.c
Normal file
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <r_lpm.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/* Low Power Mode instance control structure */
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static lpm_instance_ctrl_t pm_state_ctrl;
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/* Configuration for Runtime Idle Power State */
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const lpm_cfg_t pm_state_runtime_idle_cfg = {
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.low_power_mode = LPM_MODE_SLEEP,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ram_retention_cfg.standby_ram_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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/* Configuration for Standby Power State */
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const lpm_cfg_t pm_state_standby_cfg = {
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.low_power_mode = LPM_MODE_STANDBY,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ram_retention_cfg.standby_ram_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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case PM_STATE_STANDBY:
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R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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default:
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break;
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}
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}
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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__fallthrough;
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case PM_STATE_STANDBY:
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R_LPM_Close(&pm_state_ctrl);
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break;
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default:
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break;
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}
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irq_unlock(0);
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}
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@ -7,6 +7,10 @@ zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_PM
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power.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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@ -15,5 +15,6 @@ config SOC_SERIES_RA8M1
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select HAS_RENESAS_RA_FSP
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select SOC_EARLY_INIT_HOOK
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select GPIO_RA_HAS_VBTICTLR
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select HAS_PM
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help
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Enable support for Renesas RA8M1 MCU series
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@ -1,4 +1,4 @@
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# Copyright (c) 2024 Renesas Electronics Corporation
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# Copyright (c) 2024-2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA8M1
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@ -6,11 +6,6 @@ if SOC_SERIES_RA8M1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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@ -21,4 +16,20 @@ config CLOCK_CONTROL
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config CORTEX_M_SYSTICK
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default n if RENESAS_RA_ULPT_TIMER
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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DT_LOCO_PATH := $(dt_nodelabel_path,loco)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 4096 if RENESAS_RA_ULPT_TIMER
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config PM_DEVICE
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default y if PM
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endif # SOC_SERIES_RA8M1
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98
soc/renesas/ra/ra8m1/power.c
Normal file
98
soc/renesas/ra/ra8m1/power.c
Normal file
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <r_lpm.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/* Low Power Mode instance control structure */
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static lpm_instance_ctrl_t pm_state_ctrl;
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/* Configuration for Runtime Idle Power State */
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const lpm_cfg_t pm_state_runtime_idle_cfg = {
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.low_power_mode = LPM_MODE_SLEEP,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ram_retention_cfg.standby_ram_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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/* Configuration for Standby Power State */
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const lpm_cfg_t pm_state_standby_cfg = {
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.low_power_mode = LPM_MODE_STANDBY,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ram_retention_cfg.standby_ram_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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case PM_STATE_STANDBY:
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R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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default:
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break;
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}
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}
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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__fallthrough;
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case PM_STATE_STANDBY:
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R_LPM_Close(&pm_state_ctrl);
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break;
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default:
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break;
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}
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irq_unlock(0);
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}
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@ -7,6 +7,10 @@ zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_PM
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power.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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@ -15,3 +15,4 @@ config SOC_SERIES_RA8T1
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select HAS_RENESAS_RA_FSP
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select SOC_EARLY_INIT_HOOK
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select GPIO_RA_HAS_VBTICTLR
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select HAS_PM
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@ -6,11 +6,6 @@ if SOC_SERIES_RA8T1
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config NUM_IRQS
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default 96
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
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config BUILD_OUTPUT_HEX
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default y
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@ -21,4 +16,20 @@ config CLOCK_CONTROL
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config FLASH_FILL_BUFFER_SIZE
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default 128
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config CORTEX_M_SYSTICK
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default n if RENESAS_RA_ULPT_TIMER
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DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
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DT_LOCO_PATH := $(dt_nodelabel_path,loco)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 4096 if RENESAS_RA_ULPT_TIMER
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config PM_DEVICE
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default y if PM
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endif # SOC_SERIES_RA8T1
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98
soc/renesas/ra/ra8t1/power.c
Normal file
98
soc/renesas/ra/ra8t1/power.c
Normal file
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@ -0,0 +1,98 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <r_lpm.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/* Low Power Mode instance control structure */
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static lpm_instance_ctrl_t pm_state_ctrl;
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/* Configuration for Runtime Idle Power State */
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const lpm_cfg_t pm_state_runtime_idle_cfg = {
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.low_power_mode = LPM_MODE_SLEEP,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ram_retention_cfg.standby_ram_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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/* Configuration for Standby Power State */
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const lpm_cfg_t pm_state_standby_cfg = {
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.low_power_mode = LPM_MODE_STANDBY,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
|
||||
.io_port_state = LPM_IO_PORT_NO_CHANGE,
|
||||
.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
|
||||
.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
|
||||
.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
|
||||
.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
|
||||
.ram_retention_cfg.tcm_retention = true,
|
||||
.ram_retention_cfg.standby_ram_retention = true,
|
||||
.ldo_standby_cfg.pll1_ldo = false,
|
||||
.ldo_standby_cfg.pll2_ldo = false,
|
||||
.ldo_standby_cfg.hoco_ldo = false,
|
||||
.p_extend = NULL,
|
||||
};
|
||||
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_STATE_RUNTIME_IDLE:
|
||||
R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
|
||||
__disable_irq();
|
||||
__set_BASEPRI(0);
|
||||
__ISB();
|
||||
|
||||
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
|
||||
__enable_irq();
|
||||
__ISB();
|
||||
break;
|
||||
|
||||
case PM_STATE_STANDBY:
|
||||
R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
|
||||
__disable_irq();
|
||||
__set_BASEPRI(0);
|
||||
__ISB();
|
||||
|
||||
R_LPM_LowPowerModeEnter(&pm_state_ctrl);
|
||||
__enable_irq();
|
||||
__ISB();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_STATE_RUNTIME_IDLE:
|
||||
__fallthrough;
|
||||
case PM_STATE_STANDBY:
|
||||
R_LPM_Close(&pm_state_ctrl);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
irq_unlock(0);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue