From faf55932720a18afbbb81f20cc82a732eb312b5f Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 3 Oct 2023 21:49:35 +0000 Subject: [PATCH] soc: arm: nxp_lpc: Only clock core from PLL1 when CONFIG_FLASH=n Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This is required due to the following limitation of the flash controller (documented in the reference manual): Flash operations (erase, blank check, program) and reading a single word can only be performed for CPU frequencies of up to 100 MHz. These operations cannot be performed for frequencies above 100 MHz. The PLL1 clock source will result in a core clock of 150MHz, which violates this requirement. Fixes #62963 Signed-off-by: Daniel DeGrasse --- soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc index a7bae5aafb0..a1531b8ede4 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc +++ b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc @@ -123,10 +123,12 @@ config INIT_PLL0 config INIT_PLL1 bool "Initialize PLL1" default "y" - depends on !SOC_LPC55S06 + depends on !(SOC_LPC55S06 || FLASH) help In the LPC55XXX Family, this is currently being used to set the core clock value at it's highest frequency which clocks at 150MHz. + Note that flash programming operations are limited to 100MHz, and + this PLL should not be used as the core clock in those cases. config SECOND_CORE_MCUX bool "LPC55xxx's second core"