From fadeb3eb47b7c116abebdf6fbf8ebf10a670bb65 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Tue, 29 Oct 2019 08:55:27 -0700 Subject: [PATCH] soc: intel_s1000_crb: update LP_SRAM macros The DT_LP_SRAM_* are aliases to DT_MIMO_SRAM_1_* which are deprecated, so changing these to DT_INST_1_MMIO_SRAM_*. Signed-off-by: Daniel Leung --- soc/xtensa/intel_s1000/dts_fixup.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index b6e514ba665..bf767d7001e 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -15,8 +15,8 @@ #define DT_L2_SRAM_BASE DT_SRAM_BASE_ADDRESS #define DT_L2_SRAM_SIZE DT_SRAM_SIZE * 1024 -#define DT_LP_SRAM_BASE DT_MMIO_SRAM_1_BASE_ADDRESS -#define DT_LP_SRAM_SIZE DT_MMIO_SRAM_1_SIZE +#define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS +#define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE #define DT_CAVS_ICTL_BASE_ADDR DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS #define DT_CAVS_ICTL_0_IRQ DT_INTEL_CAVS_INTC_78800_IRQ_0