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boards: lpcxpresso55s69: use LMA adjustment for second core

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Use LMA adjustment building dual core image with LPC55s69. The load
address adjustment allows the second core image to be flashed onto the chip
by the debugger, into the secure region of the LPC flash.

Additionally, remove the build dependency that was enforced by the SOC.
This requirement to build the secondary core image first can be enforced
by the project itself, instead of the core.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-08-04 09:32:26 -05:00 • committed by Carles Cufí
commit fadd86d3e2
4 changed files with 10 additions and 42 deletions
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19
boards/arm/lpcxpresso55s69/CMakeLists.txt
View file

@ -7,22 +7,3 @@
zephyr_library()
zephyr_library_sources(pinmux.c)
if (CONFIG_SECOND_CORE_MCUX)
# Set srec_cat binary name
find_program(SREC_CAT srec_cat)
if(${SREC_CAT} STREQUAL SREC_CAT-NOTFOUND)
message(FATAL_ERROR "'srec_cat' not found. Please install it, or add it to $PATH.")
endif()
#merge cpu0 and cpu1 to a single image
#offset is taken from zephyr,code-cpu1-partition
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${SREC_CAT}
ARGS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME} -Binary
${REMOTE_ZEPHYR_DIR}/${KERNEL_BIN_NAME} -Binary
-offset ${CONFIG_SECOND_CORE_BOOT_ADDRESS_MCUX}
-o ${CMAKE_BINARY_DIR}/multicore.bin -Binary
)
endif()

5
boards/arm/lpcxpresso55s69/board.cmake
View file

@ -8,10 +8,9 @@
## DAP Link implementation in pyocd is underway,
## until then jlink can be used or copy image to storage
if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0)
if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0 OR CONFIG_SECOND_CORE_MCUX)
board_runner_args(jlink "--device=LPC55S69_M33_0")
endif()
if(CONFIG_BOARD_LPCXPRESSO55S69_CPU1)
elseif(CONFIG_BOARD_LPCXPRESSO55S69_CPU1)
board_runner_args(jlink "--device=LPC55S69_M33_1")
endif()

12
soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt
View file

@ -16,15 +16,3 @@ zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
SECTIONS usb.ld)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
if (CONFIG_SECOND_CORE_MCUX)
set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)
string(CONFIGURE ${CONFIG_SECOND_IMAGE_MCUX} second_core_image)
add_custom_target(second_core_inc_target DEPENDS ${gen_dir}/second-core.inc)
generate_inc_file_for_gen_target(${ZEPHYR_CURRENT_LIBRARY}
${second_core_image}
${gen_dir}/second-core.inc
second_core_inc_target)
endif()

16
soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc
View file

@ -120,14 +120,8 @@ config SECOND_CORE_MCUX
bool "LPC55xxx's second core"
depends on HAS_MCUX
help
Driver for second core startup
config SECOND_IMAGE_MCUX
depends on SECOND_CORE_MCUX
string "Binary image of second core's code"
help
This points to the image file for the the binary code that will be
used by the second core.
Indicates the second core will be enabled, and the part will run
in dual core mode.
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
@ -139,4 +133,10 @@ config SECOND_CORE_BOOT_ADDRESS_MCUX
help
This is the address the second core will boot from.
# Move the LMA for the second core image to be in the flash region of primary
# core, so that JLink flash will load it correctly.
config BUILD_OUTPUT_ADJUST_LMA
depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
default "0x10000000"
endif # SOC_SERIES_LPC55XXX