From fa85670f1b00613cc6584a845935bff9b8159789 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 1 Apr 2022 09:16:50 +0200 Subject: [PATCH] tests/drivers/clock_control: stm32f1: HSI clock is 8MHz On STM32F series, HSI clock is 8MHz, fix test using 16MHz and a test name. Signed-off-by: Erwan Gouriou --- .../stm32_clock_configuration/stm32_common/testcase.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml index dfbcb952a0d..2f536cf7cb5 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml @@ -92,12 +92,12 @@ tests: extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f0_f3_pll_32_hse_8.overlay" platform_allow: nucleo_f091rc stm32f3_disco drivers.stm32_clock_configuration.common.f1.sysclksrc_hsi_8: - extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_16.overlay" + extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hsi_8.overlay" platform_allow: nucleo_f103rb drivers.stm32_clock_configuration.common.f1.sysclksrc_hse_8: extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/hse_8.overlay" platform_allow: nucleo_f103rb - drivers.stm32_clock_configuration.common.f1.sysclksrc_pll_64_hsi_16: + drivers.stm32_clock_configuration.common.f1.sysclksrc_pll_64_hsi_8: extra_args: DTC_OVERLAY_FILE="boards/clear_f0_f1_f3_clocks.overlay;boards/f1_pll_64_hsi_8.overlay" platform_allow: nucleo_f103rb drivers.stm32_clock_configuration.common.f1.sysclksrc_pll_64_hse_8: