boards: Add MAX32662EVKIT board
Add MAX32662EVKIT board files For more information about this board please check https://www.analog.com/ Co-authored-by: Maureen Helm <maureen.helm@analog.com> Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
This commit is contained in:
Sadik Ozer
Anas Nashif
parent
7323757e36
commit
fa0d08c70a
8 changed files with 343 additions and 0 deletions
7
boards/adi/max32662evkit/Kconfig.max32662evkit
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7
boards/adi/max32662evkit/Kconfig.max32662evkit
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# MAX32662EVKIT boards configuration
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# Copyright (c) 2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MAX32662EVKIT
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select SOC_MAX32662
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boards/adi/max32662evkit/board.cmake
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boards/adi/max32662evkit/board.cmake
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# Copyright (c) 2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
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board_runner_args(openocd --cmd-pre-init "source [find target/max32662.cfg]")
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board_runner_args(jlink "--device=MAX32662" "--reset-after-load")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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8
boards/adi/max32662evkit/board.yml
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boards/adi/max32662evkit/board.yml
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# Copyright (c) 2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: max32662evkit
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vendor: adi
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socs:
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- name: max32662
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BIN
boards/adi/max32662evkit/doc/img/max32662evkit.webp
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boards/adi/max32662evkit/doc/img/max32662evkit.webp
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boards/adi/max32662evkit/doc/index.rst
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boards/adi/max32662evkit/doc/index.rst
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.. _max32662_evkit:
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MAX32662EVKIT
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#############
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Overview
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********
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The MAX32662 evaluation kit (EV kit) provides a platform for evaluating
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the capabilities of the MAX32662 microcontroller, which is a cost-effective,
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ultra-low power, highly integrated 32-bit microcontroller designed
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for battery-powered edge devices.
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The Zephyr port is running on the MAX32662 MCU.
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.. image:: img/max32662evkit.webp
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:align: center
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:alt: MAX32662EVKIT
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Hardware
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********
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- MAX32662 MCU:
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- High-Efficiency Microcontroller for Low-Power High-Reliability Devices
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- 256KB Flash
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- 80KB SRAM, Optionally Preserved in LowestPower BACKUP Mode
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- 16KB Unified Cache
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- Memory Protection Unit (MPU)
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- Dual- or Single-Supply Operation: 1.7V to 3.6V
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- Wide Operating Temperature: -40°C to +105°C
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- Flexible Clocking Schemes
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- Internal High-Speed 100MHz
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- Internal Low-Power 7.3728MHz
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- Ultra-Low-Power 80kHz
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- 16MHz–32MHz (External Crystal Required)
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- 32.768kHz (External Crystal Required)
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- External Clock Inputs for CPU and Low-PowerTimer
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- Power Management Maximizes Uptime for Battery Applications
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- 50μA/MHz at 0.9V up to 12MHz (CoreMark®) inACTIVE Mode
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- 44μA/MHz at 1.1V up to 100MHz (While(1)) inACTIVE Mode
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- 2.15μA Full Memory Retention Current in BACKUPMode at VDDIO = 1.8V
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- 2.4μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V
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- 350nA Ultra-Low-Power RTC
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- Wakeup from Low-Power Timer
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- Optimal Peripheral Mix Provides Platform Scalability
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- Up to 21 General-Purpose I/O Pins
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- 4-Channel, 12-Bit, 1Msps ADC
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- Two SPI Controller/Target
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- One I2S Controller/Target
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- Two 4-Wire UART
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- Two I2C Controller/Target
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- One CAN 2.0B Controller
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- 4-Channel Standard DMA Controller
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- Three 32-Bit Timers
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- One 32-Bit Low-Power Timer
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- One Watchdog Timer
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- CMOS-Level 32.768kHz Calibration Output
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- AES-128/192/256 Hardware Accelerator
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- Benefits and Features of MAX32662EVKIT:
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- 3-Pin Terminal Block for CAN Bus 2.0B
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- 128 x 128 (1.45in) Color TFT Display with SPI Interface
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- Selectable On-Board High-Precision Voltage Reference
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- USB 2.0 Micro-B to Serial UART
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- All GPIOs Signals Accessed through 0.1in Headers
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- Four Analog Inputs Accessed through 0.1in Header
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- SWD 10-Pin Header
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- Board Power Provided by USB Port
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- On-Board LDO Regulators
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- Individual Power Measurement on All IC Rails through Jumpers
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- One General-Purpose LED
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- One General-Purpose Pushbutton Switch
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Supported Features
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==================
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Below interfaces are supported by Zephyr on MAX32662EVKIT.
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock and reset control |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial |
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+-----------+------------+-------------------------------------+
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Connections and IOs
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===================
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| Name | Name | Settings | Description |
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+===========+===============+===============+==================================================================================================+
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| JP1 | VREF EN | | |
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| | | +-----------+ | +-------------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the external voltage reference to the VREF pin; must be enabled in the software. | |
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| | | | | | | See the External Voltage Reference (VREF) section for additional information. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the external voltage reference. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP2 | I2C1_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the pull-up to I2C1A_SCL (P0.6); sourced by V_AUX. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the pull-up from I2C1A_SCL (P0.6); sourced by V_AUX. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP3 | N/A | N/A | Does not exist. |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP4 | I2C1_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the pull-up to I2C1A_SDA (P0.9); sourced by V_AUX. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Oepn | | | Disconnects the pull-up from I2C1A_SDA (P0.9); sourced by V_AUX. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables LED0. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables LED0. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP6 | CTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_CTS (P0.20). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_CTS (P0.20). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP7 | RX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RX (P0.11). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RX (P0.11). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP8 | TX0A EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_TX (P0.10). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_TX (P0.10). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP9 | RTS0A EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the USB-to-serial bridge to UART0A_RTS (P0.19). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the USB-to-serial bridge from UART0A_RTS (P0.19). | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP10 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects 1V1 to VCORE. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects 1V1 from VCORE. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP11 | VDDIO/VDDASEL | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-1 | | | Connects 1V8 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 2-3 | | | Connects 3V3 to V_AUX, VDDIO EN (JP12), and VDDA EN (JP13) jumpers. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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| JP12 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Connects the JP11 selected voltage to VDDIO. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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| | | | Open | | | Disconnects the voltage from VDDIO. | |
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| | | +-----------+ | +-------------------------------------------------------------------------------+ |
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+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
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Programming and Debugging
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*************************
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Flashing
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========
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An Arm® debug access port (DAP) provides an external interface for debugging during application
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development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial
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interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J3). Logic levels are set
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to V_AUX (1V8 or 3V3), which is determined by the shunt placement on JP11. In addition,
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the UART1A port can also be accessed through J3.
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Once the debug probe is connected to your host computer, then you can simply run the
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``west flash`` command to write a firmware image into flash.
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.. note::
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This board uses OpenOCD as the default debug interface. You can also use
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a Segger J-Link with Segger's native tooling by overriding the runner,
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appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
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be connected to the standard 2*5 pin debug connector (J3) using an
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appropriate adapter board and cable.
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Debugging
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=========
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Please refer to the `Flashing`_ section and run the ``west debug`` command
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instead of ``west flash``.
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References
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**********
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- `MAX32662EVKIT web page`_
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.. _MAX32662EVKIT web page:
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https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32662evkit.html
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65
boards/adi/max32662evkit/max32662evkit.dts
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65
boards/adi/max32662evkit/max32662evkit.dts
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/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <adi/max32/max32662.dtsi>
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#include <adi/max32/max32662-pinctrl.dtsi>
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#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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model = "Analog Devices MAX32662EVKIT";
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compatible = "adi,max32662evkit";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &sram2;
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zephyr,flash = &flash0;
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};
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leds {
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compatible = "gpio-leds";
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led1: led_1 {
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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label = "Red LED";
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};
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};
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buttons {
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compatible = "gpio-keys";
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pb1: pb1 {
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gpios = <&gpio0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW
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| MAX32_GPIO_VSEL_VDDIOH)>;
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label = "SW3";
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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/* These aliases are provided for compatibility with samples */
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aliases {
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led0 = &led1;
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sw0 = &pb1;
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0a_tx_p0_10 &uart0a_rx_p0_11>;
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pinctrl-names = "default";
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current-speed = <115200>;
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data-bits = <8>;
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parity = "none";
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status = "okay";
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};
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&clk_ipo {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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14
boards/adi/max32662evkit/max32662evkit.yaml
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14
boards/adi/max32662evkit/max32662evkit.yaml
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identifier: max32662evkit
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name: max32662evkit
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vendor: adi
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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supported:
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- gpio
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- serial
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ram: 80
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flash: 256
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13
boards/adi/max32662evkit/max32662evkit_defconfig
Normal file
13
boards/adi/max32662evkit/max32662evkit_defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
||||||
|
# Copyright (c) 2024 Analog Devices, Inc.
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
# Enable GPIO
|
||||||
|
CONFIG_GPIO=y
|
||||||
|
|
||||||
|
# Console
|
||||||
|
CONFIG_CONSOLE=y
|
||||||
|
CONFIG_UART_CONSOLE=y
|
||||||
|
|
||||||
|
# Enable UART
|
||||||
|
CONFIG_SERIAL=y
|
||||||
|
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||||
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Add table
Add a link
Reference in a new issue