soc: Add the MAX32657 SoC

MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure

This commit defines Secure version of peripherals.

Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
   - 1 x UART
   - 1 x I2C/I3C
   - 1 x SPI
   - 6 x TIMER
   - 1 x RTC
   - 1 x WDT
   - 1 x TRNG

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>

dts/arm/adi/max32/max32657-pinctrl.dtsi

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2024-2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/ i3c_scl_p0_0: i3c_scl_p0_0 {
+		pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+	};
+
+	/omit-if-no-ref/ i3c_sda_p0_1: i3c_sda_p0_1 {
+		pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_mosi_p0_2: spi0_mosi_p0_2 {
+		pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_ss0_p0_3: spi0_ss0_p0_3 {
+		pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
+		pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+	};
+
+	/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
+		pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
+		pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_ss1_p0_7: spi0_ss1_p0_7 {
+		pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+	};
+
+	/omit-if-no-ref/ spi0_ss2_p0_8: spi0_ss2_p0_8 {
+		pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+	};
+
+	/omit-if-no-ref/ uart0_tx_p0_9: uart0_tx_p0_9 {
+		pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+	};
+
+	/omit-if-no-ref/ sqwout_p0_13: sqwout_p0_13 {
+		pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+	};
+
+	/omit-if-no-ref/ tmr0a_p0_0: tmr0a_p0_0 {
+		pinmux = <MAX32_PINMUX(0, 0, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr1a_p0_1: tmr1a_p0_1 {
+		pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr3a_p0_2: tmr3a_p0_2 {
+		pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr4a_p0_3: tmr4a_p0_3 {
+		pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr5a_p0_4: tmr5a_p0_4 {
+		pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr0b_p0_5: tmr0b_p0_5 {
+		pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr4b_p0_6: tmr4b_p0_6 {
+		pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr3b_p0_7: tmr3b_p0_7 {
+		pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+	};
+
+	/omit-if-no-ref/ i3c_pur_p0_8: i3c_pur_p0_8 {
+		pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr1b_p0_9: tmr1b_p0_9 {
+		pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr2a_p0_10: tmr2a_p0_10 {
+		pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+	};
+
+	/omit-if-no-ref/ tmr5b_p0_11: tmr5b_p0_11 {
+		pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+	};
+};

dts/arm/adi/max32/max32657.dtsi

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024-2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/adi_max32_clock.h>
+
+/ {
+	soc {
+		sram: sram@30000000 {
+			ranges = <0x0 0x30000000 0x40000>;
+		};
+
+		peripheral: peripheral@50000000 {
+			ranges = <0x0 0x50000000 0x10000000>;
+
+			pinctrl: pin-controller@8000 {
+				ranges = <0x8000 0x50008000 0x1000>;
+			};
+
+			flc0: flash_controller@29000 {
+				compatible = "adi,max32-flash-controller";
+				reg = <0x29000 0x400>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+				status = "okay";
+
+				flash0: flash@1000000 {
+					compatible = "soc-nv-flash";
+					reg = <0x01000000 DT_SIZE_K(1024)>;
+					write-block-size = <16>;
+					erase-block-size = <8192>;
+				};
+			};
+		};
+	};
+};
+
+#include "max32657_common.dtsi"

dts/arm/adi/max32/max32657_common.dtsi

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2024-2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flc0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	clocks {
+		clk_ipo: clk_ipo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(50)>;
+			status = "disabled";
+		};
+
+		clk_inro: clk_inro {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = < DT_FREQ_K(8) >;
+			status = "disabled";
+		};
+
+		clk_ibro: clk_ibro {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = < 7372800 >;
+			status = "disabled";
+		};
+
+		clk_ertco: clk_ertco {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = < 32768 >;
+			status = "disabled";
+		};
+
+		clk_erfo: clk_erfo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(32)>;
+			status = "disabled";
+		};
+	};
+};
+
+&sram {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x0 DT_SIZE_K(32)>;
+	};
+
+	sram1: memory@8000 {
+		compatible = "mmio-sram";
+		reg = <0x8000 DT_SIZE_K(32)>;
+	};
+
+	sram2: memory@10000 {
+		compatible = "mmio-sram";
+		reg = <0x10000 DT_SIZE_K(64)>;
+	};
+
+	sram3: memory@20000 {
+		compatible = "mmio-sram";
+		reg = <0x20000 DT_SIZE_K(64)>;
+	};
+
+	sram4: memory@30000 {
+		compatible = "mmio-sram";
+		reg = <0x30000 DT_SIZE_K(64)>;
+	};
+};
+
+&peripheral {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	gcr: clock-controller@0 {
+		reg = <0x0 0x400>;
+		compatible = "adi,max32-gcr";
+		#clock-cells = <2>;
+		clocks = <&clk_ipo>;
+		sysclk-prescaler = <1>;
+		status = "okay";
+	};
+
+	pinctrl: pin-controller@8000 {
+		compatible = "adi,max32-pinctrl";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x8000 0x1000>;
+
+		gpio0: gpio@8000 {
+			reg = <0x8000 0x1000>;
+			compatible = "adi,max32-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>;
+			interrupts = <14 0>;
+			status = "disabled";
+		};
+	};
+
+	uart0: serial@42000 {
+		compatible = "adi,max32-uart";
+		reg = <0x42000 0x1000>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>;
+		clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+		interrupts = <11 0>;
+		status = "disabled";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

soc/adi/max32/Kconfig

@@ -9,6 +9,17 @@ config SOC_FAMILY_MAX32
 	select SOC_EARLY_INIT_HOOK
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
+config SOC_FAMILY_MAX32_M33
+	select ARM
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CLOCK_CONTROL
+	select CPU_CORTEX_M33
+	select ARM_TRUSTZONE_M
+	select CPU_HAS_ARM_SAU
+	select ARMV8_M_DSP
+
 config SOC_FAMILY_MAX32_M4
 	select ARM
 	select CPU_CORTEX_M4

soc/adi/max32/Kconfig.defconfig.max32657

@@ -0,0 +1,14 @@
+# Analog Devices MAX32657 MCU
+
+# Copyright (c) 2024-2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32657
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 54
+
+endif # SOC_MAX32657

soc/adi/max32/Kconfig.soc

@@ -6,6 +6,10 @@
 config SOC_FAMILY_MAX32
 	bool
 
+config SOC_FAMILY_MAX32_M33
+	bool
+	select SOC_FAMILY_MAX32
+
 config SOC_FAMILY_MAX32_M4
 	bool
 	select SOC_FAMILY_MAX32
@@ -25,6 +29,10 @@ config SOC_MAX32655_M4
 	select SOC_MAX32655
 	select SOC_FAMILY_MAX32_M4
 
+config SOC_MAX32657
+	bool
+	select SOC_FAMILY_MAX32_M33
+
 config SOC_MAX32660
 	bool
 	select SOC_FAMILY_MAX32_M4
@@ -88,6 +96,7 @@ config SOC_MAX78002_M4
 config SOC
 	default "max32650" if SOC_MAX32650
 	default "max32655" if SOC_MAX32655
+	default "max32657" if SOC_MAX32657
 	default "max32660" if SOC_MAX32660
 	default "max32662" if SOC_MAX32662
 	default "max32666" if SOC_MAX32666

soc/adi/max32/soc.yml

@@ -8,6 +8,7 @@ family:
   - name: max32655
     cpuclusters:
     - name: m4
+  - name: max32657
   - name: max32660
   - name: max32662
   - name: max32666