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arch: xtensa: modify asm for interrupt sections

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For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.

I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit is contained in:
Iuliana Prodan 2021-06-02 20:20:09 +03:00 • committed by Christopher Friedt
commit f9810ccbe1
2 changed files with 30 additions and 7 deletions
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23
arch/xtensa/include/xtensa-asm2-s.h
View file

@ -356,6 +356,11 @@ _restore_\@:
* with a simple jump instruction. * with a simple jump instruction.
*/ */
.macro DEF_EXCINT LVL, ENTRY_SYM, C_HANDLER_SYM .macro DEF_EXCINT LVL, ENTRY_SYM, C_HANDLER_SYM
#if defined(CONFIG_IMX) && (MEM_VECT_TEXT_SIZE <= 0x1C)
.pushsection .iram.text, "ax"
.global _Level\LVL\()VectorHelper
_Level\LVL\()VectorHelper :
#else
.if \LVL == 1 .if \LVL == 1
.pushsection .iram0.text, "ax" .pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL .elseif \LVL == XCHAL_DEBUGLEVEL
@ -367,6 +372,7 @@ _restore_\@:
.endif .endif
.global _Level\LVL\()Vector .global _Level\LVL\()Vector
_Level\LVL\()Vector: _Level\LVL\()Vector:
#endif
addi a1, a1, -BASE_SAVE_AREA_SIZE addi a1, a1, -BASE_SAVE_AREA_SIZE
s32i a0, a1, BSA_A0_OFF s32i a0, a1, BSA_A0_OFF
s32i a2, a1, BSA_A2_OFF s32i a2, a1, BSA_A2_OFF
@ -418,6 +424,23 @@ _after_imms\LVL:
l32r a0, _handle_excint_imm\LVL l32r a0, _handle_excint_imm\LVL
jx a0 jx a0
.popsection .popsection
#if defined(CONFIG_IMX) && (MEM_VECT_TEXT_SIZE <= 0x1C)
.if \LVL == 1
.pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL
.pushsection .DebugExceptionVector.text, "ax"
.elseif \LVL == XCHAL_NMILEVEL
.pushsection .NMIExceptionVector.text, "ax"
.else
.pushsection .Level\LVL\()InterruptVector.text, "ax"
.endif
.global _Level\LVL\()Vector
_Level\LVL\()Vector :
j _Level\LVL\()VectorHelper
.popsection
#endif
.endm .endm
#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H */ #endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H */

14
soc/xtensa/nxp_adsp/imx8/include/soc/memory.h
View file

@ -40,7 +40,7 @@
/* Vector and literal sizes */ /* Vector and literal sizes */
#define MEM_VECT_LIT_SIZE 0x4 #define MEM_VECT_LIT_SIZE 0x4
#define MEM_VECT_TEXT_SIZE 0x30 #define MEM_VECT_TEXT_SIZE 0x1C
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ #define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
MEM_VECT_LIT_SIZE) MEM_VECT_LIT_SIZE)
@ -51,22 +51,22 @@
(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \ #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
(XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \ #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
(XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \ #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
(XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \ #define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
(XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
#define XCHAL_USER_VECTOR_PADDR_IRAM \ #define XCHAL_USER_VECTOR_PADDR_IRAM \
(XCHAL_KERNEL_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \ #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
(XCHAL_USER_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE) (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
/* Location for the intList section which is later used to construct the /* Location for the intList section which is later used to construct the
* Interrupt Descriptor Table (IDT). This is a bogus address as this * Interrupt Descriptor Table (IDT). This is a bogus address as this