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arch: xtensa: modify asm for interrupt sections

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For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.

I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit is contained in:
Iuliana Prodan 2021-06-02 20:20:09 +03:00 • committed by Christopher Friedt
commit f9810ccbe1
2 changed files with 30 additions and 7 deletions
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23
arch/xtensa/include/xtensa-asm2-s.h
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@ -356,6 +356,11 @@ _restore_\@:
* with a simple jump instruction.
*/
.macro DEF_EXCINT LVL, ENTRY_SYM, C_HANDLER_SYM
#if defined(CONFIG_IMX) && (MEM_VECT_TEXT_SIZE <= 0x1C)
.pushsection .iram.text, "ax"
.global _Level\LVL\()VectorHelper
_Level\LVL\()VectorHelper :
#else
.if \LVL == 1
.pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL
@ -367,6 +372,7 @@ _restore_\@:
.endif
.global _Level\LVL\()Vector
_Level\LVL\()Vector:
#endif
addi a1, a1, -BASE_SAVE_AREA_SIZE
s32i a0, a1, BSA_A0_OFF
s32i a2, a1, BSA_A2_OFF
@ -418,6 +424,23 @@ _after_imms\LVL:
l32r a0, _handle_excint_imm\LVL
jx a0
.popsection
#if defined(CONFIG_IMX) && (MEM_VECT_TEXT_SIZE <= 0x1C)
.if \LVL == 1
.pushsection .iram0.text, "ax"
.elseif \LVL == XCHAL_DEBUGLEVEL
.pushsection .DebugExceptionVector.text, "ax"
.elseif \LVL == XCHAL_NMILEVEL
.pushsection .NMIExceptionVector.text, "ax"
.else
.pushsection .Level\LVL\()InterruptVector.text, "ax"
.endif
.global _Level\LVL\()Vector
_Level\LVL\()Vector :
j _Level\LVL\()VectorHelper
.popsection
#endif
.endm
#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_XTENSA_ASM2_S_H */