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boards: arm: Introduce Infineon CYW920829M2EVK-02 board

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- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
  clocks instead of just one or the other

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi 2024-05-09 14:07:58 -07:00 • committed by Anas Nashif
commit f96e6ccbc0
46 changed files with 2952 additions and 12 deletions
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7
boards/infineon/cyw920829m2evk_02/Kconfig.cyw920829m2evk_02 Normal file
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# The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02)
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
config BOARD_CYW920829M2EVK_02
select SOC_CYW20829B0LKML

4
boards/infineon/cyw920829m2evk_02/board.cmake Normal file
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

5
boards/infineon/cyw920829m2evk_02/board.yml Normal file
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@ -0,0 +1,5 @@
board:
name: cyw920829m2evk_02
vendor: infineon
socs:
- name: cyw20829b0lkml

60
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-common.dtsi Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (c) 2024 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &user_led0;
led1 = &user_led1;
sw0 = &user_bt0;
sw1 = &user_bt1;
};
leds {
compatible = "gpio-leds";
user_led0: led_0 {
label = "LED_0";
gpios = <&gpio_prt1 1 GPIO_ACTIVE_LOW>;
};
user_led1: led_1 {
label = "LED_1";
gpios = <&gpio_prt5 2 GPIO_ACTIVE_LOW>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt0: user_btn0 {
label = "SW_1";
gpios = <&gpio_prt0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
user_bt1: user_btn1 {
label = "SW_2";
gpios = <&gpio_prt1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
&gpio_prt0 {
status = "okay";
};
&gpio_prt1 {
status = "okay";
};
&gpio_prt3 {
status = "okay";
};
&gpio_prt5 {
status = "okay";
};

13
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02-pinctrl.dtsi Normal file
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/*
* Copyright (c) 2024 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/* Configure pin control bias mode for uart2 pins */
&p3_3_scb2_uart_tx {
drive-push-pull;
};
&p3_2_scb2_uart_rx {
input-enable;
};

107
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts Normal file
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@ -0,0 +1,107 @@
/*
* Copyright (c) 2024 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/infineon/cat1b/mpns/CYW20829B0LKML.dtsi>
#include <arm/infineon/cat1b/cyw20829/system_clocks.dtsi>
#include "cyw920829m2evk_02-common.dtsi"
#include "cyw920829m2evk_02-pinctrl.dtsi"
/ {
model = "The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02)";
compatible = "infineon,cyw920829m2evk_02", "infineon,CYW20829";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &app_region;
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};
uart2: &scb2 {
compatible = "infineon,cat1-uart";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx>;
pinctrl-names = "default";
};
&fll0 {
status = "okay";
};
&path_mux0 {
status = "okay";
};
&path_mux1 {
status = "okay";
};
&path_mux2 {
status = "okay";
};
&path_mux3 {
status = "okay";
};
&clk_hf0 {
status = "okay";
clocks = <&fll0>;
};
&clk_hf1 {
status = "okay";
};
&clk_hf2 {
status = "okay";
};
&clk_hf3 {
status = "okay";
};
&flash_controller {
flash0: flash@60000000 {
compatible = "soc-nv-flash";
reg = <0x60000000 DT_SIZE_K(512)>;
write-block-size = <16>;
erase-block-size = <256>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
toc2_region: flash@60000000 {
compatible = "zephyr,memory-region", "soc-nv-flash";
zephyr,memory-region = "APP_HEADER_FLASH";
reg = <0x60000000 0x50>;
};
bootstrap_region: flash@60000050 {
compatible = "zephyr,memory-region", "soc-nv-flash";
zephyr,memory-region = "BOOTSTRAP_FLASH";
reg = <0x60000050 0x2550>;
};
app_region: flash@60002600 {
compatible = "soc-nv-flash";
reg = <0x60002600 0x5da00>;
};
storage_partition: flash@60060000 {
compatible = "soc-nv-flash";
reg = <0x60060000 0x20000>;
};
};
};
};

21
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml Normal file
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#
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
identifier: cyw920829m2evk_02
name: The Infineon AIROC™ CYW20829 Bluetooth® LE evaluation kit (CYW92089M2EVK-02)
type: mcu
arch: arm
ram: 1024
flash: 2048
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
- uart
- clock_control
- bluetooth
vendor: infineon

31
boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig Normal file
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#
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# General configuration
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable pin controller
CONFIG_PINCTRL=y
# Enable GPIO driver
CONFIG_GPIO=y
# Enable clock controller
CONFIG_CLOCK_CONTROL=y
# Main Stack Size
CONFIG_MAIN_STACK_SIZE=2048

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boards/infineon/cyw920829m2evk_02/doc/img/cyw920829m2evk_02.webp Normal file
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125
boards/infineon/cyw920829m2evk_02/doc/index.rst Normal file
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.. _cyw920829m2evk_02:
INFINEON CYW920829M2EVK-02
############################
Overview
********
The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with its included on-board peripherals enables evaluation, prototyping, and development of a wide array of Bluetooth® Low Energy applications, all on Infineon's low power, high performance AIROC™ CYW20829. The AIROC™ CYW20829's robust RF performance and 10 dBm TX output power without an external power amplifier (PA). This provides enough link budget for the entire spectrum of Bluetooth® LE use cases including industrial IoT applications, smart home, asset tracking, beacons and sensors, and medical devices.
The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO support with extended headers and Arduino Uno R3 compatibility for third-party shields.
.. image:: img/cyw920829m2evk_02.webp
:align: center
:alt: CYW920829M2EVK_02
Hardware
********
For more information about the CYW20829 SoC and CYW920829M2EVK-02 board:
- `CYW920829M2EVK-02 Website`_
- `CYW920829M2EVK-02 BT User Guide`_
Kit Features:
=============
- AIROC™ CYW20829 Bluetooth® LE MCU in 56 pin QFN package
- Arduino compatible headers for hardware expansion
- On-board sensors - 6-axis IMU, Thermistor, Infineon analog microphone, and Infineon digital microphone
- User switches, RGB LED and user LEDs
- USB connector for power, programming and USB-UART bridge
Kit Contents:
=============
- CYW20829 evaluation board (CYW9BTM2BASE3+CYW920829M2IPA2)
- USB Type-A to Micro-B cable
- Six jumper wires (five inches each)
- Quick start guide
Supported Features
==================
The board configuration supports the following hardware features:
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| NVIC | on-chip | nested vectored |
| | | interrupt controller |
+-----------+------------+-----------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-----------------------+
| GPIO | on-chip | GPIO |
+-----------+------------+-----------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-----------------------+
The default configuration can be found in the Kconfig
:zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig`
System Clock
============
The AIROC™ CYW20829 Bluetooth® MCU SoC is configured to use the internal IMO+FLL as a source for
the system clock. Other sources for the system clock are provided in the SOC, depending on your
system requirements.
Build blinking led sample
*************************
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: cyw920829m2evk_02
:goals: build flash
OpenOCD Installation
====================
To get the OpenOCD package, it is required that you
1. Download and install the `ModusToolbox`_ software.
2. After the installation, add the directory containing the OpenOCD scripts to your environment's PATH variable.
Programming and Debugging
*************************
The CYW920829M2EVK-02 includes an onboard programmer/debugger (KitProg3) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands must be pointed to the Cypress OpenOCD you downloaded above.
On Windows:
.. code-block:: console
west flash --openocd path/to/infineon/openocd/bin/openocd.exe
west debug --openocd path/to/infineon/openocd/bin/openocd.exe
On Linux:
.. code-block:: console
west flash --openocd path/to/infineon/openocd/bin/openocd
west debug --openocd path/to/infineon/openocd/bin/openocd
Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the CYW20829 CM33 core.
.. _CYW920829M2EVK-02 Website:
https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/
.. _CYW920829M2EVK-02 BT User Guide:
https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-bluetooth-le-bluetooth-multiprotocol/airoc-bluetooth-le/cyw20829/#!?fileId=8ac78c8c8929aa4d018a16f726c46b26
.. _ModusToolbox:
https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox
.. _Infineon OpenOCD:
https://github.com/infineon/openocd/releases/tag/release-v4.3.0

10
boards/infineon/cyw920829m2evk_02/support/openocd.cfg Normal file
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#
# Copyright (c) 2018 Linaro Limited.
#
# SPDX-License-Identifier: Apache-2.0
source [find interface/kitprog3.cfg]
transport select swd
source [find target/cyw20829.cfg]

29
boards/infineon/cyw920829m2evk_02/support/qspi_config.cfg Normal file
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################################################################################
# File Name: qspi_config.cfg
#
# Description:
# This file contains a SMIF Bank layout for use with OpenOCD.
# This file was automatically generated and should not be modified.
# QSPI Configurator: 4.22.0.1756
#
################################################################################
# Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
set SMIF_BANKS {
0 {addr 0x60000000 size 0x100000 psize 0x0000100 esize 0x0001000}
}

268
drivers/clock_control/clock_control_ifx_cat1.c
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@ -18,7 +18,13 @@
/* Enumeration of enabled in device tree Clock, uses for indexing clock info table */
enum {
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_imo), okay)
INFINEON_CAT1_CLOCK_IMO,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_iho), okay)
INFINEON_CAT1_CLOCK_IHO,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(path_mux0), okay)
INFINEON_CAT1_CLOCK_PATHMUX0,
@ -60,6 +66,42 @@ enum {
INFINEON_CAT1_CLOCK_HF4,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf5), okay)
INFINEON_CAT1_CLOCK_HF5,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf6), okay)
INFINEON_CAT1_CLOCK_HF6,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf7), okay)
INFINEON_CAT1_CLOCK_HF7,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf8), okay)
INFINEON_CAT1_CLOCK_HF8,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf9), okay)
INFINEON_CAT1_CLOCK_HF9,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf10), okay)
INFINEON_CAT1_CLOCK_HF10,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf11), okay)
INFINEON_CAT1_CLOCK_HF11,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf12), okay)
INFINEON_CAT1_CLOCK_HF12,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf13), okay)
INFINEON_CAT1_CLOCK_HF13,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_fast), okay)
INFINEON_CAT1_CLOCK_FAST,
#endif
@ -100,7 +142,13 @@ struct infineon_cat1_clock_info_t {
static struct infineon_cat1_clock_info_t
clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = {
/* We always have IMO */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_imo), okay)
[INFINEON_CAT1_CLOCK_IMO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_iho), okay)
[INFINEON_CAT1_CLOCK_IHO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_iho)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(path_mux0), okay)
[INFINEON_CAT1_CLOCK_PATHMUX0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux0)) },
@ -142,6 +190,42 @@ static struct infineon_cat1_clock_info_t
[INFINEON_CAT1_CLOCK_HF4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf4)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf5), okay)
[INFINEON_CAT1_CLOCK_HF5] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf5)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf6), okay)
[INFINEON_CAT1_CLOCK_HF6] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf6)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf7), okay)
[INFINEON_CAT1_CLOCK_HF7] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf7)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf8), okay)
[INFINEON_CAT1_CLOCK_HF8] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf8)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf9), okay)
[INFINEON_CAT1_CLOCK_HF9] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf9)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf10), okay)
[INFINEON_CAT1_CLOCK_HF10] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf10)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf11), okay)
[INFINEON_CAT1_CLOCK_HF11] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf11)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf12), okay)
[INFINEON_CAT1_CLOCK_HF12] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf12)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf13), okay)
[INFINEON_CAT1_CLOCK_HF13] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf13)) },
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_fast), okay)
[INFINEON_CAT1_CLOCK_FAST] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_fast)) },
#endif
@ -242,13 +326,67 @@ static cyhal_clock_t *_get_hal_obj_from_ord(uint32_t dt_ord)
return ret_obj;
}
#if DT_NODE_HAS_STATUS(DT_NODELABEL(dpll_hp), okay)
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while (1) {
}
}
void Cy_SysClk_Dpll_Hp0_Init(void)
{
#define CY_CFG_SYSCLK_PLL_ERROR 3
static cy_stc_dpll_hp_config_t srss_0_clock_0_pll500m_0_hp_pllConfig = {
.pDiv = 0,
.nDiv = 15,
.kDiv = 1,
.nDivFract = 0,
.freqModeSel = CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL,
.ivrTrim = 0x8U,
.clkrSel = 0x1U,
.alphaCoarse = 0xCU,
.betaCoarse = 0x5U,
.flockThresh = 0x3U,
.flockWait = 0x6U,
.flockLkThres = 0x7U,
.flockLkWait = 0x4U,
.alphaExt = 0x14U,
.betaExt = 0x14U,
.lfEn = 0x1U,
.dcEn = 0x1U,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
static cy_stc_pll_manual_config_t srss_0_clock_0_pll500m_0_pllConfig = {
.hpPllCfg = &srss_0_clock_0_pll500m_0_hp_pllConfig,
};
#if !defined(CY_PDL_TZ_ENABLED)
if (Cy_SysClk_PllIsEnabled(SRSS_DPLL_HP_0_PATH_NUM)) {
return;
}
#endif
Cy_SysClk_PllDisable(SRSS_DPLL_HP_0_PATH_NUM);
if (CY_SYSCLK_SUCCESS !=
Cy_SysClk_PllManualConfigure(SRSS_DPLL_HP_0_PATH_NUM,
&srss_0_clock_0_pll500m_0_pllConfig)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_DPLL_HP_0_PATH_NUM, 10000u)) {
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
#endif
static int clock_control_infineon_cat1_init(const struct device *dev)
{
ARG_UNUSED(dev);
cy_rslt_t rslt;
cyhal_clock_t *clock_obj = NULL;
cyhal_clock_t *clock_source_obj = NULL;
uint32 frequency;
__attribute__((unused)) uint32 frequency;
uint32 clock_div;
/* Configure IMO */
@ -257,8 +395,16 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IMO)) {
return -EIO;
}
#else
#error "IMO clock must be enabled"
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_iho), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj;
if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IHO)) {
return -EIO;
}
#endif
#if !DT_NODE_HAS_STATUS(DT_NODELABEL(clk_imo), okay) && \
!DT_NODE_HAS_STATUS(DT_NODELABEL(clk_iho), okay)
#error "IMO clock or IHO clock must be enabled"
#endif
/* Configure the PathMux[0] to source defined in tree device 'path_mux0' node */
@ -403,6 +549,105 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
}
#endif
/* Configure the HF[5] to source defined in tree device 'clk_hf5' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf5), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf5));
clock_div = DT_PROP(DT_NODELABEL(clk_hf5), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[5], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[6] to source defined in tree device 'clk_hf6' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf6), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf6));
clock_div = DT_PROP(DT_NODELABEL(clk_hf6), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[6], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[7] to source defined in tree device 'clk_hf7' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf7), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf7));
clock_div = DT_PROP(DT_NODELABEL(clk_hf7), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[7], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[8] to source defined in tree device 'clk_hf8' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf8), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf8));
clock_div = DT_PROP(DT_NODELABEL(clk_hf8), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[8], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[9] to source defined in tree device 'clk_hf9' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf9), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf9));
clock_div = DT_PROP(DT_NODELABEL(clk_hf9), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[9], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[10] to source defined in tree device 'clk_hf10' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf10), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf10));
clock_div = DT_PROP(DT_NODELABEL(clk_hf10), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[10], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[11] to source defined in tree device 'clk_hf11' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf11), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf11));
clock_div = DT_PROP(DT_NODELABEL(clk_hf11), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[11], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[12] to source defined in tree device 'clk_hf12' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf12), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf12));
clock_div = DT_PROP(DT_NODELABEL(clk_hf12), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[12], clock_div)) {
return -EIO;
}
#endif
/* Configure the HF[13] to source defined in tree device 'clk_hf13' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_hf13), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj;
clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf13));
clock_div = DT_PROP(DT_NODELABEL(clk_hf13), clock_div);
if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[13], clock_div)) {
return -EIO;
}
#endif
/* Configure the clock fast to source defined in tree device 'clk_fast' node */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_fast), okay)
clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj;
@ -445,6 +690,11 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
}
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(dpll_hp), okay)
Cy_SysClk_Dpll_Hp0_Init();
SystemCoreClockUpdate();
#endif
return (int) rslt;
}
@ -463,6 +713,7 @@ static const struct clock_control_driver_api clock_control_infineon_cat1_api = {
.off = clock_control_infineon_cat_on_off
};
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_imo), okay)
DEVICE_DT_DEFINE(DT_NODELABEL(clk_imo),
&clock_control_infineon_cat1_init,
NULL,
@ -471,3 +722,14 @@ DEVICE_DT_DEFINE(DT_NODELABEL(clk_imo),
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&clock_control_infineon_cat1_api);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(clk_iho), okay)
DEVICE_DT_DEFINE(DT_NODELABEL(clk_iho),
&clock_control_infineon_cat1_init,
NULL,
NULL,
NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
&clock_control_infineon_cat1_api);
#endif

8
drivers/gpio/gpio_ifx_cat1.c
View file

@ -59,7 +59,15 @@ struct gpio_cat1_data {
/* Map port number to device object */
static const struct device *const port_dev_obj[IOSS_GPIO_GPIO_PORT_NR] = {
/* the integer used as the first variable in listify is equivalent to
* IOSS_GPIO_GPIO_PORT_NR for the respective categories, but using
* the macro in LISTIFY causes build failures
*/
#if CONFIG_SOC_FAMILY_INFINEON_CAT1A
LISTIFY(15, GET_DEV_OBJ_FROM_LIST, (,))
#elif CONFIG_SOC_FAMILY_INFINEON_CAT1B
LISTIFY(6, GET_DEV_OBJ_FROM_LIST, (,))
#endif
};
static int gpio_cat1_configure(const struct device *dev,

7
dts/arm/infineon/cat1b/cyw20829/clock_source_def.h Normal file
View file

@ -0,0 +1,7 @@
/*
* Copyright (c) 2024, Cypress Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
#define CLK_SOURCE_IHO
#define CLK_SOURCE_PILO

206
dts/arm/infineon/cat1b/cyw20829/cyw20829.40-qfn.dtsi Normal file
View file

@ -0,0 +1,206 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
#include "cyw20829.dtsi"
/ {
soc {
pinctrl: pinctrl@40400000 {
/* scb_i2c_scl */
/omit-if-no-ref/ p1_2_scb2_i2c_scl: p1_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_2_scb2_i2c_scl: p3_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_0_scb0_i2c_scl: p4_0_scb0_i2c_scl {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_0_scb2_i2c_scl: p5_0_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
};
/* scb_i2c_sda */
/omit-if-no-ref/ p1_3_scb2_i2c_sda: p1_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_3_scb2_i2c_sda: p3_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_1_scb0_i2c_sda: p4_1_scb0_i2c_sda {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_1_scb2_i2c_sda: p5_1_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
};
/* scb_spi_m_clk */
/omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_m_clk: p1_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_m_clk: p3_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_miso */
/omit-if-no-ref/ p1_3_scb1_spi_m_miso: p1_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_m_miso: p3_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_m_miso: p4_1_scb0_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_mosi */
/omit-if-no-ref/ p1_2_scb1_spi_m_mosi: p1_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_m_mosi: p3_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_m_mosi: p4_0_scb0_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_m_select0: p1_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_m_select0: p5_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_m_select0: p5_1_scb0_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select1 */
/omit-if-no-ref/ p0_5_scb1_spi_m_select1: p0_5_scb1_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select2 */
/omit-if-no-ref/ p0_4_scb1_spi_m_select2: p0_4_scb1_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select3 */
/* scb_spi_s_clk */
/omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_s_clk: p1_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_s_clk: p3_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_miso */
/omit-if-no-ref/ p1_3_scb1_spi_s_miso: p1_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_s_miso: p3_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_s_miso: p4_1_scb0_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_mosi */
/omit-if-no-ref/ p1_2_scb1_spi_s_mosi: p1_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_s_mosi: p3_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_s_mosi: p4_0_scb0_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_s_select0: p1_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_s_select0: p5_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_s_select0: p5_1_scb0_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select1 */
/omit-if-no-ref/ p0_5_scb1_spi_s_select1: p0_5_scb1_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select2 */
/omit-if-no-ref/ p0_4_scb1_spi_s_select2: p0_4_scb1_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select3 */
/* scb_uart_cts */
/omit-if-no-ref/ p1_0_scb1_uart_cts: p1_0_scb1_uart_cts {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p4_0_scb2_uart_cts: p4_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p5_0_scb2_uart_cts: p5_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rts */
/omit-if-no-ref/ p1_1_scb1_uart_rts: p1_1_scb1_uart_rts {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_1_scb2_uart_rts: p3_1_scb2_uart_rts {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rx */
/omit-if-no-ref/ p1_2_scb1_uart_rx: p1_2_scb1_uart_rx {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_2_scb2_uart_rx: p3_2_scb2_uart_rx {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_tx */
/omit-if-no-ref/ p1_3_scb1_uart_tx: p1_3_scb1_uart_tx {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_3_scb2_uart_tx: p3_3_scb2_uart_tx {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
};
};
};
&gpio_prt0 {
ngpios = <2>;
};
&gpio_prt1 {
ngpios = <4>;
};
&gpio_prt3 {
ngpios = <3>;
};
&gpio_prt5 {
ngpios = <2>;
};

257
dts/arm/infineon/cat1b/cyw20829/cyw20829.56-qfn.dtsi Normal file
View file

@ -0,0 +1,257 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
#include "cyw20829.dtsi"
/ {
soc {
pinctrl: pinctrl@40400000 {
/* scb_i2c_scl */
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p1_2_scb2_i2c_scl: p1_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_2_scb2_i2c_scl: p3_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_0_scb0_i2c_scl: p4_0_scb0_i2c_scl {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_0_scb2_i2c_scl: p5_0_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
};
/* scb_i2c_sda */
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p1_3_scb2_i2c_sda: p1_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_3_scb2_i2c_sda: p3_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_1_scb0_i2c_sda: p4_1_scb0_i2c_sda {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_1_scb2_i2c_sda: p5_1_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
};
/* scb_spi_m_clk */
/omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_m_clk: p1_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_m_clk: p3_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_miso */
/omit-if-no-ref/ p0_3_scb0_spi_m_miso: p0_3_scb0_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_3_scb1_spi_m_miso: p1_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_m_miso: p3_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_m_miso: p4_1_scb0_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_mosi */
/omit-if-no-ref/ p0_2_scb0_spi_m_mosi: p0_2_scb0_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_2_scb1_spi_m_mosi: p1_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_m_mosi: p3_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_m_mosi: p4_0_scb0_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_m_select0: p1_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_0_scb1_spi_m_select0: p3_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_m_select0: p5_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_m_select0: p5_1_scb0_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select1 */
/omit-if-no-ref/ p0_0_scb0_spi_m_select1: p0_0_scb0_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_5_scb1_spi_m_select1: p0_5_scb1_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_6_scb1_spi_m_select1: p3_6_scb1_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select2 */
/omit-if-no-ref/ p0_1_scb0_spi_m_select2: p0_1_scb0_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_4_scb1_spi_m_select2: p0_4_scb1_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_5_scb1_spi_m_select2: p3_5_scb1_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select3 */
/omit-if-no-ref/ p0_3_scb1_spi_m_select3: p0_3_scb1_spi_m_select3 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_4_scb1_spi_m_select3: p3_4_scb1_spi_m_select3 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_clk */
/omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_s_clk: p1_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_s_clk: p3_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_miso */
/omit-if-no-ref/ p0_3_scb0_spi_s_miso: p0_3_scb0_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_3_scb1_spi_s_miso: p1_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_s_miso: p3_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_s_miso: p4_1_scb0_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_mosi */
/omit-if-no-ref/ p0_2_scb0_spi_s_mosi: p0_2_scb0_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_2_scb1_spi_s_mosi: p1_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_s_mosi: p3_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_s_mosi: p4_0_scb0_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_s_select0: p1_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_0_scb1_spi_s_select0: p3_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_s_select0: p5_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_s_select0: p5_1_scb0_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select1 */
/omit-if-no-ref/ p0_0_scb0_spi_s_select1: p0_0_scb0_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_5_scb1_spi_s_select1: p0_5_scb1_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_6_scb1_spi_s_select1: p3_6_scb1_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select2 */
/omit-if-no-ref/ p0_1_scb0_spi_s_select2: p0_1_scb0_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_4_scb1_spi_s_select2: p0_4_scb1_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_5_scb1_spi_s_select2: p3_5_scb1_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select3 */
/omit-if-no-ref/ p0_3_scb1_spi_s_select3: p0_3_scb1_spi_s_select3 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_4_scb1_spi_s_select3: p3_4_scb1_spi_s_select3 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_uart_cts */
/omit-if-no-ref/ p1_0_scb1_uart_cts: p1_0_scb1_uart_cts {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_0_scb2_uart_cts: p3_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p4_0_scb2_uart_cts: p4_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p5_0_scb2_uart_cts: p5_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rts */
/omit-if-no-ref/ p1_1_scb1_uart_rts: p1_1_scb1_uart_rts {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_1_scb2_uart_rts: p3_1_scb2_uart_rts {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rx */
/omit-if-no-ref/ p1_2_scb1_uart_rx: p1_2_scb1_uart_rx {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_2_scb2_uart_rx: p3_2_scb2_uart_rx {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_tx */
/omit-if-no-ref/ p1_3_scb1_uart_tx: p1_3_scb1_uart_tx {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_3_scb2_uart_tx: p3_3_scb2_uart_tx {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
};
};
};

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dts/arm/infineon/cat1b/cyw20829/cyw20829.77-bga.dtsi Normal file
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@ -0,0 +1,256 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
#include "cyw20829.dtsi"
/ {
soc {
pinctrl: pinctrl@40400000 {
/* scb_i2c_scl */
/omit-if-no-ref/ p0_2_scb0_i2c_scl: p0_2_scb0_i2c_scl {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p1_2_scb2_i2c_scl: p1_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_2_scb2_i2c_scl: p3_2_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_0_scb0_i2c_scl: p4_0_scb0_i2c_scl {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_0_scb2_i2c_scl: p5_0_scb2_i2c_scl {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
};
/* scb_i2c_sda */
/omit-if-no-ref/ p0_3_scb0_i2c_sda: p0_3_scb0_i2c_sda {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p1_3_scb2_i2c_sda: p1_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p3_3_scb2_i2c_sda: p3_3_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_7)>;
};
/omit-if-no-ref/ p4_1_scb0_i2c_sda: p4_1_scb0_i2c_sda {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_3)>;
};
/omit-if-no-ref/ p5_1_scb2_i2c_sda: p5_1_scb2_i2c_sda {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
};
/* scb_spi_m_clk */
/omit-if-no-ref/ p0_4_scb0_spi_m_clk: p0_4_scb0_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_m_clk: p1_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_m_clk: p3_1_scb1_spi_m_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_miso */
/omit-if-no-ref/ p0_3_scb0_spi_m_miso: p0_3_scb0_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_3_scb1_spi_m_miso: p1_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_m_miso: p3_3_scb1_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_m_miso: p4_1_scb0_spi_m_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_mosi */
/omit-if-no-ref/ p0_2_scb0_spi_m_mosi: p0_2_scb0_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_2_scb1_spi_m_mosi: p1_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_m_mosi: p3_2_scb1_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_m_mosi: p4_0_scb0_spi_m_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_m_select0: p1_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_0_scb1_spi_m_select0: p3_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_m_select0: p5_0_scb1_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_m_select0: p5_1_scb0_spi_m_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_m_select1 */
/omit-if-no-ref/ p0_0_scb0_spi_m_select1: p0_0_scb0_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_5_scb1_spi_m_select1: p0_5_scb1_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_6_scb1_spi_m_select1: p3_6_scb1_spi_m_select1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select2 */
/omit-if-no-ref/ p0_1_scb0_spi_m_select2: p0_1_scb0_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_4_scb1_spi_m_select2: p0_4_scb1_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_5_scb1_spi_m_select2: p3_5_scb1_spi_m_select2 {
pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_m_select3 */
/omit-if-no-ref/ p0_3_scb1_spi_m_select3: p0_3_scb1_spi_m_select3 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_4_scb1_spi_m_select3: p3_4_scb1_spi_m_select3 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_clk */
/omit-if-no-ref/ p0_4_scb0_spi_s_clk: p0_4_scb0_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_1_scb1_spi_s_clk: p1_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_1_scb1_spi_s_clk: p3_1_scb1_spi_s_clk {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_miso */
/omit-if-no-ref/ p0_3_scb0_spi_s_miso: p0_3_scb0_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_3_scb1_spi_s_miso: p1_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_3_scb1_spi_s_miso: p3_3_scb1_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_1_scb0_spi_s_miso: p4_1_scb0_spi_s_miso {
pinmux = <DT_CAT1_PINMUX(4, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_mosi */
/omit-if-no-ref/ p0_2_scb0_spi_s_mosi: p0_2_scb0_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(0, 2, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p1_2_scb1_spi_s_mosi: p1_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_2_scb1_spi_s_mosi: p3_2_scb1_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p4_0_scb0_spi_s_mosi: p4_0_scb0_spi_s_mosi {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select0 */
/omit-if-no-ref/ p1_0_scb1_spi_s_select0: p1_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_0_scb1_spi_s_select0: p3_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_0_scb1_spi_s_select0: p5_0_scb1_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p5_1_scb0_spi_s_select0: p5_1_scb0_spi_s_select0 {
pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_DS_6)>;
};
/* scb_spi_s_select1 */
/omit-if-no-ref/ p0_0_scb0_spi_s_select1: p0_0_scb0_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(0, 0, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_5_scb1_spi_s_select1: p0_5_scb1_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_6_scb1_spi_s_select1: p3_6_scb1_spi_s_select1 {
pinmux = <DT_CAT1_PINMUX(3, 6, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select2 */
/omit-if-no-ref/ p0_1_scb0_spi_s_select2: p0_1_scb0_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(0, 1, HSIOM_SEL_DS_6)>;
};
/omit-if-no-ref/ p0_4_scb1_spi_s_select2: p0_4_scb1_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_5_scb1_spi_s_select2: p3_5_scb1_spi_s_select2 {
pinmux = <DT_CAT1_PINMUX(3, 5, HSIOM_SEL_ACT_8)>;
};
/* scb_spi_s_select3 */
/omit-if-no-ref/ p0_3_scb1_spi_s_select3: p0_3_scb1_spi_s_select3 {
pinmux = <DT_CAT1_PINMUX(0, 3, HSIOM_SEL_ACT_8)>;
};
/omit-if-no-ref/ p3_4_scb1_spi_s_select3: p3_4_scb1_spi_s_select3 {
pinmux = <DT_CAT1_PINMUX(3, 4, HSIOM_SEL_ACT_8)>;
};
/* scb_uart_cts */
/omit-if-no-ref/ p1_0_scb1_uart_cts: p1_0_scb1_uart_cts {
pinmux = <DT_CAT1_PINMUX(1, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_0_scb2_uart_cts: p3_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(3, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p4_0_scb2_uart_cts: p4_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(4, 0, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p5_0_scb2_uart_cts: p5_0_scb2_uart_cts {
pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rts */
/omit-if-no-ref/ p1_1_scb1_uart_rts: p1_1_scb1_uart_rts {
pinmux = <DT_CAT1_PINMUX(1, 1, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_1_scb2_uart_rts: p3_1_scb2_uart_rts {
pinmux = <DT_CAT1_PINMUX(3, 1, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_rx */
/omit-if-no-ref/ p1_2_scb1_uart_rx: p1_2_scb1_uart_rx {
pinmux = <DT_CAT1_PINMUX(1, 2, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_2_scb2_uart_rx: p3_2_scb2_uart_rx {
pinmux = <DT_CAT1_PINMUX(3, 2, HSIOM_SEL_ACT_6)>;
};
/* scb_uart_tx */
/omit-if-no-ref/ p1_3_scb1_uart_tx: p1_3_scb1_uart_tx {
pinmux = <DT_CAT1_PINMUX(1, 3, HSIOM_SEL_ACT_6)>;
};
/omit-if-no-ref/ p3_3_scb2_uart_tx: p3_3_scb2_uart_tx {
pinmux = <DT_CAT1_PINMUX(3, 3, HSIOM_SEL_ACT_6)>;
};
};
};
};

301
dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi Normal file
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@ -0,0 +1,301 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
};
};
flash_controller: flash_controller@40250000 {
compatible = "infineon,cat1-flash-controller";
reg = <0x40250000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x3DC00>;
};
sram_bootstrap: memory@2003DC00 {
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "BOOTSTRAP_RAM";
reg = <0x2003DC00 0x2400>;
};
soc {
pinctrl: pinctrl@40400000 {
compatible = "infineon,cat1-pinctrl";
reg = <0x40400000 0x20000>;
};
hsiom: hsiom@40400000 {
compatible = "infineon,cat1-hsiom";
reg = <0x40400000 0x4000>;
interrupts = <7 6>, <6 6>;
status = "disabled";
};
gpio_prt0: gpio@40410000 {
compatible = "infineon,cat1-gpio";
reg = <0x40410000 0x80>;
interrupts = <0 6>;
gpio-controller;
ngpios = <6>;
status = "disabled";
#gpio-cells = <2>;
};
gpio_prt1: gpio@40410080 {
compatible = "infineon,cat1-gpio";
reg = <0x40410080 0x80>;
interrupts = <1 6>;
gpio-controller;
ngpios = <7>;
status = "disabled";
#gpio-cells = <2>;
};
gpio_prt2: gpio@40410100 {
compatible = "infineon,cat1-gpio";
reg = <0x40410100 0x80>;
interrupts = <2 6>;
gpio-controller;
ngpios = <6>;
status = "disabled";
#gpio-cells = <2>;
};
gpio_prt3: gpio@40410180 {
compatible = "infineon,cat1-gpio";
reg = <0x40410180 0x80>;
interrupts = <3 6>;
gpio-controller;
ngpios = <8>;
status = "disabled";
#gpio-cells = <2>;
};
gpio_prt4: gpio@40410200 {
compatible = "infineon,cat1-gpio";
reg = <0x40410200 0x80>;
interrupts = <4 6>;
gpio-controller;
ngpios = <2>;
status = "disabled";
#gpio-cells = <2>;
};
gpio_prt5: gpio@40410280 {
compatible = "infineon,cat1-gpio";
reg = <0x40410280 0x80>;
interrupts = <5 6>;
gpio-controller;
ngpios = <3>;
status = "disabled";
#gpio-cells = <2>;
};
ipc0: ipc@401d0000 {
compatible = "infineon,cat1-ipc";
reg = <0x401d0000 0x10000>;
status = "disabled";
#ipc-config-cells = <3>;
};
scb0: scb@40590000 {
compatible = "infineon,cat1-scb";
reg = <0x40590000 0xfd0>;
interrupts = <8 6>;
status = "disabled";
};
scb1: scb@405a0000 {
compatible = "infineon,cat1-scb";
reg = <0x405a0000 0xfd0>;
interrupts = <17 6>;
status = "disabled";
};
scb2: scb@405b0000 {
compatible = "infineon,cat1-scb";
reg = <0x405b0000 0xfd0>;
interrupts = <18 6>;
status = "disabled";
};
watchdog0: watchdog@4020c000 {
compatible = "infineon,cat1-watchdog";
reg = <0x4020c000 0x10>;
interrupts = <15 6>;
status = "disabled";
};
mcwdt0: mcwdt@4020d000 {
compatible = "infineon,cat1-lp-timer";
reg = <0x4020d000 0x40>;
interrupts = <9 6>;
status = "disabled";
};
counter0_0: counter@404a0000 {
compatible = "infineon,cat1-counter";
reg = <0x404a0000 0x80>;
interrupts = <42 6>;
resolution = <32>;
status = "disabled";
};
counter0_1: counter@404a0080 {
compatible = "infineon,cat1-counter";
reg = <0x404a0080 0x80>;
interrupts = <43 6>;
resolution = <32>;
status = "disabled";
};
counter1_0: counter@404a8000 {
compatible = "infineon,cat1-counter";
reg = <0x404a8000 0x80>;
interrupts = <44 6>;
resolution = <16>;
status = "disabled";
};
counter1_1: counter@404a8080 {
compatible = "infineon,cat1-counter";
reg = <0x404a8080 0x80>;
interrupts = <45 6>;
resolution = <16>;
status = "disabled";
};
counter1_2: counter@404a8100 {
compatible = "infineon,cat1-counter";
reg = <0x404a8100 0x80>;
interrupts = <46 6>;
resolution = <16>;
status = "disabled";
};
counter1_3: counter@404a8180 {
compatible = "infineon,cat1-counter";
reg = <0x404a8180 0x80>;
interrupts = <47 6>;
resolution = <16>;
status = "disabled";
};
counter1_4: counter@404a8200 {
compatible = "infineon,cat1-counter";
reg = <0x404a8200 0x80>;
interrupts = <48 6>;
resolution = <16>;
status = "disabled";
};
counter1_5: counter@404a8280 {
compatible = "infineon,cat1-counter";
reg = <0x404a8280 0x80>;
interrupts = <49 6>;
resolution = <16>;
status = "disabled";
};
counter1_6: counter@404a8300 {
compatible = "infineon,cat1-counter";
reg = <0x404a8300 0x80>;
interrupts = <50 6>;
resolution = <16>;
status = "disabled";
};
pwm0_0: pwm@404a0000 {
compatible = "infineon,cat1-pwm";
reg = <0x404a0000 0x80>;
interrupts = <42 6>;
resolution = <32>;
status = "disabled";
};
pwm0_1: pwm@404a0080 {
compatible = "infineon,cat1-pwm";
reg = <0x404a0080 0x80>;
interrupts = <43 6>;
resolution = <32>;
status = "disabled";
};
pwm1_0: pwm@404a8000 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8000 0x80>;
interrupts = <44 6>;
resolution = <16>;
status = "disabled";
};
pwm1_1: pwm@404a8080 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8080 0x80>;
interrupts = <45 6>;
resolution = <16>;
status = "disabled";
};
pwm1_2: pwm@404a8100 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8100 0x80>;
interrupts = <46 6>;
resolution = <16>;
status = "disabled";
};
pwm1_3: pwm@404a8180 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8180 0x80>;
interrupts = <47 6>;
resolution = <16>;
status = "disabled";
};
pwm1_4: pwm@404a8200 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8200 0x80>;
interrupts = <48 6>;
resolution = <16>;
status = "disabled";
};
pwm1_5: pwm@404a8280 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8280 0x80>;
interrupts = <49 6>;
resolution = <16>;
status = "disabled";
};
pwm1_6: pwm@404a8300 {
compatible = "infineon,cat1-pwm";
reg = <0x404a8300 0x80>;
interrupts = <50 6>;
resolution = <16>;
status = "disabled";
};
dma0: dw@40180000 {
#dma-cells = <1>;
compatible = "infineon,cat1-dma";
reg = <0x40180000 0x10000>;
dma-channels = <16>;
interrupts = <19 6>, /* CH0 */
<20 6>, /* CH1 */
<21 6>, /* CH2 */
<22 6>, /* CH3 */
<23 6>, /* CH4 */
<24 6>, /* CH5 */
<25 6>, /* CH6 */
<26 6>, /* CH7 */
<27 6>, /* CH8 */
<28 6>, /* CH9 */
<29 6>, /* CH10 */
<30 6>, /* CH11 */
<31 6>, /* CH12 */
<32 6>, /* CH13 */
<33 6>, /* CH14 */
<34 6>; /* CH15 */
status = "disabled";
};
};
};

105
dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi Normal file
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@ -0,0 +1,105 @@
/*
* Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "clock_source_def.h"
/ {
clocks {
/* iho */
clk_iho: clk_iho {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
status = "okay";
};
/* imo */
clk_imo: clk_imo {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <8000000>;
status = "okay";
};
/* fll */
fll0: fll0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
status = "okay";
};
/* path mux0 */
path_mux0: path_mux0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_iho>;
status = "disabled";
};
/* path mux1 */
path_mux1: path_mux1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_iho>;
status = "disabled";
};
/* path mux2 */
path_mux2: path_mux2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_iho>;
status = "disabled";
};
/* path mux3 */
path_mux3: path_mux3 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_imo>;
status = "disabled";
};
/* clk_hf0 */
clk_hf0: clk_hf0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&fll0>;
status = "disabled";
};
/* clk_hf1 */
clk_hf1: clk_hf1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&fll0>;
status = "disabled";
};
/* clk_hf2 */
clk_hf2: clk_hf2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux2>;
status = "disabled";
};
/* clk_hf3 */
clk_hf3: clk_hf3 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clocks = <&path_mux1>;
status = "disabled";
};
};
};

8
dts/arm/infineon/cat1b/mpns/CYW20829A0KML.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.40-qfn.dtsi"

8
dts/arm/infineon/cat1b/mpns/CYW20829A0LKML.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.56-qfn.dtsi"

8
dts/arm/infineon/cat1b/mpns/CYW20829B0KML.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.40-qfn.dtsi"

13
dts/arm/infineon/cat1b/mpns/CYW20829B0LKML.dtsi Normal file
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@ -0,0 +1,13 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include "../cyw20829/cyw20829.56-qfn.dtsi"
&nvic {
arm,num-irq-priority-bits = <3>;
};

8
dts/arm/infineon/cat1b/mpns/CYW89829A0KML.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.40-qfn.dtsi"

8
dts/arm/infineon/cat1b/mpns/CYW89829B01MKSBG.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.77-bga.dtsi"

8
dts/arm/infineon/cat1b/mpns/CYW89829B0KML.dtsi Normal file
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@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../cyw20829/cyw20829.40-qfn.dtsi"

9
modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
View file

@ -5,9 +5,11 @@
set(hal_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-hal-cat1)
set(hal_cat1a_dir ${hal_dir}/COMPONENT_CAT1A)
set(hal_cat1b_dir ${hal_dir}/COMPONENT_CAT1B)
# PSoC 6 family defines
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A COMPONENT_CAT1A)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B COMPONENT_CAT1B)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 COMPONENT_CAT1)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
@ -15,6 +17,7 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
zephyr_include_directories(${hal_dir}/include)
zephyr_include_directories(${hal_dir}/include_pvt)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${hal_cat1a_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${hal_cat1b_dir}/include)
# Packages sources
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
@ -54,6 +57,12 @@ zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_04_68_QFN
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_04_80_TQFP
${hal_cat1a_dir}/source/pin_packages/cyhal_psoc6_04_80_tqfp.c)
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_CYW20829_56_QFN
${hal_cat1b_dir}/source/pin_packages/cyhal_cyw20829_56_qfn.c)
zephyr_library_sources_ifdef(CONFIG_SOC_DIE_CYW20829
${hal_cat1b_dir}/source/triggers/cyhal_triggers_cyw20829.c)
zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_01
${hal_cat1a_dir}/source/triggers/cyhal_triggers_psoc6_01.c)
zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_02

17
modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
View file

@ -6,6 +6,7 @@
set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1)
set(pdl_drv_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/drivers)
set(pdl_dev_cat1a_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1A)
set(pdl_dev_cat1b_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1B)
# Generate PDL specific SOC defines
@ -17,10 +18,15 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_CYBLE_416045_02 CYBLE_416045_02_devi
# Add mtb-pdl-cat1
zephyr_include_directories(${pdl_drv_dir}/include)
zephyr_include_directories(${pdl_dev_cat1a_dir}/include)
zephyr_include_directories(${pdl_dev_cat1a_dir}/include/ip)
zephyr_library_sources(${pdl_dev_cat1a_dir}/source/cy_device.c)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1a_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1a_dir}/include/ip)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1a_dir}/source/cy_device.c)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/include/ip)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/source/cy_device.c)
zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S)
# Peripheral drivers
@ -61,6 +67,11 @@ zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_pipe.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_sema.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_prot.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysclk.c)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysclk_v2.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_systick_v2.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_btss.c)
endif()
zephyr_library_sources(${pdl_drv_dir}/source/cy_syslib.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_systick.c)

12
modules/hal_infineon/mtb-template-cat1/CMakeLists.txt
View file

@ -5,10 +5,22 @@
set(template_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-template-cat1)
set(cat1a_dir ${template_dir}/files/templates/cat1a)
set(cat1b_dir ${template_dir}/files/templates/cat1b)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
zephyr_include_directories(${cat1a_dir}/COMPONENT_MTB)
zephyr_include_directories(${cat1a_dir}/COMPONENT_MTB/COMPONENT_CM33/HEADER_FILES)
zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M4
${cat1a_dir}/COMPONENT_MTB/COMPONENT_CM4/system_psoc6_cm4.c)
zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS
${cat1a_dir}/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c)
endif()
# Add support cyw20829 (cat1b)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_include_directories(${cat1b_dir}/COMPONENT_MTB)
zephyr_include_directories(${cat1b_dir}/COMPONENT_MTB/COMPONENT_CM33/HEADER_FILES)
zephyr_library_sources(${cat1b_dir}/COMPONENT_MTB/COMPONENT_CM33/system_cyw20829.c)
endif()

5
soc/infineon/cat1b/CMakeLists.txt Normal file
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@ -0,0 +1,5 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(common)
add_subdirectory(${SOC_SERIES})

9
soc/infineon/cat1b/Kconfig Normal file
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@ -0,0 +1,9 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig"
endif # SOC_FAMILY_INFINEON_CAT1B

10
soc/infineon/cat1b/Kconfig.defconfig Normal file
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@ -0,0 +1,10 @@
# PSOC CAT1B Configuration
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_INFINEON_CAT1B

14
soc/infineon/cat1b/Kconfig.soc Normal file
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@ -0,0 +1,14 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Family definitions
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1B
bool
select SOC_FAMILY_INFINEON_CAT1
# MPNs definitions
rsource "*/Kconfig.soc"

4
soc/infineon/cat1b/common/CMakeLists.txt Normal file
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@ -0,0 +1,4 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)

133
soc/infineon/cat1b/common/pinctrl_soc.h Normal file
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@ -0,0 +1,133 @@
/*
* Copyright (c) 2016-2017 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/**
* Bit definition in PINMUX field
*/
#define SOC_PINMUX_PORT_POS (0)
#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
#define SOC_PINMUX_PIN_POS (8)
#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
#define SOC_PINMUX_HSIOM_FUNC_POS (16)
#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
#define SOC_PINMUX_SIGNAL_POS (24)
#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
/*
* Pin flags/attributes
*/
#define SOC_GPIO_DEFAULT (0)
#define SOC_GPIO_FLAGS_POS (0)
#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS)
#define SOC_GPIO_PULLUP_POS (0)
#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
#define SOC_GPIO_PULLDOWN_POS (1)
#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
#define SOC_GPIO_OPENDRAIN_POS (2)
#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
#define SOC_GPIO_OPENSOURCE_POS (3)
#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS)
/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_PUSHPULL_POS (4)
#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS)
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_INPUTENABLE_POS (5)
#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS)
#define SOC_GPIO_HIGHZ_POS (6)
#define SOC_GPIO_HIGHZ (1 << SOC_GPIO_HIGHZ_POS)
/** Type for CAT1 Soc pin. */
typedef struct {
/**
* Pinmux settings (port, pin and function).
* [0..7] - Port nunder
* [8..15] - Pin number
* [16..23]- HSIOM function
*/
uint32_t pinmux;
/** Pin configuration (bias, drive and slew rate). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
#define CAT1_PINMUX_GET_PORT_NUM(pinmux) \
(((pinmux) & SOC_PINMUX_PORT_MASK) >> SOC_PINMUX_PORT_POS)
#define CAT1_PINMUX_GET_PIN_NUM(pinmux) \
(((pinmux) & SOC_PINMUX_PIN_MASK) >> SOC_PINMUX_PIN_POS)
#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) \
(((pinmux) & SOC_PINMUX_HSIOM_MASK) >> SOC_PINMUX_HSIOM_FUNC_POS)
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) ( \
(DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \
(DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \
(DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \
(DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \
(DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \
(DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \
(DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS))
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param state_prop State property name.
* @param idx State property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
{ .pinmux = Z_PINCTRL_CAT1_PINMUX_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)) },
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */

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# Copyright (c) 2023 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_sources(app_header.c)
zephyr_include_directories(.)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B COMPONENT_CAT1B)
zephyr_compile_definitions(COMPONENT_CM33)
# Use custom linker script
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/linker.ld CACHE INTERNAL "")

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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CAT1B devices
# Series definitions
config SOC_SERIES_CYW20829
select ARM
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M33
select CPU_HAS_FPU
select DYNAMIC_INTERRUPTS

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# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CYW20829 based MCU default configuration
if SOC_DIE_CYW20829
config NUM_IRQS
default 70
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 48000000
# add additional die specific params
endif # SOC_DIE_CYW20829

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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CYW20829 series MCUs
# SOC series
config SOC_SERIES_CYW20829
bool
config SOC_SERIES
default "cyw20829" if SOC_SERIES_CYW20829
# SOC die
config SOC_DIE_CYW20829
bool
select SOC_FAMILY_INFINEON_CAT1B
# SOC packages
config SOC_PACKAGE_CYW20829_56_QFN
bool
config SOC_PACKAGE_CYW20829_40_QFN
bool
config SOC_PACKAGE_CYW20829_77_BGA
bool
# MPN
config SOC_CYW20829A0LKML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_56_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829A0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829A0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829B0LKML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_56_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829B0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829B0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829B01MKSBG
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_77_BGA
select SOC_SERIES_CYW20829
config SOC
default "cyw20829a0lkml" if SOC_CYW20829A0LKML
default "cyw20829a0kml" if SOC_CYW20829A0KML
default "cyw89829a0kml" if SOC_CYW89829A0KML
default "cyw20829b0lkml" if SOC_CYW20829B0LKML
default "cyw20829b0kml" if SOC_CYW20829B0KML
default "cyw89829b0kml" if SOC_CYW89829B0KML
default "cyw89829b01mksbg" if SOC_CYW89829B01MKSBG

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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <stdint.h>
struct toc2_data {
uint32_t toc2_size;
uint32_t l1_app_descr_addr;
uint32_t service_app_descr_addr;
uint32_t debug_cert_addr;
} __packed;
struct l1_desc {
uint32_t l1_app_descr_size;
uint32_t boot_strap_addr;
uint32_t boot_strap_dst_addr;
uint32_t boot_strap_size;
uint32_t reserved[3];
} __packed;
struct l1_usr_app_hdr {
uint8_t reserved[32];
} __packed;
struct app_header {
struct toc2_data toc2_data;
struct l1_desc l1_desc;
uint8_t padding[4];
struct l1_usr_app_hdr l1_usr_app_hdr;
} __packed;
const struct app_header app_header Z_GENERIC_SECTION(.app_header) = {
.toc2_data = {.toc2_size = sizeof(struct toc2_data),
.l1_app_descr_addr = offsetof(struct app_header, l1_desc)},
.l1_desc = {.l1_app_descr_size = sizeof(struct l1_desc),
.boot_strap_addr = DT_REG_ADDR(DT_NODELABEL(bootstrap_region)) -
DT_REG_ADDR(DT_NODELABEL(flash0)),
.boot_strap_dst_addr = DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)),
.boot_strap_size = DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))},
};

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/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTIONS
{
.app_header :
{
KEEP(*(.app_header))
} > APP_HEADER_FLASH
/* Cortex-M33 bootstrap code area */
.bootstrapText :
{
. = ALIGN(4);
__bootstrapText_begin = .;
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_START ...). This typically contains the vector
* table and debug information.
*/
#include <snippets-rom-start.ld>
/* startup code */
*(.text._reset_section)
*startup_cat1b_cm33.*(.text*)
*system_cyw20829.*(.text*)
/* drivers */
*cy_device.*(.text*)
*cy_btss.*(.text*)
*cy_sysclk_v2.*(.text*)
*cy_syspm_v2.*(.text*)
*cy_sysint_v2.*(.text*)
*cy_syslib*.*(.text*)
*ppu_v1.*(.text*)
*cy_mpc.*(.text*)
*cy_syspm_ppu.*(.text*)
*memcpy*.* (.text*) /* add memcpy from the NewLib library here*/
*memset*.* (.text*) /* add memcpy from the NewLib library here*/
*memmove*.* (.text*) /* add memcpy from the NewLib library here*/
*s_fabs.* (.text*)
KEEP(*(.cy_l1func*))
. = ALIGN(4);
__bootstrapText_end = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapzero.table :
{
. = ALIGN(4);
__bootstrapzero_table_start__ = .;
LONG (__bootstrap_bss_start__)
LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
. = ALIGN(4);
__bootstrapzero_table_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapData :
{
__bootstrapData_start__ = .;
. = ALIGN(4);
/* startup code */
*startup_cat1b_cm33.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*system_cyw20829.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
/* drivers */
*cy_device.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_btss.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysclk_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_syspm_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysint_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_syslib.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*ppu_v1.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_mpc.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_pd_ppu.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.cy_l1data*))
. = ALIGN(4);
__bootstrapData_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapBss (NOLOAD):
{
. = ALIGN(4);
__bootstrap_bss_start__ = .;
/* startup code */
*startup_cat1b_cm33.*(.bss* COMMON)
*system_cyw20829.*(.bss* COMMON)
/* drivers */
*cy_device.*(.bss* COMMON)
*cy_btss.*(.bss* COMMON)
*cy_sysclk_v2.*(.bss* COMMON)
*cy_syspm_v2.*(.bss* COMMON)
*cy_sysint_v2.*(.bss* COMMON)
*cy_syslib.*(.bss* COMMON)
*ppu_v1.*(.bss* COMMON)
*cy_mpc.*(.bss* COMMON)
*cy_pd_ppu.*(.bss* COMMON)
KEEP(*(.cy_l1bss*))
. = ALIGN(4);
__bootstrap_bss_end__ = .;
} > BOOTSTRAP_RAM
}

486
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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Cortex-M platforms.
*/
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
/* physical address of RAM */
#ifdef CONFIG_XIP
#define ROMABLE_REGION FLASH
#else
#define ROMABLE_REGION RAM
#endif
#define RAMABLE_REGION RAM
#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
#define ROM_ADDR RAM_ADDR
#else
#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif
#if defined(CONFIG_ROM_END_OFFSET)
#define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
#else
#define ROM_END_OFFSET 0
#endif
#if CONFIG_FLASH_LOAD_SIZE > 0
#define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)
#else
#define ROM_SIZE (CONFIG_FLASH_SIZE * 1024 - CONFIG_FLASH_LOAD_OFFSET - ROM_END_OFFSET)
#endif
#if defined(CONFIG_XIP)
#if defined(CONFIG_IS_BOOTLOADER)
#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
#else
#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif
#else
#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif
#if defined(CONFIG_CUSTOM_SECTION_ALIGN)
_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;
#else
/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
* to make linker section alignment comply with MPU granularity.
*/
#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#else
/* If building without MPU support, use default 4-byte alignment. */
_region_min_align = 4;
#endif
#endif
#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align); \
. = ALIGN( 1 << LOG2CEIL(region_size))
#else
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align)
#endif
#include <zephyr/linker/linker-devnull.h>
MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
#endif
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
}
ENTRY(CONFIG_KERNEL_ENTRY)
#include <bootstrap.ld>
SECTIONS
{
#include <zephyr/linker/rel-sections.ld>
/*
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
* before text section.
*/
/DISCARD/ :
{
*(.plt)
}
/DISCARD/ :
{
*(.iplt)
}
GROUP_START(ROMABLE_REGION)
__rom_region_start = ROM_ADDR;
SECTION_PROLOGUE(rom_start,,)
{
} GROUP_LINK_IN(ROMABLE_REGION)
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_relocate.ld>
#endif /* CONFIG_CODE_DATA_RELOCATION */
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
__text_region_start = .;
#include <zephyr/linker/kobject-text.ld>
*(.text)
*(".text.*")
*(".TEXT.*")
*(.gnu.linkonce.t.*)
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* after .gnu.linkonce.t.*
*/
*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
__text_region_end = .;
#if defined (CONFIG_CPP)
SECTION_PROLOGUE(.ARM.extab,,)
{
/*
* .ARM.extab section containing exception unwinding information.
*/
*(.ARM.extab* .gnu.linkonce.armextab.*)
} GROUP_LINK_IN(ROMABLE_REGION)
#endif
SECTION_PROLOGUE(.ARM.exidx,,)
{
/*
* This section, related to stack and exception unwinding, is placed
* explicitly to prevent it from being shared between multiple regions.
* It must be defined for gcc to support 64-bit math and avoid
* section overlap.
*/
__exidx_start = .;
#if defined (__GCC_LINKER_CMD__)
*(.ARM.exidx* gnu.linkonce.armexidx.*)
#endif
__exidx_end = .;
} GROUP_LINK_IN(ROMABLE_REGION)
__rodata_region_start = .;
#include <zephyr/linker/common-rom.ld>
#include <zephyr/linker/thread-local-storage.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rodata.ld>
#include <zephyr/linker/kobject-rom.ld>
/*
* For XIP images, in order to avoid the situation when __data_rom_start
* is 32-bit aligned, but the actual data is placed right after rodata
* section, which may not end exactly at 32-bit border, pad rodata
* section, so __data_rom_start points at data and it is 32-bit aligned.
*
* On non-XIP images this may enlarge image size up to 3 bytes. This
* generally is not an issue, since modern ROM and FLASH memory is
* usually 4k aligned.
*/
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
#include <zephyr/linker/cplusplus-rom.ld>
#if defined(CONFIG_BUILD_ALIGN_LMA)
/*
* Include a padding section here to make sure that the LMA address
* of the sections in the RAMABLE_REGION are aligned with those
* section's VMA alignment requirements.
*/
SECTION_PROLOGUE(padding_section,,)
{
__rodata_region_end = .;
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
} GROUP_LINK_IN(ROMABLE_REGION)
#else
__rodata_region_end = .;
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
#endif
__rom_region_end = __rom_region_start + . - ADDR(rom_start);
GROUP_END(ROMABLE_REGION)
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* before data section.
*/
/DISCARD/ : {
*(.got.plt)
*(.igot.plt)
*(.got)
*(.igot)
}
GROUP_START(RAMABLE_REGION)
. = RAM_ADDR;
/* Align the start of image RAM with the
* minimum granularity required by MPU.
*/
. = ALIGN(_region_min_align);
_image_ram_start = .;
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-ram-sections.ld>
#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
#define SMEM_PARTITION_ALIGN MPU_ALIGN
#include <app_smem.ld>
_app_smem_size = _app_smem_end - _app_smem_start;
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
*(.bss)
*(".bss.*")
*(COMMON)
*(".kernel_bss.*")
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#include <zephyr/linker/common-noinit.ld>
#endif /* CONFIG_USERSPACE */
GROUP_START(DATA_REGION)
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
__data_region_start = .;
__data_start = .;
*(.data)
*(".data.*")
*(".kernel.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rwdata.ld>
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_data_relocate.ld>
#endif
__data_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__data_size = __data_end - __data_start;
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
#include <zephyr/linker/common-ram.ld>
#include <zephyr/linker/kobject-data.ld>
#include <zephyr/linker/cplusplus-ram.ld>
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-data-sections.ld>
__data_region_end = .;
#ifndef CONFIG_USERSPACE
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
*(.bss)
*(".bss.*")
*(COMMON)
*(".kernel_bss.*")
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
*(".kernel_noinit.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-noinit.ld>
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#endif /* CONFIG_USERSPACE */
/* Define linker symbols */
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
GROUP_START(ITCM)
SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))
{
__itcm_start = .;
*(.itcm)
*(".itcm.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function. */
#include <snippets-itcm-section.ld>
__itcm_end = .;
} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
__itcm_size = __itcm_end - __itcm_start;
__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);
GROUP_END(ITCM)
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
GROUP_START(DTCM)
SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__dtcm_start = .;
__dtcm_bss_start = .;
*(.dtcm_bss)
*(".dtcm_bss.*")
__dtcm_bss_end = .;
} GROUP_LINK_IN(DTCM)
SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__dtcm_noinit_start = .;
*(.dtcm_noinit)
*(".dtcm_noinit.*")
__dtcm_noinit_end = .;
} GROUP_LINK_IN(DTCM)
SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))
{
__dtcm_data_start = .;
*(.dtcm_data)
*(".dtcm_data.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function. */
#include <snippets-dtcm-section.ld>
__dtcm_data_end = .;
} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
__dtcm_end = .;
__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
GROUP_END(DTCM)
#endif
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-sections.ld>
#include <zephyr/linker/ram-end.ld>
GROUP_END(RAMABLE_REGION)
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
SECTION_PROLOGUE(.ARM.attributes, 0,)
{
KEEP(*(.ARM.attributes))
KEEP(*(.gnu.attributes))
}
/* Sections generated from 'zephyr,memory-region' nodes */
LINKER_DT_SECTIONS()
/* Must be last in romable region */
SECTION_PROLOGUE(.last_section,,)
{
#ifdef CONFIG_LINKER_LAST_SECTION_ID
/* Fill last section with a word to ensure location counter and actual rom
* region data usage match. */
LONG(CONFIG_LINKER_LAST_SECTION_ID_PATTERN)
#endif
} GROUP_LINK_IN(ROMABLE_REGION)
/* To provide the image size as a const expression,
* calculate this value here. */
_flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
}

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soc/infineon/cat1b/cyw20829/soc.c Normal file
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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon CYW920829 soc.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
#include <system_cat1b.h>
#include "cy_pdl.h"
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
{
CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
/* The interrupt vector will be relocated only if the vector table was
* moved to SRAM (CONFIG_DYNAMIC_INTERRUPTS and CONFIG_GEN_ISR_TABLES
* must be enabled). Otherwise it is ignored.
*/
#if defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES)
if (config != NULL) {
uint32_t priority;
/* NOTE:
* PendSV IRQ (which is used in Cortex-M variants to implement thread
* context-switching) is assigned the lowest IRQ priority level.
* If priority is same as PendSV, we will catch assertion in
* z_arm_irq_priority_set function. To avoid this, change priority
* to IRQ_PRIO_LOWEST, if it > IRQ_PRIO_LOWEST. Macro IRQ_PRIO_LOWEST
* takes in to account PendSV specific.
*/
priority = (config->intrPriority > IRQ_PRIO_LOWEST) ?
IRQ_PRIO_LOWEST : config->intrPriority;
/* Configure a dynamic interrupt */
(void) irq_connect_dynamic(config->intrSrc, priority,
(void *) userIsr, NULL, 0);
} else {
status = CY_SYSINT_BAD_PARAM;
}
#endif /* defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) */
return(status);
}
static int init_cycfg_platform_wrapper(void)
{
/* Initializes the system */
SystemInit();
return 0;
}
SYS_INIT(init_cycfg_platform_wrapper, PRE_KERNEL_1, 0);

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soc/infineon/cat1b/cyw20829/soc.h Normal file
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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon CYW20829 soc.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

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soc/infineon/cat1b/soc.yml Normal file
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family:
- name: cat1b
series:
- name: cyw20829
socs:
- name: cyw20829a0lkml
- name: cyw20829a0kml
- name: cyw89829a0kml
- name: cyw20829b0lkml
- name: cyw20829b0kml
- name: cyw89829b0kml
- name: cyw89829b01mksbg