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boards: arm: Introduce Infineon CYW920829M2EVK-02 board

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- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
  clocks instead of just one or the other

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This commit is contained in:
Sreeram Tatapudi 2024-05-09 14:07:58 -07:00 • committed by Anas Nashif
commit f96e6ccbc0
46 changed files with 2952 additions and 12 deletions
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soc/infineon/cat1b/CMakeLists.txt Normal file
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# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(common)
add_subdirectory(${SOC_SERIES})

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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig"
endif # SOC_FAMILY_INFINEON_CAT1B

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# PSOC CAT1B Configuration
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_INFINEON_CAT1B

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soc/infineon/cat1b/Kconfig.soc Normal file
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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Family definitions
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1B
bool
select SOC_FAMILY_INFINEON_CAT1
# MPNs definitions
rsource "*/Kconfig.soc"

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# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)

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/*
* Copyright (c) 2016-2017 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/**
* Bit definition in PINMUX field
*/
#define SOC_PINMUX_PORT_POS (0)
#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
#define SOC_PINMUX_PIN_POS (8)
#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
#define SOC_PINMUX_HSIOM_FUNC_POS (16)
#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
#define SOC_PINMUX_SIGNAL_POS (24)
#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
/*
* Pin flags/attributes
*/
#define SOC_GPIO_DEFAULT (0)
#define SOC_GPIO_FLAGS_POS (0)
#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS)
#define SOC_GPIO_PULLUP_POS (0)
#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
#define SOC_GPIO_PULLDOWN_POS (1)
#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
#define SOC_GPIO_OPENDRAIN_POS (2)
#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
#define SOC_GPIO_OPENSOURCE_POS (3)
#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS)
/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_PUSHPULL_POS (4)
#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS)
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_INPUTENABLE_POS (5)
#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS)
#define SOC_GPIO_HIGHZ_POS (6)
#define SOC_GPIO_HIGHZ (1 << SOC_GPIO_HIGHZ_POS)
/** Type for CAT1 Soc pin. */
typedef struct {
/**
* Pinmux settings (port, pin and function).
* [0..7] - Port nunder
* [8..15] - Pin number
* [16..23]- HSIOM function
*/
uint32_t pinmux;
/** Pin configuration (bias, drive and slew rate). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
#define CAT1_PINMUX_GET_PORT_NUM(pinmux) \
(((pinmux) & SOC_PINMUX_PORT_MASK) >> SOC_PINMUX_PORT_POS)
#define CAT1_PINMUX_GET_PIN_NUM(pinmux) \
(((pinmux) & SOC_PINMUX_PIN_MASK) >> SOC_PINMUX_PIN_POS)
#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) \
(((pinmux) & SOC_PINMUX_HSIOM_MASK) >> SOC_PINMUX_HSIOM_FUNC_POS)
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) ( \
(DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \
(DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \
(DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \
(DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \
(DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \
(DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \
(DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS))
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param state_prop State property name.
* @param idx State property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
{ .pinmux = Z_PINCTRL_CAT1_PINMUX_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.pincfg = Z_PINCTRL_CAT1_PINCFG_INIT( \
DT_PROP_BY_IDX(node_id, state_prop, idx)) },
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */

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# Copyright (c) 2023 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_sources(app_header.c)
zephyr_include_directories(.)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B COMPONENT_CAT1B)
zephyr_compile_definitions(COMPONENT_CM33)
# Use custom linker script
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/linker.ld CACHE INTERNAL "")

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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CAT1B devices
# Series definitions
config SOC_SERIES_CYW20829
select ARM
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M33
select CPU_HAS_FPU
select DYNAMIC_INTERRUPTS

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# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CYW20829 based MCU default configuration
if SOC_DIE_CYW20829
config NUM_IRQS
default 70
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 48000000
# add additional die specific params
endif # SOC_DIE_CYW20829

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# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CYW20829 series MCUs
# SOC series
config SOC_SERIES_CYW20829
bool
config SOC_SERIES
default "cyw20829" if SOC_SERIES_CYW20829
# SOC die
config SOC_DIE_CYW20829
bool
select SOC_FAMILY_INFINEON_CAT1B
# SOC packages
config SOC_PACKAGE_CYW20829_56_QFN
bool
config SOC_PACKAGE_CYW20829_40_QFN
bool
config SOC_PACKAGE_CYW20829_77_BGA
bool
# MPN
config SOC_CYW20829A0LKML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_56_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829A0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829A0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829B0LKML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_56_QFN
select SOC_SERIES_CYW20829
config SOC_CYW20829B0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829B0KML
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_40_QFN
select SOC_SERIES_CYW20829
config SOC_CYW89829B01MKSBG
bool
select SOC_DIE_CYW20829
select SOC_PACKAGE_CYW20829_77_BGA
select SOC_SERIES_CYW20829
config SOC
default "cyw20829a0lkml" if SOC_CYW20829A0LKML
default "cyw20829a0kml" if SOC_CYW20829A0KML
default "cyw89829a0kml" if SOC_CYW89829A0KML
default "cyw20829b0lkml" if SOC_CYW20829B0LKML
default "cyw20829b0kml" if SOC_CYW20829B0KML
default "cyw89829b0kml" if SOC_CYW89829B0KML
default "cyw89829b01mksbg" if SOC_CYW89829B01MKSBG

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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <stdint.h>
struct toc2_data {
uint32_t toc2_size;
uint32_t l1_app_descr_addr;
uint32_t service_app_descr_addr;
uint32_t debug_cert_addr;
} __packed;
struct l1_desc {
uint32_t l1_app_descr_size;
uint32_t boot_strap_addr;
uint32_t boot_strap_dst_addr;
uint32_t boot_strap_size;
uint32_t reserved[3];
} __packed;
struct l1_usr_app_hdr {
uint8_t reserved[32];
} __packed;
struct app_header {
struct toc2_data toc2_data;
struct l1_desc l1_desc;
uint8_t padding[4];
struct l1_usr_app_hdr l1_usr_app_hdr;
} __packed;
const struct app_header app_header Z_GENERIC_SECTION(.app_header) = {
.toc2_data = {.toc2_size = sizeof(struct toc2_data),
.l1_app_descr_addr = offsetof(struct app_header, l1_desc)},
.l1_desc = {.l1_app_descr_size = sizeof(struct l1_desc),
.boot_strap_addr = DT_REG_ADDR(DT_NODELABEL(bootstrap_region)) -
DT_REG_ADDR(DT_NODELABEL(flash0)),
.boot_strap_dst_addr = DT_REG_ADDR(DT_NODELABEL(sram_bootstrap)),
.boot_strap_size = DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))},
};

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/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTIONS
{
.app_header :
{
KEEP(*(.app_header))
} > APP_HEADER_FLASH
/* Cortex-M33 bootstrap code area */
.bootstrapText :
{
. = ALIGN(4);
__bootstrapText_begin = .;
/* Located in generated directory. This file is populated by calling
* zephyr_linker_sources(ROM_START ...). This typically contains the vector
* table and debug information.
*/
#include <snippets-rom-start.ld>
/* startup code */
*(.text._reset_section)
*startup_cat1b_cm33.*(.text*)
*system_cyw20829.*(.text*)
/* drivers */
*cy_device.*(.text*)
*cy_btss.*(.text*)
*cy_sysclk_v2.*(.text*)
*cy_syspm_v2.*(.text*)
*cy_sysint_v2.*(.text*)
*cy_syslib*.*(.text*)
*ppu_v1.*(.text*)
*cy_mpc.*(.text*)
*cy_syspm_ppu.*(.text*)
*memcpy*.* (.text*) /* add memcpy from the NewLib library here*/
*memset*.* (.text*) /* add memcpy from the NewLib library here*/
*memmove*.* (.text*) /* add memcpy from the NewLib library here*/
*s_fabs.* (.text*)
KEEP(*(.cy_l1func*))
. = ALIGN(4);
__bootstrapText_end = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapzero.table :
{
. = ALIGN(4);
__bootstrapzero_table_start__ = .;
LONG (__bootstrap_bss_start__)
LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
. = ALIGN(4);
__bootstrapzero_table_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapData :
{
__bootstrapData_start__ = .;
. = ALIGN(4);
/* startup code */
*startup_cat1b_cm33.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*system_cyw20829.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
/* drivers */
*cy_device.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_btss.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysclk_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_syspm_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysint_v2.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_syslib.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*ppu_v1.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_mpc.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_pd_ppu.*(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.cy_l1data*))
. = ALIGN(4);
__bootstrapData_end__ = .;
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
.bootstrapBss (NOLOAD):
{
. = ALIGN(4);
__bootstrap_bss_start__ = .;
/* startup code */
*startup_cat1b_cm33.*(.bss* COMMON)
*system_cyw20829.*(.bss* COMMON)
/* drivers */
*cy_device.*(.bss* COMMON)
*cy_btss.*(.bss* COMMON)
*cy_sysclk_v2.*(.bss* COMMON)
*cy_syspm_v2.*(.bss* COMMON)
*cy_sysint_v2.*(.bss* COMMON)
*cy_syslib.*(.bss* COMMON)
*ppu_v1.*(.bss* COMMON)
*cy_mpc.*(.bss* COMMON)
*cy_pd_ppu.*(.bss* COMMON)
KEEP(*(.cy_l1bss*))
. = ALIGN(4);
__bootstrap_bss_end__ = .;
} > BOOTSTRAP_RAM
}

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/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Cortex-M platforms.
*/
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
/* physical address of RAM */
#ifdef CONFIG_XIP
#define ROMABLE_REGION FLASH
#else
#define ROMABLE_REGION RAM
#endif
#define RAMABLE_REGION RAM
#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
#define ROM_ADDR RAM_ADDR
#else
#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif
#if defined(CONFIG_ROM_END_OFFSET)
#define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
#else
#define ROM_END_OFFSET 0
#endif
#if CONFIG_FLASH_LOAD_SIZE > 0
#define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)
#else
#define ROM_SIZE (CONFIG_FLASH_SIZE * 1024 - CONFIG_FLASH_LOAD_OFFSET - ROM_END_OFFSET)
#endif
#if defined(CONFIG_XIP)
#if defined(CONFIG_IS_BOOTLOADER)
#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
#else
#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif
#else
#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif
#if defined(CONFIG_CUSTOM_SECTION_ALIGN)
_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;
#else
/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
* to make linker section alignment comply with MPU granularity.
*/
#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#else
/* If building without MPU support, use default 4-byte alignment. */
_region_min_align = 4;
#endif
#endif
#if !defined(CONFIG_CUSTOM_SECTION_ALIGN) && defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align); \
. = ALIGN( 1 << LOG2CEIL(region_size))
#else
#define MPU_ALIGN(region_size) \
. = ALIGN(_region_min_align)
#endif
#include <zephyr/linker/linker-devnull.h>
MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
#endif
LINKER_DT_REGIONS()
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFF7FFF, LENGTH = 32K
}
ENTRY(CONFIG_KERNEL_ENTRY)
#include <bootstrap.ld>
SECTIONS
{
#include <zephyr/linker/rel-sections.ld>
/*
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
* before text section.
*/
/DISCARD/ :
{
*(.plt)
}
/DISCARD/ :
{
*(.iplt)
}
GROUP_START(ROMABLE_REGION)
__rom_region_start = ROM_ADDR;
SECTION_PROLOGUE(rom_start,,)
{
} GROUP_LINK_IN(ROMABLE_REGION)
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_relocate.ld>
#endif /* CONFIG_CODE_DATA_RELOCATION */
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
__text_region_start = .;
#include <zephyr/linker/kobject-text.ld>
*(.text)
*(".text.*")
*(".TEXT.*")
*(.gnu.linkonce.t.*)
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* after .gnu.linkonce.t.*
*/
*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
__text_region_end = .;
#if defined (CONFIG_CPP)
SECTION_PROLOGUE(.ARM.extab,,)
{
/*
* .ARM.extab section containing exception unwinding information.
*/
*(.ARM.extab* .gnu.linkonce.armextab.*)
} GROUP_LINK_IN(ROMABLE_REGION)
#endif
SECTION_PROLOGUE(.ARM.exidx,,)
{
/*
* This section, related to stack and exception unwinding, is placed
* explicitly to prevent it from being shared between multiple regions.
* It must be defined for gcc to support 64-bit math and avoid
* section overlap.
*/
__exidx_start = .;
#if defined (__GCC_LINKER_CMD__)
*(.ARM.exidx* gnu.linkonce.armexidx.*)
#endif
__exidx_end = .;
} GROUP_LINK_IN(ROMABLE_REGION)
__rodata_region_start = .;
#include <zephyr/linker/common-rom.ld>
#include <zephyr/linker/thread-local-storage.ld>
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rodata.ld>
#include <zephyr/linker/kobject-rom.ld>
/*
* For XIP images, in order to avoid the situation when __data_rom_start
* is 32-bit aligned, but the actual data is placed right after rodata
* section, which may not end exactly at 32-bit border, pad rodata
* section, so __data_rom_start points at data and it is 32-bit aligned.
*
* On non-XIP images this may enlarge image size up to 3 bytes. This
* generally is not an issue, since modern ROM and FLASH memory is
* usually 4k aligned.
*/
. = ALIGN(4);
} GROUP_LINK_IN(ROMABLE_REGION)
#include <zephyr/linker/cplusplus-rom.ld>
#if defined(CONFIG_BUILD_ALIGN_LMA)
/*
* Include a padding section here to make sure that the LMA address
* of the sections in the RAMABLE_REGION are aligned with those
* section's VMA alignment requirements.
*/
SECTION_PROLOGUE(padding_section,,)
{
__rodata_region_end = .;
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
} GROUP_LINK_IN(ROMABLE_REGION)
#else
__rodata_region_end = .;
MPU_ALIGN(__rodata_region_end - ADDR(rom_start));
#endif
__rom_region_end = __rom_region_start + . - ADDR(rom_start);
GROUP_END(ROMABLE_REGION)
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* before data section.
*/
/DISCARD/ : {
*(.got.plt)
*(.igot.plt)
*(.got)
*(.igot)
}
GROUP_START(RAMABLE_REGION)
. = RAM_ADDR;
/* Align the start of image RAM with the
* minimum granularity required by MPU.
*/
. = ALIGN(_region_min_align);
_image_ram_start = .;
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-ram-sections.ld>
#if defined(CONFIG_USERSPACE)
#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
#define SMEM_PARTITION_ALIGN MPU_ALIGN
#include <app_smem.ld>
_app_smem_size = _app_smem_end - _app_smem_start;
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
*(.bss)
*(".bss.*")
*(COMMON)
*(".kernel_bss.*")
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#include <zephyr/linker/common-noinit.ld>
#endif /* CONFIG_USERSPACE */
GROUP_START(DATA_REGION)
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
{
__data_region_start = .;
__data_start = .;
*(.data)
*(".data.*")
*(".kernel.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-rwdata.ld>
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_data_relocate.ld>
#endif
__data_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
__data_size = __data_end - __data_start;
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
#include <zephyr/linker/common-ram.ld>
#include <zephyr/linker/kobject-data.ld>
#include <zephyr/linker/cplusplus-ram.ld>
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-data-sections.ld>
__data_region_end = .;
#ifndef CONFIG_USERSPACE
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
__kernel_ram_start = .;
*(.bss)
*(".bss.*")
*(COMMON)
*(".kernel_bss.*")
#ifdef CONFIG_CODE_DATA_RELOCATION
#include <linker_sram_bss_relocate.ld>
#endif
/*
* As memory is cleared in words only, it is simpler to ensure the BSS
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
*/
__bss_end = ALIGN(4);
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-initialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
*(".kernel_noinit.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-noinit.ld>
} GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#endif /* CONFIG_USERSPACE */
/* Define linker symbols */
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
GROUP_START(ITCM)
SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(4))
{
__itcm_start = .;
*(.itcm)
*(".itcm.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function. */
#include <snippets-itcm-section.ld>
__itcm_end = .;
} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
__itcm_size = __itcm_end - __itcm_start;
__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);
GROUP_END(ITCM)
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
GROUP_START(DTCM)
SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__dtcm_start = .;
__dtcm_bss_start = .;
*(.dtcm_bss)
*(".dtcm_bss.*")
__dtcm_bss_end = .;
} GROUP_LINK_IN(DTCM)
SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__dtcm_noinit_start = .;
*(.dtcm_noinit)
*(".dtcm_noinit.*")
__dtcm_noinit_end = .;
} GROUP_LINK_IN(DTCM)
SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))
{
__dtcm_data_start = .;
*(.dtcm_data)
*(".dtcm_data.*")
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function. */
#include <snippets-dtcm-section.ld>
__dtcm_data_end = .;
} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
__dtcm_end = .;
__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
GROUP_END(DTCM)
#endif
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/
#include <snippets-sections.ld>
#include <zephyr/linker/ram-end.ld>
GROUP_END(RAMABLE_REGION)
#include <zephyr/linker/debug-sections.ld>
/DISCARD/ : { *(.note.GNU-stack) }
SECTION_PROLOGUE(.ARM.attributes, 0,)
{
KEEP(*(.ARM.attributes))
KEEP(*(.gnu.attributes))
}
/* Sections generated from 'zephyr,memory-region' nodes */
LINKER_DT_SECTIONS()
/* Must be last in romable region */
SECTION_PROLOGUE(.last_section,,)
{
#ifdef CONFIG_LINKER_LAST_SECTION_ID
/* Fill last section with a word to ensure location counter and actual rom
* region data usage match. */
LONG(CONFIG_LINKER_LAST_SECTION_ID_PATTERN)
#endif
} GROUP_LINK_IN(ROMABLE_REGION)
/* To provide the image size as a const expression,
* calculate this value here. */
_flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
}

61
soc/infineon/cat1b/cyw20829/soc.c Normal file
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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon CYW920829 soc.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
#include <system_cat1b.h>
#include "cy_pdl.h"
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
{
CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
/* The interrupt vector will be relocated only if the vector table was
* moved to SRAM (CONFIG_DYNAMIC_INTERRUPTS and CONFIG_GEN_ISR_TABLES
* must be enabled). Otherwise it is ignored.
*/
#if defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES)
if (config != NULL) {
uint32_t priority;
/* NOTE:
* PendSV IRQ (which is used in Cortex-M variants to implement thread
* context-switching) is assigned the lowest IRQ priority level.
* If priority is same as PendSV, we will catch assertion in
* z_arm_irq_priority_set function. To avoid this, change priority
* to IRQ_PRIO_LOWEST, if it > IRQ_PRIO_LOWEST. Macro IRQ_PRIO_LOWEST
* takes in to account PendSV specific.
*/
priority = (config->intrPriority > IRQ_PRIO_LOWEST) ?
IRQ_PRIO_LOWEST : config->intrPriority;
/* Configure a dynamic interrupt */
(void) irq_connect_dynamic(config->intrSrc, priority,
(void *) userIsr, NULL, 0);
} else {
status = CY_SYSINT_BAD_PARAM;
}
#endif /* defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) */
return(status);
}
static int init_cycfg_platform_wrapper(void)
{
/* Initializes the system */
SystemInit();
return 0;
}
SYS_INIT(init_cycfg_platform_wrapper, PRE_KERNEL_1, 0);

18
soc/infineon/cat1b/cyw20829/soc.h Normal file
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/* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon CYW20829 soc.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

12
soc/infineon/cat1b/soc.yml Normal file
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family:
- name: cat1b
series:
- name: cyw20829
socs:
- name: cyw20829a0lkml
- name: cyw20829a0kml
- name: cyw89829a0kml
- name: cyw20829b0lkml
- name: cyw20829b0kml
- name: cyw89829b0kml
- name: cyw89829b01mksbg