board: imx8mm_evk: enable ENET ethernet on Cortex-A Core

Enabled ENET ethernet port on Cortex-A Core for imx8mm EVK board.
Updated suported featues in board document.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>

boards/nxp/imx8mm_evk/Kconfig.defconfig

@@ -0,0 +1,44 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_IMX8MM_EVK
+
+if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config NET_TX_STACK_SIZE
+	default 8192
+
+config NET_RX_STACK_SIZE
+	default 8192
+
+if NET_TCP
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 8192
+
+endif # NET_TCP
+
+if NET_MGMT_EVENT
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 8192
+
+endif # NET_MGMT_EVENT
+
+if NET_SOCKETS_SERVICE
+
+config NET_SOCKETS_SERVICE_STACK_SIZE
+	default 8192
+
+endif # NET_SOCKETS_SERVICE
+
+endif # NETWORKING
+
+endif # BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP
+
+endif # BOARD_IMX8MM_EVK

boards/nxp/imx8mm_evk/doc/index.rst

@@ -55,8 +55,18 @@ features:
 +-----------+------------+-------------------------------------+
 | ARM TIMER | on-chip    | system clock                        |
 +-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | clock_control                       |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| RDC       | on-chip    | Resource Domain Controller          |
++-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial port                         |
 +-----------+------------+-------------------------------------+
+| GPT       | on-chip    | timer                               |
++-----------+------------+-------------------------------------+
+| ENET      | on-chip    | ethernet port                       |
++-----------+------------+-------------------------------------+
 
 The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware
 features:

boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi

@@ -25,4 +25,42 @@
 		};
 	};
 
+	pinmux_enet: pinmux_enet {
+		group0 {
+			pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
+				<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
+				<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
+				<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
+				<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
+				<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
+			slew-rate = "fast";
+			drive-strength = "x6";
+		};
+
+		group1 {
+			pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
+				<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
+				<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
+				<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
+				<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
+				<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
+			slew-rate = "fast";
+			drive-strength = "x1";
+		};
+
+		group2 {
+			pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
+			slew-rate = "fast";
+			drive-strength = "x1";
+		};
+	};
+
+	pinmux_mdio: pinmux_mdio {
+		group0 {
+			pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
+				<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
+			slew-rate = "slow";
+			drive-strength = "x6";
+		};
+	};
 };

boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2022 NXP
+ * Copyright 2020-2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,6 +36,30 @@
 	};
 };
 
+&enet {
+	status = "okay";
+};
+
+&enet_mac {
+	pinctrl-0 = <&pinmux_enet>;
+	pinctrl-names = "default";
+	phy-handle = <&phy>;
+	zephyr,random-mac-address;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enet_mdio {
+	pinctrl-0 = <&pinmux_mdio>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy: phy@0 {
+		compatible = "qca,ar8031";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
 &uart4 {
 	current-speed = <115200>;
 	pinctrl-0 = <&uart4_default>;

boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig

@@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y
 
 # Zephyr Kernel Configuration
 CONFIG_XIP=n
+CONFIG_KERNEL_DIRECT_MAP=y
 
 # Serial Drivers
 CONFIG_SERIAL=y

boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2022 NXP
+ * Copyright 2021-2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -38,6 +38,30 @@
 	};
 };
 
+&enet {
+	status = "okay";
+};
+
+&enet_mac {
+	pinctrl-0 = <&pinmux_enet>;
+	pinctrl-names = "default";
+	phy-handle = <&phy>;
+	zephyr,random-mac-address;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enet_mdio {
+	pinctrl-0 = <&pinmux_mdio>;
+	pinctrl-names = "default";
+	status = "okay";
+	phy: phy@0 {
+		compatible = "qca,ar8031";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
 &uart4 {
 	current-speed = <115200>;
 	pinctrl-0 = <&uart4_default>;

boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig

@@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y
 
 # Zephyr Kernel Configuration
 CONFIG_XIP=n
+CONFIG_KERNEL_DIRECT_MAP=y
 
 # SMP
 CONFIG_SMP=y

dts/arm64/nxp/nxp_mimx8mm_a53.dtsi

@@ -143,4 +143,36 @@
 		compatible = "nxp,rdc";
 		reg = <0x303d0000 DT_SIZE_K(64)>;
 	};
+
+	enet: enet@30be0000 {
+		compatible = "nxp,enet1g";
+		reg = <0x30be0000 DT_SIZE_K(64)>;
+		clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+
+		enet_mac: ethernet {
+			compatible = "nxp,enet-mac";
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "COMMON";
+			interrupt-parent = <&gic>;
+			nxp,mdio = <&enet_mdio>;
+			nxp,ptp-clock = <&enet_ptp_clock>;
+			status = "disabled";
+		};
+		enet_mdio: mdio {
+			compatible = "nxp,enet-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		enet_ptp_clock: ptp_clock {
+			compatible = "nxp,enet-ptp-clock";
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
+			status = "disabled";
+		};
+	};
+
 };