dts: bindings: riscv: Don't use riscv, prefix for vendor compat

In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for
sifive CPUs'), new compat strings for SiFive CPUs were added, but with
riscv prefixes. Vendor-specific compats should just be prefixed with the
vendor, so move that over here.

Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings
  for sifive CPUs')
Signed-off-by: Olof Johansson <olof@lixom.net>

dts/bindings/riscv/sifive,e24.yaml

@@ -3,6 +3,6 @@
 
 description: SiFive E24 Standard Core CPU
 
-compatible: "riscv,sifive-e24"
+compatible: "sifive,e24"
 
-include: riscv,sifive.yaml
+include: sifive-common.yaml

dts/bindings/riscv/sifive,e31.yaml

@@ -3,6 +3,6 @@
 
 description: SiFive E31 Standard Core CPU
 
-compatible: "riscv,sifive-e31"
+compatible: "sifive,e31"
 
-include: riscv,sifive.yaml
+include: sifive-common.yaml

dts/bindings/riscv/sifive,e51.yaml

@@ -3,6 +3,6 @@
 
 description: SiFive E51 Standard Core CPU
 
-compatible: "riscv,sifive-e51"
+compatible: "sifive,e51"
 
-include: riscv,sifive.yaml
+include: sifive-common.yaml

dts/bindings/riscv/sifive,s7.yaml

@@ -3,6 +3,6 @@
 
 description: SiFive S7 Standard Core CPU
 
-compatible: "riscv,sifive-s7"
+compatible: "sifive,s7"
 
-include: riscv,sifive.yaml
+include: sifive-common.yaml

dts/riscv/sifive/riscv32-fe310.dtsi

@@ -27,7 +27,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		cpu: cpu@0 {
-			compatible = "riscv,sifive-e31";
+			compatible = "sifive,e31";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32imac";

dts/riscv/sifive/riscv64-fu540.dtsi

@@ -33,7 +33,7 @@
 		#size-cells = <0>;
 
 		cpu: cpu@0 {
-			compatible = "riscv,sifive-e51";
+			compatible = "sifive,e51";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imac";

dts/riscv/sifive/riscv64-fu740.dtsi

@@ -32,7 +32,7 @@
 		#size-cells = <0>;
 
 		cpu: cpu@0 {
-			compatible = "riscv,sifive-s7";
+			compatible = "sifive,s7";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imac";