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dts: bindings: riscv: Don't use riscv, prefix for vendor compat

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In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for
sifive CPUs'), new compat strings for SiFive CPUs were added, but with
riscv prefixes. Vendor-specific compats should just be prefixed with the
vendor, so move that over here.

Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings
  for sifive CPUs')
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2022-06-14 19:42:00 +02:00 • committed by Carles Cufí
commit f847742c77
8 changed files with 11 additions and 11 deletions
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4
dts/bindings/riscv/riscv,sifive-e24.yaml → dts/bindings/riscv/sifive,e24.yaml
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@ -3,6 +3,6 @@
description: SiFive E24 Standard Core CPU description: SiFive E24 Standard Core CPU
compatible: "riscv,sifive-e24" compatible: "sifive,e24"
include: riscv,sifive.yaml include: sifive-common.yaml

4
dts/bindings/riscv/riscv,sifive-e31.yaml → dts/bindings/riscv/sifive,e31.yaml
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@ -3,6 +3,6 @@
description: SiFive E31 Standard Core CPU description: SiFive E31 Standard Core CPU
compatible: "riscv,sifive-e31" compatible: "sifive,e31"
include: riscv,sifive.yaml include: sifive-common.yaml

4
dts/bindings/riscv/riscv,sifive-e51.yaml → dts/bindings/riscv/sifive,e51.yaml
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@ -3,6 +3,6 @@
description: SiFive E51 Standard Core CPU description: SiFive E51 Standard Core CPU
compatible: "riscv,sifive-e51" compatible: "sifive,e51"
include: riscv,sifive.yaml include: sifive-common.yaml

4
dts/bindings/riscv/riscv,sifive-s7.yaml → dts/bindings/riscv/sifive,s7.yaml
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@ -3,6 +3,6 @@
description: SiFive S7 Standard Core CPU description: SiFive S7 Standard Core CPU
compatible: "riscv,sifive-s7" compatible: "sifive,s7"
include: riscv,sifive.yaml include: sifive-common.yaml

0
dts/bindings/riscv/riscv,sifive.yaml → dts/bindings/riscv/sifive-common.yaml
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2
dts/riscv/sifive/riscv32-fe310.dtsi
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@ -27,7 +27,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu: cpu@0 { cpu: cpu@0 {
compatible = "riscv,sifive-e31"; compatible = "sifive,e31";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
riscv,isa = "rv32imac"; riscv,isa = "rv32imac";

2
dts/riscv/sifive/riscv64-fu540.dtsi
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@ -33,7 +33,7 @@
#size-cells = <0>; #size-cells = <0>;
cpu: cpu@0 { cpu: cpu@0 {
compatible = "riscv,sifive-e51"; compatible = "sifive,e51";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
riscv,isa = "rv64imac"; riscv,isa = "rv64imac";

2
dts/riscv/sifive/riscv64-fu740.dtsi
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@ -32,7 +32,7 @@
#size-cells = <0>; #size-cells = <0>;
cpu: cpu@0 { cpu: cpu@0 {
compatible = "riscv,sifive-s7"; compatible = "sifive,s7";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
riscv,isa = "rv64imac"; riscv,isa = "rv64imac";