arch: arm: aarch32: initialize FPSCR to reset value for ARMv8.1
With GCC 11 now supporting low overhead branching in ARMv8.1, ASM "LE" (loop-end) instructions would trigger an INVSTATE hard-fault after FPSCR was set to 0. This was due to the FPSCR getting a new field in ARMv8.1. LTPSIZE is now set to it's reset value of Tail predication not applied. Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
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@ -144,7 +144,15 @@ static inline void z_arm_floating_point_init(void)
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__ISB();
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/* Initialize the Floating Point Status and Control Register. */
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#if defined(CONFIG_ARMV8_1_M_MAINLINE)
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/*
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* For ARMv8.1-M with FPU, the FPSCR[18:16] LTPSIZE field must be set
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* to 0b100 for "Tail predication not applied" as it's reset value
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*/
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__set_FPSCR(4 << FPU_FPDSCR_LTPSIZE_Pos);
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#else
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__set_FPSCR(0);
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#endif
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/*
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* Note:
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@ -499,7 +499,15 @@ static void z_arm_prepare_switch_to_main(void)
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* Unshared FP Registers mode (In Shared FP Registers mode, FPSCR is
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* initialized at thread creation for threads that make use of the FP).
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*/
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#if defined(CONFIG_ARMV8_1_M_MAINLINE)
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/*
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* For ARMv8.1-M with FPU, the FPSCR[18:16] LTPSIZE field must be set
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* to 0b100 for "Tail predication not applied" as it's reset value
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*/
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__set_FPSCR(4 << FPU_FPDSCR_LTPSIZE_Pos);
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#else
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__set_FPSCR(0);
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#endif
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#if defined(CONFIG_FPU_SHARING)
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/* In Sharing mode clearing FPSCR may set the CONTROL.FPCA flag. */
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__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
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@ -197,7 +197,15 @@ void arm_isr_handler(const void *args)
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* to prevent from having the interrupt line set to pending again,
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* in case FPU IRQ is selected by the test as "Available IRQ line"
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*/
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#if defined(CONFIG_ARMV8_1_M_MAINLINE)
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/*
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* For ARMv8.1-M with FPU, the FPSCR[18:16] LTPSIZE field must be set
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* to 0b100 for "Tail predication not applied" as it's reset value
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*/
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__set_FPSCR(4 << FPU_FPDSCR_LTPSIZE_Pos);
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#else
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__set_FPSCR(0);
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#endif
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#endif
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test_flag++;
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