drivers/i2c: Add I2C driver of it51xxx

Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
      0~12.
      supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
      interface 0~8.
      supports 16 bytes dedicated FIFO mode that only supports write or
      read mode and the maximum buffer size is 256 bytes.
      support non-FIFO write to shared FIFO read mode. The maximum
      shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
                       i2c_burst_write(), i2c_write_read()

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>

boards/ite/it515xx_evb/it515xx_evb.dts

@@ -15,6 +15,7 @@
 	compatible = "ite,it515xx-evb";
 
 	aliases {
+		i2c-0 = &i2c0;
 		led0 = &led0;
 		watchdog0 = &twd0;
 	};
@@ -38,6 +39,14 @@
 	};
 };
 
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_clk_gpf2_default
+		     &i2c0_data_gpf3_default>;
+	pinctrl-names = "default";
+};
+
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;

boards/ite/it515xx_evb/it515xx_evb.yaml

@@ -8,6 +8,7 @@ ram: 128
 supported:
   - flash
   - gpio
+  - i2c
   - pinctrl
   - pm
   - uart

drivers/i2c/CMakeLists.txt

@@ -38,6 +38,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_INFINEON_CAT1	i2c_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_INFINEON_XMC4	i2c_ifx_xmc4.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_IPROC		i2c_bcm_iproc.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_ITE_ENHANCE	i2c_ite_enhance.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_ITE_IT51XXX	i2c_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_ITE_IT8XXX2	i2c_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_LITEX		i2c_litex.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_LITEX_LITEI2C	i2c_litex_litei2c.c)

drivers/i2c/Kconfig

@@ -132,6 +132,7 @@ source "drivers/i2c/Kconfig.gpio"
 source "drivers/i2c/Kconfig.i2c_emul"
 source "drivers/i2c/Kconfig.ifx_cat1"
 source "drivers/i2c/Kconfig.ifx_xmc4"
+source "drivers/i2c/Kconfig.it51xxx"
 source "drivers/i2c/Kconfig.it8xxx2"
 source "drivers/i2c/Kconfig.litex"
 source "drivers/i2c/Kconfig.lpc11u6x"

drivers/i2c/Kconfig.it51xxx

@@ -0,0 +1,51 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_ITE_IT51XXX
+	bool "ITE IT51XXX I2C driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_I2C_ENABLED
+	select PINCTRL
+	select I2C_BITBANG
+	help
+	  Enable I2C support on IT51XXX series.
+	  Supports nine hosts and three targets and each one able to located
+	  at I2C interface0~8.
+	  Three I2C targets on design A, B and C. Support 16 bytes dedicated
+	  FIFO mode for read/write.
+	  Supported Speeds: 50kHz, 100kHz, 400kHz and 1MHz.
+	  This driver supports repeated start.
+
+if I2C_ITE_IT51XXX
+
+config I2C_IT51XXX_FIFO_MODE
+	bool "IT51XXX I2C FIFO mode"
+	default y
+	help
+	  This is an option to enable FIFO mode which can reduce the time
+	  between each byte to improve the I2C bus clock stretching during
+	  I2C transaction.
+	  The I2C controller supports two 32-bytes FIFOs,
+	  FIFO1 supports I2C 0, and FIFO2 supports other ports.
+	  I2C FIFO mode of IT51XXX can support I2C APIs including:
+	  i2c_write(), i2c_read(), i2c_burst_read.
+
+endif # I2C_ITE_IT51XXX
+
+if I2C_TARGET
+
+config I2C_TARGET_IT51XXX_MAX_BUF_SIZE
+	int "It is allowed to configure the dedicated FIFO size up to 256 bytes."
+	default 256
+
+config I2C_IT51XXX_MAX_SHARE_FIFO_SIZE
+	int "It is allowed to configure the shared FIFO size up to 256 bytes."
+	range 16 256
+	default 256
+
+config SOC_IT51XXX_CPU_IDLE_GATING
+	default y
+	help
+	  This option is used when the I2C target shared FIFO property is enabled.
+
+endif # I2C_TARGET

dts/bindings/i2c/ite,it51xxx-i2c.yaml

@@ -0,0 +1,201 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it51xxx I2C
+
+compatible: "ite,it51xxx-i2c"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  scl-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The SCL pin for the selected port.
+
+  sda-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The SDA pin for the selected port.
+
+  transfer-timeout-ms:
+    type: int
+    default: 500
+    description: |
+      Maximum time allowed for an I2C transfer.
+
+  port-num:
+    type: int
+    required: true
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+      - 4
+      - 5
+      - 6
+      - 7
+      - 8
+    description: Ordinal identifying the port
+      0 = SMB_CHANNEL_A,
+      1 = SMB_CHANNEL_B,
+      2 = SMB_CHANNEL_C,
+      3 = SMB_CHANNEL_D,
+      4 = SMB_CHANNEL_E,
+      5 = SMB_CHANNEL_F,
+      6 = SMB_CHANNEL_G,
+      7 = SMB_CHANNEL_H,
+      8 = SMB_CHANNEL_I,
+
+  channel-switch-sel:
+    type: int
+    required: true
+    enum:
+      - 1
+      - 2
+      - 3
+      - 4
+      - 5
+      - 6
+      - 7
+      - 8
+      - 9
+      - 10
+      - 11
+      - 12
+      - 13
+    description: |
+      The default setting is as described below
+      1 = SMB_SWITCH_INTERFACE0: Switch to interface0 SMCLK0/SMDAT0
+      2 = SMB_SWITCH_INTERFACE1: Switch to interface1 SMCLK1/SMDAT1
+      3 = SMB_SWITCH_INTERFACE2: Switch to interface2 SMCLK2/SMDAT2
+      4 = SMB_SWITCH_INTERFACE3: Switch to interface3 SMCLK3/SMDAT3
+      5 = SMB_SWITCH_INTERFACE4: Switch to interface4 SMCLK4/SMDAT4
+      6 = SMB_SWITCH_INTERFACE5: Switch to interface5 SMCLK5/SMDAT5
+      7 = SMB_SWITCH_INTERFACE6: Switch to interface6 SMCLK6/SMDAT6
+      8 = SMB_SWITCH_INTERFACE7: Switch to interface7 SMCLK7/SMDAT7
+      9 = SMB_SWITCH_INTERFACE8: Switch to interface8 SMCLK8/SMDAT8
+      10 = SMB_SWITCH_INTERFACE9: Switch to interface9 SMCLK9/SMDAT9
+      11 = SMB_SWITCH_INTERFACE10: Switch to interface10 SMCLK10/SMDAT10
+      12 = SMB_SWITCH_INTERFACE11: Switch to interface11 SMCLK11/SMDAT11
+      13 = SMB_SWITCH_INTERFACE12: Switch to interface12 SMCLK12/SMDAT12
+
+      The following is an example of the 'channel-switch-sel' property
+      being swapped between node &i2c0 and &i2c2 in the application:
+      Note: The property of 'port-num' cannot be changed in the
+            application.
+
+            If the property of 'channel-switch-sel' is changed, the pinctrl
+            setting and recovery pin in &i2c0 and &i2c2 nodes must also be
+            modified accordingly.
+
+      Valid example(Host):
+
+      Channel A switches to interface2:
+      &i2c0 {
+             status = "okay";
+             pinctrl-0 = <&i2c2_clk_gpf6_default
+                          &i2c2_data_gpf7_default>;
+             pinctrl-names = "default";
+             scl-gpios = <&gpiof 6 0>;
+             sda-gpios = <&gpiof 7 0>;
+             channel-switch-sel = <SMB_SWITCH_INTERFACE2>;
+      };
+
+      Channel C switches to interface0:
+      &i2c2 {
+             status = "okay";
+             pinctrl-0 = <&i2c0_clk_gpf2_default
+                          &i2c0_data_gpf3_default>;
+             pinctrl-names = "default";
+             scl-gpios = <&gpiof 2 0>;
+             sda-gpios = <&gpiof 3 0>;
+             channel-switch-sel = <SMB_SWITCH_INTERFACE0>;
+      };
+
+      Invalid example(Host):
+
+      Channel A switches to interface2:
+      &i2c0 {
+             status = "okay";
+             pinctrl-0 = <&i2c2_clk_gpf6_default
+                          &i2c2_data_gpf7_default>;
+             pinctrl-names = "default";
+             scl-gpios = <&gpiof 6 0>;
+             sda-gpios = <&gpiof 7 0>;
+             channel-switch-sel = <SMB_SWITCH_INTERFACE2>;
+      };
+
+      Channel C maintains the original configuration:
+      &i2c2 {
+             status = "okay";
+             pinctrl-0 = <&i2c2_clk_gpf6_default
+                          &i2c2_data_gpf7_default>;
+             pinctrl-names = "default";
+      };
+
+      Valid example(Target):
+
+      Channel A switches to interface5:
+      &i2c0 {
+             status = "okay";
+             pinctrl-0 = <&i2c5_clk_gpa4_default
+                          &i2c5_data_gpa5_default>;
+             pinctrl-names = "default";
+             scl-gpios = <&gpioa 4 0>;
+             sda-gpios = <&gpioa 5 0>;
+             channel-switch-sel = <SMB_SWITCH_INTERFACE5>;
+
+             target-enable;
+             i2c0_target: target@52 {
+                 compatible = "ite,target-i2c";
+                 reg = <0x52>;
+             };
+      };
+
+  target-enable:
+    type: boolean
+    description: |
+      This option is used when the I2C target is enabled. It is
+      necessary to prevent the target port from being configured
+      with I2C host related initialization.
+
+  target-fifo-mode:
+    type: boolean
+    description: |
+      Only supports write or read mode and the maximum buffer size
+      is 256 bytes. Support dedicated FIFO mode 16 bytes.
+
+  target-shared-fifo-mode:
+    type: boolean
+    description: |
+      This option is used to support non-FIFO write to shared FIFO
+      read mode. The maximum supported shared FIFO is 256 bytes.
+
+  fifo-enable:
+    type: boolean
+    description: |
+      The I2C controller supports two 32-bytes FIFOs,
+      FIFO1 supports I2C port 0. FIFO2 only supports one port among
+      1~8. The default is I2C port 1.
+
+  push-pull-recovery:
+    type: boolean
+    description: |
+      This property is enabled when selecting the push-pull GPIO output
+      type to drive the I2C recovery. The default is open-drain.

dts/riscv/ite/it51xxx-pinctrl-map.dtsi

@@ -113,6 +113,39 @@
 		pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_4>;
 	};
 
+	/* I2C switch to interface */
+	i2c9_clk_gpj3_default: i2c9_clk_gpj3_default {
+		pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c9_data_gpj4_default: i2c9_data_gpj4_default {
+		pinmuxs = <&pinctrlj 4 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c10_clk_gpj5_default: i2c10_clk_gpj5_default {
+		pinmuxs = <&pinctrlj 5 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c10_data_gpe1_default: i2c10_data_gpe1_default {
+		pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c11_clk_gpe2_default: i2c11_clk_gpe2_default {
+		pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c11_data_gpe3_default: i2c11_data_gpe3_default {
+		pinmuxs = <&pinctrle 3 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c12_clk_gpf0_default: i2c12_clk_gpf0_default {
+		pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c12_data_gpf1_default: i2c12_data_gpf1_default {
+		pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_3>;
+	};
+
 	/* I3C alternate function */
 	i3c0_clk_gpj3_default: i3c0_clk_gpj3_default {
 		pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_1>;

dts/riscv/ite/it51xxx.dtsi

@@ -10,6 +10,8 @@
 #include <zephyr/dt-bindings/dt-util.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/i2c/it51xxx-i2c.h>
 #include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h>
 #include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h>
 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
@@ -602,9 +604,9 @@
 			compatible = "ite,it8xxx2-pinctrl-func";
 			reg = <0x00f01630 8     /* GPCR */
 			       NO_FUNC    1>;
-			func3-gcr =     <0xf016f3 NO_FUNC  NO_FUNC  NO_FUNC
+			func3-gcr =     <0xf016f3 0xf016ed 0xf016ed 0xf016ed
 					 NO_FUNC  0xf016f0 0xf016fe 0xf016fe>;
-			func3-en-mask = <BIT(0)   0        0        0
+			func3-en-mask = <BIT(0)   BIT(5)   BIT(6)   BIT(6)
 					 0        BIT(3)   BIT(7)   BIT(4)  >;
 			func4-gcr =     <0xf016fe NO_FUNC  NO_FUNC  NO_FUNC
 					 NO_FUNC  NO_FUNC  0xf016f5 NO_FUNC >;
@@ -622,9 +624,9 @@
 			compatible = "ite,it8xxx2-pinctrl-func";
 			reg = <0x00f01638 8     /* GPCR */
 			       NO_FUNC    1>;
-			func3-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+			func3-gcr =     <0xf016d1 0xf016d1 NO_FUNC  NO_FUNC
 					 NO_FUNC  NO_FUNC  0xf016f1 NO_FUNC>;
-			func3-en-mask = <0        0        0        0
+			func3-en-mask = <BIT(2)   BIT(2)   0        0
 					 0        0        BIT(4)   0      >;
 			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
 					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC>;
@@ -702,10 +704,10 @@
 			compatible = "ite,it8xxx2-pinctrl-func";
 			reg = <0x00f01658 8     /* GPCR */
 			       NO_FUNC    1>;
-			func3-gcr =     <0xf016f1 0xf016fe NO_FUNC  NO_FUNC
+			func3-gcr =     <0xf016f1 0xf016fe NO_FUNC  0xf016ed
-					 NO_FUNC  NO_FUNC  0xf016f4 0xf016d1>;
+					 0xf016ed 0xf016ed 0xf016f4 0xf016d1>;
-			func3-en-mask = <BIT(7)   BIT(3)   0        0
+			func3-en-mask = <BIT(7)   BIT(3)   0        BIT(4)
-					 0        0        BIT(1)   BIT(3)  >;
+					 BIT(4)   BIT(5)   BIT(1)   BIT(3)  >;
 			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
 					 NO_FUNC  NO_FUNC  0xf016ed 0xf016f0>;
 			func4-en-mask = <0        0        0        0
@@ -927,6 +929,165 @@
 			#wuc-cells = <1>;
 		};
 
+		i2cbase: i2cbase@f04100 {
+			compatible = "ite,it51xxx-i2cbase";
+			reg = <0x00f04100 1
+			       0x00f01c00 1>;
+		};
+
+		i2c0: i2c@f04100 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04100 0x0028
+			       0x00f04200 0x0020>;
+			interrupts = <IT51XXX_IRQ_SMB_A IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_SMB_SA IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpiof 2 0>;
+			sda-gpios = <&gpiof 3 0>;
+			port-num = <SMB_CHANNEL_A>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE0>;
+			fifo-enable;   /* FIFO1 */
+		};
+
+		i2c1: i2c@f04128 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04128 0x0028
+			       0x00f04220 0x0020>;
+			interrupts = <IT51XXX_IRQ_SMB_B IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_SMB_SB IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpioc 1 0>;
+			sda-gpios = <&gpioc 2 0>;
+			port-num = <SMB_CHANNEL_B>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE1>;
+			fifo-enable;   /* FIFO2 */
+		};
+
+		i2c2: i2c@f04150 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04150 0x0028
+			       0x00f04240 0x0020>;
+			interrupts = <IT51XXX_IRQ_SMB_C IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_SMB_SC IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpiof 6 0>;
+			sda-gpios = <&gpiof 7 0>;
+			port-num = <SMB_CHANNEL_C>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE2>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c3: i2c@f04178 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04178 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_D IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpioh 1 0>;
+			sda-gpios = <&gpioh 2 0>;
+			port-num = <SMB_CHANNEL_D>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE3>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c4: i2c@f041a0 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f041a0 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_E IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpioe 0 0>;
+			sda-gpios = <&gpioe 7 0>;
+			port-num = <SMB_CHANNEL_E>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE4>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c5: i2c@f041c8 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f041c8 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_F IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpioa 4 0>;
+			sda-gpios = <&gpioa 5 0>;
+			port-num = <SMB_CHANNEL_F>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE5>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c6: i2c@f04260 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04260 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_G IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpiod 0 0>;
+			sda-gpios = <&gpiod 1 0>;
+			port-num = <SMB_CHANNEL_G>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE6>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c7: i2c@f04288 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f04288 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_H IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpiob 2 0>;
+			sda-gpios = <&gpioh 0 0>;
+			port-num = <SMB_CHANNEL_H>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE7>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
+		i2c8: i2c@f042b0 {
+			compatible = "ite,it51xxx-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			reg = <0x00f042b0 0x0028
+			       0 1>;
+			interrupts = <IT51XXX_IRQ_SMB_I IRQ_TYPE_LEVEL_HIGH
+				      0 0>;
+			interrupt-parent = <&intc>;
+			scl-gpios = <&gpiob 5 0>;
+			sda-gpios = <&gpioj 6 0>;
+			port-num = <SMB_CHANNEL_I>;
+			channel-switch-sel = <SMB_SWITCH_INTERFACE8>;
+			/delete-property/ fifo-enable;   /* FIFO2 */
+		};
+
 		ecpm: clock-controller@f01e00 {
 			compatible = "ite,it51xxx-ecpm";
 			reg = <0x00f01e00 0x0a>;

include/zephyr/dt-bindings/i2c/i2c.h

@@ -15,6 +15,12 @@
 #define SMB_CHANNEL_A	0
 #define SMB_CHANNEL_B	1
 #define SMB_CHANNEL_C	2
+#define SMB_CHANNEL_D   3
+#define SMB_CHANNEL_E   4
+#define SMB_CHANNEL_F   5
+#define SMB_CHANNEL_G   6
+#define SMB_CHANNEL_H   7
+#define SMB_CHANNEL_I   8
 #define I2C_CHANNEL_D	3
 #define I2C_CHANNEL_E	4
 #define I2C_CHANNEL_F	5

include/zephyr/dt-bindings/i2c/it51xxx-i2c.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 ITE Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT51XXX_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT51XXX_H_
+
+/* SMBus channel switch selection */
+#define SMB_SWITCH_INTERFACE0  1
+#define SMB_SWITCH_INTERFACE1  2
+#define SMB_SWITCH_INTERFACE2  3
+#define SMB_SWITCH_INTERFACE3  4
+#define SMB_SWITCH_INTERFACE4  5
+#define SMB_SWITCH_INTERFACE5  6
+#define SMB_SWITCH_INTERFACE6  7
+#define SMB_SWITCH_INTERFACE7  8
+#define SMB_SWITCH_INTERFACE8  9
+#define SMB_SWITCH_INTERFACE9  10
+#define SMB_SWITCH_INTERFACE10 11
+#define SMB_SWITCH_INTERFACE11 12
+#define SMB_SWITCH_INTERFACE12 13
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT51XXX_H_ */

soc/ite/ec/it51xxx/chip_chipregs.h

@@ -323,4 +323,16 @@ struct gctrl_it51xxx_regs {
 #define gctrl_ite_ec_regs      gctrl_it51xxx_regs
 #define GCTRL_ITE_EC_REGS_BASE GCTRL_IT51XXX_REGS_BASE
 
+/**
+ *
+ * (42xxh) SMBus Interface for target (SMB) registers
+ *
+ */
+#define IT51XXX_SMB_BASE 0xf04200
+/* 0x0a, 0x2a, 0x4a: Slave n Dedicated FIFO Pre-defined Control Register */
+#define SMB_SADFPCTL     (IT51XXX_SMB_BASE + 0x0a)
+#define SMB_SBDFPCTL     (IT51XXX_SMB_BASE + 0x2a)
+#define SMB_SCDFPCTL     (IT51XXX_SMB_BASE + 0x4a)
+#define SMB_HSAPE        BIT(1)
+
 #endif /* CHIP_CHIPREGS_H */

soc/ite/ec/it51xxx/soc.c

@@ -116,4 +116,13 @@ void soc_prep_hook(void)
 	/* Switch UART1 and UART2 on without hardware flow control */
 	gpio_regs->GPIO_GCR1 |=
 		IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN | IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN;
+
+	/*
+	 * Disable this feature that can detect pre-define hardware target A, B, C through
+	 * I2C0, I2C1, I2C2 respectively. This is for debugging use, so it can be disabled
+	 * to avoid illegal access.
+	 */
+	sys_write8(sys_read8(SMB_SADFPCTL) & ~SMB_HSAPE, SMB_SADFPCTL);
+	sys_write8(sys_read8(SMB_SBDFPCTL) & ~SMB_HSAPE, SMB_SBDFPCTL);
+	sys_write8(sys_read8(SMB_SCDFPCTL) & ~SMB_HSAPE, SMB_SCDFPCTL);
 }