From f7bad922f086a7e2d9b87c175586e5ce7c3b90dd Mon Sep 17 00:00:00 2001 From: Richard Osterloh Date: Wed, 4 Sep 2019 09:40:48 +0100 Subject: [PATCH] drivers: gpio: Add STM32G4X gpio support Add GPIO driver support for STM32G4X SoC series. Signed-off-by: Richard Osterloh --- drivers/gpio/gpio_stm32.c | 3 +- drivers/gpio/gpio_stm32.h | 9 +++ dts/arm/st/g4/stm32g4.dtsi | 70 +++++++++++++++++++ .../st_stm32/stm32g4/Kconfig.defconfig.series | 17 +++++ soc/arm/st_stm32/stm32g4/dts_fixup.h | 63 +++++++++++++++++ soc/arm/st_stm32/stm32g4/soc.h | 4 ++ 6 files changed, 165 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 2718c175e81..94676d687e2 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -196,7 +196,8 @@ const int gpio_stm32_enable_int(int port, int pin) defined(CONFIG_SOC_SERIES_STM32F7X) || \ defined(CONFIG_SOC_SERIES_STM32H7X) || \ defined(CONFIG_SOC_SERIES_STM32L1X) || \ - defined(CONFIG_SOC_SERIES_STM32L4X) + defined(CONFIG_SOC_SERIES_STM32L4X) || \ + defined(CONFIG_SOC_SERIES_STM32G4X) struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); struct stm32_pclken pclken = { #ifdef CONFIG_SOC_SERIES_STM32H7X diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h index 2968d3664f4..a798cceca82 100644 --- a/drivers/gpio/gpio_stm32.h +++ b/drivers/gpio/gpio_stm32.h @@ -153,6 +153,15 @@ #define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD #define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE #define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH +#elif CONFIG_SOC_SERIES_STM32G4X +#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2 +#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA +#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB +#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC +#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD +#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE +#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF +#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG #endif /* CONFIG_SOC_SERIES_* */ #ifdef CONFIG_SOC_SERIES_STM32F1X diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index 0ac076fef06..d64400a629f 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { cpus { @@ -32,6 +33,75 @@ label = "STM32_CLK_RCC"; }; + pinctrl: pin-controller@48000000 { + compatible = "st,stm32-pinmux"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x48000000 0x2000>; + + gpioa: gpio@48000000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; + label = "GPIOA"; + }; + + gpiob: gpio@48000400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; + label = "GPIOB"; + }; + + gpioc: gpio@48000800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; + label = "GPIOC"; + }; + + gpiod: gpio@48000c00 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48000c00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; + label = "GPIOD"; + }; + + gpioe: gpio@48001000 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; + label = "GPIOE"; + }; + + gpiof: gpio@48001400 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; + label = "GPIOF"; + }; + + gpiog: gpio@48001800 { + compatible = "st,stm32-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x48001800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; + label = "GPIOG"; + }; + }; }; }; diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series index 07acc937604..69d78837359 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series +++ b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series @@ -12,4 +12,21 @@ source "soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4*" config SOC_SERIES default "stm32g4" +if GPIO_STM32 + +# GPIO ports A, B and C are set in ../common/Kconfig.defconfig.series + +config GPIO_STM32_PORTD + default y + +config GPIO_STM32_PORTE + default y + +config GPIO_STM32_PORTF + default y + +config GPIO_STM32_PORTG + default y + +endif # GPIO_STM32 endif # SOC_SERIES_STM32G4X diff --git a/soc/arm/st_stm32/stm32g4/dts_fixup.h b/soc/arm/st_stm32/stm32g4/dts_fixup.h index 20be3443b2f..7e307c11f66 100644 --- a/soc/arm/st_stm32/stm32g4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32g4/dts_fixup.h @@ -8,4 +8,67 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_48001800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_48001800_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_48001800_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_48001800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_48001800_CLOCK_BUS + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h index f4832aaa893..c96a8577048 100644 --- a/soc/arm/st_stm32/stm32g4/soc.h +++ b/soc/arm/st_stm32/stm32g4/soc.h @@ -34,6 +34,10 @@ #include #include #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + +#ifdef CONFIG_GPIO_STM32 +#include +#endif #endif /* !_ASMLANGUAGE */ #endif /* _STM32G4_SOC_H_ */