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gpio: intel_apl: rework driver for pin_mask callback

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To avoid confusion, callbacks using ordinal pin numbers
is going to be reverted. So the driver has to be re-worked
to expose multiple devices so each device has 32 pins.

Also fixes #12765

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2019-01-29 19:34:41 -08:00 • committed by Anas Nashif
commit f7a42a70f8
10 changed files with 619 additions and 440 deletions
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111
boards/x86/up_squared/board.h
View file

@ -8,33 +8,88 @@
#define __INC_BOARD_H #define __INC_BOARD_H
/* Map APL GPIO pins to pins on UP Squared HAT */ /* Map APL GPIO pins to pins on UP Squared HAT */
#define UP2_HAT_PIN_3 APL_GPIO_28 #define UP2_HAT_PIN_3_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_5 APL_GPIO_29 #define UP2_HAT_PIN_3 APL_GPIO_28
#define UP2_HAT_PIN_7 APL_GPIO_123
#define UP2_HAT_PIN_8 APL_GPIO_43 #define UP2_HAT_PIN_5_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_10 APL_GPIO_42 #define UP2_HAT_PIN_5 APL_GPIO_29
#define UP2_HAT_PIN_11 APL_GPIO_44
#define UP2_HAT_PIN_12 APL_GPIO_146 #define UP2_HAT_PIN_7_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_13 APL_GPIO_122 #define UP2_HAT_PIN_7 APL_GPIO_123
#define UP2_HAT_PIN_15 APL_GPIO_121
#define UP2_HAT_PIN_16 APL_GPIO_37 #define UP2_HAT_PIN_8_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_18 APL_GPIO_88 #define UP2_HAT_PIN_8 APL_GPIO_43
#define UP2_HAT_PIN_19 APL_GPIO_110
#define UP2_HAT_PIN_21 APL_GPIO_109 #define UP2_HAT_PIN_10_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_22 APL_GPIO_85 #define UP2_HAT_PIN_10 APL_GPIO_42
#define UP2_HAT_PIN_23 APL_GPIO_104
#define UP2_HAT_PIN_24 APL_GPIO_105 #define UP2_HAT_PIN_11_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_26 APL_GPIO_106 #define UP2_HAT_PIN_11 APL_GPIO_44
#define UP2_HAT_PIN_27 APL_GPIO_30
#define UP2_HAT_PIN_28 APL_GPIO_31 #define UP2_HAT_PIN_12_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_29 APL_GPIO_120 #define UP2_HAT_PIN_12 APL_GPIO_146
#define UP2_HAT_PIN_31 APL_GPIO_87
#define UP2_HAT_PIN_32 APL_GPIO_34 #define UP2_HAT_PIN_13_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_33 APL_GPIO_35 #define UP2_HAT_PIN_13 APL_GPIO_122
#define UP2_HAT_PIN_35 APL_GPIO_147
#define UP2_HAT_PIN_36 APL_GPIO_45 #define UP2_HAT_PIN_15_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_37 APL_GPIO_86 #define UP2_HAT_PIN_15 APL_GPIO_121
#define UP2_HAT_PIN_38 APL_GPIO_148
#define UP2_HAT_PIN_40 APL_GPIO_149 #define UP2_HAT_PIN_16_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_16 APL_GPIO_37
#define UP2_HAT_PIN_18_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_18 APL_GPIO_88
#define UP2_HAT_PIN_19_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_19 APL_GPIO_110
#define UP2_HAT_PIN_21_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_21 APL_GPIO_109
#define UP2_HAT_PIN_22_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_22 APL_GPIO_85
#define UP2_HAT_PIN_23_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_23 APL_GPIO_104
#define UP2_HAT_PIN_24_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_24 APL_GPIO_105
#define UP2_HAT_PIN_26_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_26 APL_GPIO_106
#define UP2_HAT_PIN_27_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_27 APL_GPIO_30
#define UP2_HAT_PIN_28_DEV APL_GPIO_DEV_N_0
#define UP2_HAT_PIN_28 APL_GPIO_31
#define UP2_HAT_PIN_29_DEV APL_GPIO_DEV_NW_2
#define UP2_HAT_PIN_29 APL_GPIO_120
#define UP2_HAT_PIN_31_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_31 APL_GPIO_87
#define UP2_HAT_PIN_32_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_32 APL_GPIO_34
#define UP2_HAT_PIN_33_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_33 APL_GPIO_35
#define UP2_HAT_PIN_35_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_35 APL_GPIO_147
#define UP2_HAT_PIN_36_DEV APL_GPIO_DEV_N_1
#define UP2_HAT_PIN_36 APL_GPIO_45
#define UP2_HAT_PIN_37_DEV APL_GPIO_DEV_NW_1
#define UP2_HAT_PIN_37 APL_GPIO_86
#define UP2_HAT_PIN_38_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_38 APL_GPIO_148
#define UP2_HAT_PIN_40_DEV APL_GPIO_DEV_W_0
#define UP2_HAT_PIN_40 APL_GPIO_149
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

234
drivers/gpio/gpio_intel_apl.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018 Intel Corporation * Copyright (c) 2018-2019 Intel Corporation
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -12,21 +12,26 @@
* both GPIOs and Pinmuxing function. This driver provides * both GPIOs and Pinmuxing function. This driver provides
* the GPIO function. * the GPIO function.
* *
* Currently, this driver does not handle pin triggering. * The GPIO controller has 245 pins divided into four sets.
* * Each set has its own MMIO address space. Due to GPIO
* Note that since the GPIO controller controls more then 32 pins, * callback only allowing 32 pins (as a 32-bit mask) at once,
* the pin_mux of the API does not work anymore. * each set is further sub-divided into multiple devices.
* Because of this, shared IRQ must be used.
*/ */
#include <errno.h> #include <errno.h>
#include <gpio.h> #include <gpio.h>
#include <shared_irq.h>
#include <soc.h> #include <soc.h>
#include <sys_io.h> #include <sys_io.h>
#include <misc/__assert.h>
#include <misc/slist.h> #include <misc/slist.h>
#include "gpio_utils.h" #include "gpio_utils.h"
#define NUM_ISLANDS 4 #ifndef CONFIG_SHARED_IRQ
#error "Need CONFIG_SHARED_IRQ!"
#endif
#define REG_PAD_BASE_ADDR 0x000C #define REG_PAD_BASE_ADDR 0x000C
@ -85,40 +90,30 @@
#define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS) #define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
#define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS) #define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
struct apl_gpio_island {
u32_t reg_base;
u32_t num_pins;
};
struct gpio_intel_apl_config { struct gpio_intel_apl_config {
struct apl_gpio_island islands[NUM_ISLANDS]; u32_t reg_base;
u8_t pin_offset;
u8_t num_pins;
}; };
struct gpio_intel_apl_data { struct gpio_intel_apl_data {
/* Pad base address for each island */ /* Pad base address */
u32_t pad_base[NUM_ISLANDS]; u32_t pad_base;
sys_slist_t cb; sys_slist_t cb;
}; };
static inline void extract_island_and_pin(u32_t pin, u32_t *island,
u32_t *raw_pin)
{
*island = pin >> APL_GPIO_ISLAND_POS;
*raw_pin = pin & APL_GPIO_PIN_MASK;
}
#ifdef CONFIG_GPIO_INTEL_APL_CHECK_PERMS #ifdef CONFIG_GPIO_INTEL_APL_CHECK_PERMS
/** /**
* @brief Check if host has permission to alter this GPIO pin. * @brief Check if host has permission to alter this GPIO pin.
* *
* @param "struct device *dev" Device struct * @param "struct device *dev" Device struct
* @param "u32_t island" Island index
* @param "u32_t raw_pin" Raw GPIO pin * @param "u32_t raw_pin" Raw GPIO pin
* *
* @return true if host owns the GPIO pin, false otherwise * @return true if host owns the GPIO pin, false otherwise
*/ */
static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin) static bool check_perm(struct device *dev, u32_t raw_pin)
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
@ -128,7 +123,7 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
/* read the Pad Ownership register related to the pin */ /* read the Pad Ownership register related to the pin */
offset = REG_PAD_OWNER_BASE + ((raw_pin >> 3) << 2); offset = REG_PAD_OWNER_BASE + ((raw_pin >> 3) << 2);
val = sys_read32(cfg->islands[island].reg_base + offset); val = sys_read32(cfg->reg_base + offset);
/* get the bits about ownership */ /* get the bits about ownership */
offset = raw_pin % 8; offset = raw_pin % 8;
@ -139,8 +134,8 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
} }
/* Also need to make sure the function of pad is GPIO */ /* Also need to make sure the function of pad is GPIO */
offset = data->pad_base[island] + (raw_pin << 3); offset = data->pad_base + (raw_pin << 3);
val = sys_read32(cfg->islands[island].reg_base + offset); val = sys_read32(cfg->reg_base + offset);
if (val & PAD_CFG0_PMODE_MASK) { if (val & PAD_CFG0_PMODE_MASK) {
/* mode is not zero => not functioning as GPIO */ /* mode is not zero => not functioning as GPIO */
return false; return false;
@ -152,24 +147,31 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
#define check_perm(...) (1) #define check_perm(...) (1)
#endif #endif
static void gpio_intel_apl_isr(void *arg) static int gpio_intel_apl_isr(struct device *dev)
{ {
struct device *dev = arg;
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
struct gpio_callback *cb; struct gpio_callback *cb, *tmp;
u32_t island, raw_pin, reg; u32_t reg, int_sts, cur_mask, acc_mask;
SYS_SLIST_FOR_EACH_CONTAINER(&data->cb, cb, node) { reg = cfg->reg_base + REG_GPI_INT_STS_BASE
extract_island_and_pin(cb->pin, &island, &raw_pin); + ((cfg->pin_offset >> 5) << 2);
int_sts = sys_read32(reg);
acc_mask = 0;
reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE; SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {
cur_mask = int_sts & cb->pin_mask;
if (sys_bitfield_test_and_set_bit(reg, raw_pin)) { acc_mask |= cur_mask;
if (cur_mask) {
__ASSERT(cb->handler, "No callback handler!"); __ASSERT(cb->handler, "No callback handler!");
cb->handler(dev, cb, cb->pin); cb->handler(dev, cb, cur_mask);
} }
} }
/* clear handled interrupt bits */
sys_write32(acc_mask, reg);
return 0;
} }
static int gpio_intel_apl_config(struct device *dev, int access_op, static int gpio_intel_apl_config(struct device *dev, int access_op,
@ -177,13 +179,20 @@ static int gpio_intel_apl_config(struct device *dev, int access_op,
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
u32_t island, raw_pin, reg, cfg0, cfg1, val; u32_t raw_pin, reg, cfg0, cfg1, val;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) { /*
* Pin must be input for interrupt to work.
* And there is no double-edge trigger according
* to datasheet.
*/
if ((flags & GPIO_INT)
&& ((flags & GPIO_DIR_OUT)
|| (flags & GPIO_INT_DOUBLE_EDGE))) {
return -EINVAL; return -EINVAL;
} }
@ -192,21 +201,24 @@ static int gpio_intel_apl_config(struct device *dev, int access_op,
return -EINVAL; return -EINVAL;
} }
extract_island_and_pin(pin, &island, &raw_pin); if (pin > cfg->num_pins) {
return -EINVAL;
}
if (!check_perm(dev, island, raw_pin)) { raw_pin = cfg->pin_offset + pin;
if (!check_perm(dev, raw_pin)) {
return -EPERM; return -EPERM;
} }
/* Set GPIO to trigger legacy interrupt */ /* Set GPIO to trigger legacy interrupt */
if (flags & GPIO_INT) { if (flags & GPIO_INT) {
reg = cfg->islands[island].reg_base + REG_PAD_HOST_SW_OWNER; reg = cfg->reg_base + REG_PAD_HOST_SW_OWNER;
sys_bitfield_set_bit(reg, raw_pin); sys_bitfield_set_bit(reg, raw_pin);
} }
/* read in pad configuration register */ /* read in pad configuration register */
reg = cfg->islands[island].reg_base reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
+ data->pad_base[island] + (raw_pin * 8);
cfg0 = sys_read32(reg); cfg0 = sys_read32(reg);
cfg1 = sys_read32(reg + 4); cfg1 = sys_read32(reg + 4);
@ -273,20 +285,23 @@ static int gpio_intel_apl_write(struct device *dev, int access_op,
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
u32_t island, raw_pin, reg, val; u32_t raw_pin, reg, val;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
extract_island_and_pin(pin, &island, &raw_pin); if (pin > cfg->num_pins) {
return -EINVAL;
}
if (!check_perm(dev, island, raw_pin)) { raw_pin = cfg->pin_offset + pin;
if (!check_perm(dev, raw_pin)) {
return -EPERM; return -EPERM;
} }
reg = cfg->islands[island].reg_base reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
+ data->pad_base[island] + (raw_pin * 8);
val = sys_read32(reg); val = sys_read32(reg);
if (value) { if (value) {
@ -305,20 +320,23 @@ static int gpio_intel_apl_read(struct device *dev, int access_op,
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
u32_t island, raw_pin, reg, val; u32_t raw_pin, reg, val;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
extract_island_and_pin(pin, &island, &raw_pin); if (pin > cfg->num_pins) {
return -EINVAL;
}
if (!check_perm(dev, island, raw_pin)) { raw_pin = cfg->pin_offset + pin;
if (!check_perm(dev, raw_pin)) {
return -EPERM; return -EPERM;
} }
reg = cfg->islands[island].reg_base reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
+ data->pad_base[island] + (raw_pin * 8);
val = sys_read32(reg); val = sys_read32(reg);
if (!(val & PAD_CFG0_TXDIS)) { if (!(val & PAD_CFG0_TXDIS)) {
@ -345,24 +363,28 @@ static int gpio_intel_apl_enable_callback(struct device *dev,
int access_op, u32_t pin) int access_op, u32_t pin)
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
u32_t island, raw_pin, reg; u32_t raw_pin, reg;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
extract_island_and_pin(pin, &island, &raw_pin); if (pin > cfg->num_pins) {
return -EINVAL;
}
if (!check_perm(dev, island, raw_pin)) { raw_pin = cfg->pin_offset + pin;
if (!check_perm(dev, raw_pin)) {
return -EPERM; return -EPERM;
} }
/* clear (by setting) interrupt status bit */ /* clear (by setting) interrupt status bit */
reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE; reg = cfg->reg_base + REG_GPI_INT_STS_BASE;
sys_bitfield_set_bit(reg, raw_pin); sys_bitfield_set_bit(reg, raw_pin);
/* enable interrupt bit */ /* enable interrupt bit */
reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE; reg = cfg->reg_base + REG_GPI_INT_EN_BASE;
sys_bitfield_set_bit(reg, raw_pin); sys_bitfield_set_bit(reg, raw_pin);
return 0; return 0;
@ -372,20 +394,24 @@ static int gpio_intel_apl_disable_callback(struct device *dev,
int access_op, u32_t pin) int access_op, u32_t pin)
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
u32_t island, raw_pin, reg; u32_t raw_pin, reg;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
extract_island_and_pin(pin, &island, &raw_pin); if (pin > cfg->num_pins) {
return -EINVAL;
}
if (!check_perm(dev, island, raw_pin)) { raw_pin = cfg->pin_offset + pin;
if (!check_perm(dev, raw_pin)) {
return -EPERM; return -EPERM;
} }
/* disable interrupt bit */ /* disable interrupt bit */
reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE; reg = cfg->reg_base + REG_GPI_INT_EN_BASE;
sys_bitfield_clear_bit(reg, raw_pin); sys_bitfield_clear_bit(reg, raw_pin);
return 0; return 0;
@ -406,62 +432,60 @@ int gpio_intel_apl_init(struct device *dev)
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
int i;
gpio_intel_apl_irq_config(dev); gpio_intel_apl_irq_config(dev);
for (i = 0; i < NUM_ISLANDS; i++) { data->pad_base = sys_read32(cfg->reg_base + REG_PAD_BASE_ADDR);
data->pad_base[i] = sys_read32(cfg->islands[i].reg_base
+ REG_PAD_BASE_ADDR);
/* Set to route interrupt through IRQ 14 */ /* Set to route interrupt through IRQ 14 */
sys_bitfield_clear_bit(data->pad_base[i] + REG_MISCCFG, sys_bitfield_clear_bit(data->pad_base + REG_MISCCFG,
MISCCFG_IRQ_ROUTE_POS); MISCCFG_IRQ_ROUTE_POS);
}
dev->driver_api = &gpio_intel_apl_api; dev->driver_api = &gpio_intel_apl_api;
return 0; return 0;
} }
static const struct gpio_intel_apl_config gpio_intel_apl_cfg = { #define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos, offset, pins) \
.islands = { static const struct gpio_intel_apl_config \
{ gpio_intel_apl_cfg_##dir_l##_##pos = { \
/* North island */ .reg_base = DT_APL_GPIO_BASE_ADDRESS_##dir_u, \
.reg_base = DT_APL_GPIO_BASE_ADDRESS_0, .pin_offset = offset, \
.num_pins = 78, .num_pins = pins, \
}, }; \
{ \
/* Northwest island */ static struct gpio_intel_apl_data gpio_intel_apl_data_##dir_l##_##pos; \
.reg_base = DT_APL_GPIO_BASE_ADDRESS_1, \
.num_pins = 77, DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \
}, DT_APL_GPIO_LABEL_##dir_u##_##pos, \
{ gpio_intel_apl_init, \
/* West island */ &gpio_intel_apl_data_##dir_l##_##pos, \
.reg_base = DT_APL_GPIO_BASE_ADDRESS_2, &gpio_intel_apl_cfg_##dir_l##_##pos, \
.num_pins = 47, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
}, &gpio_intel_apl_api)
{
/* Southwest island */
.reg_base = DT_APL_GPIO_BASE_ADDRESS_3,
.num_pins = 43,
},
},
};
static struct gpio_intel_apl_data gpio_intel_apl_data; GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 1, 32, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 2, 32, 14);
DEVICE_AND_API_INIT(gpio_intel_apl, DT_APL_GPIO_LABEL, GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 0, 0, 32);
gpio_intel_apl_init, GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 1, 32, 32);
&gpio_intel_apl_data, &gpio_intel_apl_cfg, GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 2, 32, 13);
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_intel_apl_api); GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 1, 32, 15);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 0, 0, 32);
GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 1, 32, 11);
static void gpio_intel_apl_irq_config(struct device *dev) static void gpio_intel_apl_irq_config(struct device *dev)
{ {
IRQ_CONNECT(DT_APL_GPIO_IRQ, DT_APL_GPIO_IRQ_PRIORITY, struct device *irq_dev;
gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
DT_APL_GPIO_IRQ_SENSE);
irq_enable(DT_APL_GPIO_IRQ); irq_dev = device_get_binding(DT_SHARED_IRQ_SHAREDIRQ0_LABEL);
__ASSERT(irq_dev != NULL,
"Failed to get shared IRQ device binding");
shared_irq_isr_register(irq_dev, gpio_intel_apl_isr, dev);
shared_irq_enable(irq_dev, dev);
} }

8
dts/bindings/gpio/intel,apl-gpio.yaml
View file

@ -1,5 +1,5 @@
# #
# Copyright (c) 2018 Intel Corporation # Copyright (c) 2018-2019 Intel Corporation
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #
@ -24,12 +24,6 @@ properties:
generation: define generation: define
category: required category: required
interrupts:
type: array
category: required
description: required interrupts
generation: define
label: label:
type: string type: string
category: required category: required

15
dts/x86/apollo_lake.dtsi
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2018 Intel Corporation. * Copyright (c) 2017-2019 Intel Corporation.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -50,9 +50,7 @@
<0xd0c40000 0x1000>, <0xd0c40000 0x1000>,
<0xd0c70000 0x1000>, <0xd0c70000 0x1000>,
<0xd0c00000 0x1000>; <0xd0c00000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>; label = "APL_GPIO";
interrupt-parent = <&intc>;
label = "GPIO_0";
gpio-controller ; gpio-controller ;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -60,4 +58,13 @@
status = "disabled"; status = "disabled";
}; };
}; };
sharedirq0: sharedirq0 {
compatible = "shared-irq";
label = "APL_GPIO_IRQ";
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "ok";
};
}; };

75
samples/boards/up_squared/gpio_counter/src/main.c
View file

@ -38,18 +38,40 @@
*/ */
struct _pin { struct _pin {
u32_t hat_num; u32_t hat_num;
u32_t pin; u32_t pin;
const char *gpio_dev_name;
struct device *gpio_dev;
}; };
struct _pin counter_pins[] = { struct _pin counter_pins[] = {
{ 35, UP2_HAT_PIN_35 }, {
{ 37, UP2_HAT_PIN_37 }, .hat_num = 35,
{ 38, UP2_HAT_PIN_38 }, .pin = UP2_HAT_PIN_35,
{ 40, UP2_HAT_PIN_40 }, .gpio_dev_name = UP2_HAT_PIN_35_DEV,
},
{
.hat_num = 37,
.pin = UP2_HAT_PIN_37,
.gpio_dev_name = UP2_HAT_PIN_37_DEV,
},
{
.hat_num = 38,
.pin = UP2_HAT_PIN_38,
.gpio_dev_name = UP2_HAT_PIN_38_DEV,
},
{
.hat_num = 40,
.pin = UP2_HAT_PIN_40,
.gpio_dev_name = UP2_HAT_PIN_40_DEV,
},
}; };
struct _pin intr_pin = { 16, UP2_HAT_PIN_16 }; struct _pin intr_pin = {
.hat_num = 16,
.pin = UP2_HAT_PIN_16,
.gpio_dev_name = UP2_HAT_PIN_16_DEV,
};
static struct gpio_callback gpio_cb; static struct gpio_callback gpio_cb;
@ -72,21 +94,37 @@ void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin)
k_sem_give(&counter_sem); k_sem_give(&counter_sem);
} }
int get_gpio_dev(struct _pin *pin)
{
pin->gpio_dev = device_get_binding(pin->gpio_dev_name);
if (!pin->gpio_dev) {
printk("ERROR: cannot get device binding for %s\n",
pin->gpio_dev_name);
return -1;
}
return 0;
}
void main(void) void main(void)
{ {
struct device *gpiodev = device_get_binding(GPIO_DEV);
u32_t val; u32_t val;
int i, ret; int i, ret;
if (!gpiodev) { for (i = 0; i < NUM_PINS; i++) {
printk("ERROR: cannot get device binding for %s\n", if (get_gpio_dev(&counter_pins[i]) != 0) {
GPIO_DEV); return;
}
}
if (get_gpio_dev(&intr_pin) != 0) {
return; return;
} }
/* Set pins to output */ /* Set pins to output */
for (i = 0; i < NUM_PINS; i++) { for (i = 0; i < NUM_PINS; i++) {
ret = gpio_pin_configure(gpiodev, counter_pins[i].pin, ret = gpio_pin_configure(counter_pins[i].gpio_dev,
counter_pins[i].pin,
GPIO_DIR_OUT); GPIO_DIR_OUT);
if (ret) { if (ret) {
printk("ERROR: cannot set HAT pin %d to OUT (%d)\n", printk("ERROR: cannot set HAT pin %d to OUT (%d)\n",
@ -96,16 +134,18 @@ void main(void)
} }
/* Setup input pin */ /* Setup input pin */
ret = gpio_pin_configure(gpiodev, intr_pin.pin, INTR_PIN_FLAGS); ret = gpio_pin_configure(intr_pin.gpio_dev, intr_pin.pin,
INTR_PIN_FLAGS);
if (ret) { if (ret) {
printk("ERROR: cannot set HAT pin %d to OUT (%d)\n", printk("ERROR: cannot set HAT pin %d to OUT (%d)\n",
intr_pin.hat_num, ret); intr_pin.hat_num, ret);
return; return;
} }
gpio_init_callback(&gpio_cb, button_cb, intr_pin.pin); /* Callback uses pin_mask, so need bit shifting */
gpio_add_callback(gpiodev, &gpio_cb); gpio_init_callback(&gpio_cb, button_cb, (1 << intr_pin.pin));
gpio_pin_enable_callback(gpiodev, intr_pin.pin); gpio_add_callback(intr_pin.gpio_dev, &gpio_cb);
gpio_pin_enable_callback(intr_pin.gpio_dev, intr_pin.pin);
/* main loop */ /* main loop */
val = 0U; val = 0U;
@ -113,7 +153,8 @@ void main(void)
printk("counter: 0x%x\n", val); printk("counter: 0x%x\n", val);
for (i = 0; i < NUM_PINS; i++) { for (i = 0; i < NUM_PINS; i++) {
ret = gpio_pin_write(gpiodev, counter_pins[i].pin, ret = gpio_pin_write(counter_pins[i].gpio_dev,
counter_pins[i].pin,
(val & BIT(i))); (val & BIT(i)));
if (ret) { if (ret) {
printk("ERROR: cannot set HAT pin %d value (%d)\n", printk("ERROR: cannot set HAT pin %d value (%d)\n",

11
soc/x86/apollo_lake/Kconfig.defconfig
View file

@ -1,7 +1,7 @@
# #
# Kconfig - Apollo Lake SoC configuration options # Kconfig - Apollo Lake SoC configuration options
# #
# Copyright (c) 2018 Intel Corporation # Copyright (c) 2018-2019 Intel Corporation
# Copyright (c) 2014-2015 Wind River Systems, Inc. # Copyright (c) 2014-2015 Wind River Systems, Inc.
# #
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
@ -77,6 +77,15 @@ if GPIO
config GPIO_INTEL_APL config GPIO_INTEL_APL
default y default y
config SHARED_IRQ
default y if GPIO_INTEL_APL
config SHARED_IRQ_0
default y if SHARED_IRQ
config SHARED_IRQ_NUM_CLIENTS
default 10 if SHARED_IRQ
endif # GPIO endif # GPIO
endif # SOC_APOLLO_LAKE endif # SOC_APOLLO_LAKE

69
soc/x86/apollo_lake/dts_fixup.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018 Intel Corporation Inc. * Copyright (c) 2018-2019 Intel Corporation Inc.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -14,19 +14,62 @@
#define DT_ROM_SIZE CONFIG_FLASH_SIZE #define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS #define DT_IOAPIC_BASE_ADDRESS \
DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_APL_GPIO_BASE_ADDRESS_N \
DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define DT_APL_GPIO_BASE_ADDRESS_NW \
DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define DT_APL_GPIO_BASE_ADDRESS_W \
DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define DT_APL_GPIO_BASE_ADDRESS_SW \
DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define DT_APL_GPIO_BASE_ADDRESS_0 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define DT_APL_GPIO_BASE_ADDRESS_1 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define DT_APL_GPIO_BASE_ADDRESS_2 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define DT_APL_GPIO_BASE_ADDRESS_3 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0 #define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE #define DT_APL_GPIO_IRQ_PRIORITY \
#define DT_APL_GPIO_LABEL DT_INTEL_APL_GPIO_D0C50000_LABEL DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define DT_APL_GPIO_MEM_SIZE_0 DT_INTEL_APL_GPIO_D0C50000_SIZE_0
#define DT_APL_GPIO_MEM_SIZE_1 DT_INTEL_APL_GPIO_D0C50000_SIZE_1 #define DT_APL_GPIO_IRQ_SENSE \
#define DT_APL_GPIO_MEM_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
#define DT_APL_GPIO_MEM_SIZE_3 DT_oINTEL_APL_GPIO_D0C50000_SIZE_3
#define DT_APL_GPIO_MEM_SIZE_N DT_INTEL_APL_GPIO_D0C50000_SIZE_0
#define DT_APL_GPIO_MEM_SIZE_NW DT_INTEL_APL_GPIO_D0C50000_SIZE_1
#define DT_APL_GPIO_MEM_SIZE_W DT_INTEL_APL_GPIO_D0C50000_SIZE_2
#define DT_APL_GPIO_MEM_SIZE_SW DT_INTEL_APL_GPIO_D0C50000_SIZE_3
#define DT_APL_GPIO_LABEL_N_0 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_0"
#define DT_APL_GPIO_LABEL_N_1 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_1"
#define DT_APL_GPIO_LABEL_N_2 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_N_2"
#define DT_APL_GPIO_LABEL_NW_0 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_0"
#define DT_APL_GPIO_LABEL_NW_1 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_1"
#define DT_APL_GPIO_LABEL_NW_2 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_NW_2"
#define DT_APL_GPIO_LABEL_W_0 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_0"
#define DT_APL_GPIO_LABEL_W_1 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_W_1"
#define DT_APL_GPIO_LABEL_SW_0 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_0"
#define DT_APL_GPIO_LABEL_SW_1 \
DT_INTEL_APL_GPIO_D0C50000_LABEL "_SW_1"
/* End of SoC Level DTS fixup file */ /* End of SoC Level DTS fixup file */

16
soc/x86/apollo_lake/soc.c
View file

@ -102,17 +102,17 @@ MMU_BOOT_REGION(DT_I2C_7_BASE_ADDR, 0x1000,
/* for GPIO controller */ /* for GPIO controller */
#ifdef CONFIG_GPIO_INTEL_APL #ifdef CONFIG_GPIO_INTEL_APL
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_0, MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_N,
DT_APL_GPIO_MEM_SIZE_0, DT_APL_GPIO_MEM_SIZE_N,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE)); (MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_1, MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_NW,
DT_APL_GPIO_MEM_SIZE_1, DT_APL_GPIO_MEM_SIZE_NW,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE)); (MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_2, MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_W,
DT_APL_GPIO_MEM_SIZE_2, DT_APL_GPIO_MEM_SIZE_W,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE)); (MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_3, MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_SW,
DT_APL_GPIO_MEM_SIZE_3, DT_APL_GPIO_MEM_SIZE_SW,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE)); (MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif #endif

4
soc/x86/apollo_lake/soc.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, Intel Corporation * Copyright (c) 2018-2019, Intel Corporation
* Copyright (c) 2010-2015, Wind River Systems, Inc. * Copyright (c) 2010-2015, Wind River Systems, Inc.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
@ -23,7 +23,9 @@
#include <random/rand32.h> #include <random/rand32.h>
#endif #endif
#ifdef CONFIG_GPIO_INTEL_APL
#include "soc_gpio.h" #include "soc_gpio.h"
#endif
#ifdef CONFIG_PCI #ifdef CONFIG_PCI

516
soc/x86/apollo_lake/soc_gpio.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018, Intel Corporation * Copyright (c) 2018-2019, Intel Corporation
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -15,265 +15,269 @@
#ifndef __SOC_GPIO_H_ #ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_ #define __SOC_GPIO_H_
#define APL_GPIO_N 0 #define APL_GPIO_DEV_N_0 DT_APL_GPIO_LABEL_N_0
#define APL_GPIO_NW 1 #define APL_GPIO_0 00
#define APL_GPIO_W 2 #define APL_GPIO_1 01
#define APL_GPIO_SW 3 #define APL_GPIO_2 02
#define APL_GPIO_3 03
#define APL_GPIO_4 04
#define APL_GPIO_5 05
#define APL_GPIO_6 06
#define APL_GPIO_7 07
#define APL_GPIO_8 08
#define APL_GPIO_9 09
#define APL_GPIO_10 10
#define APL_GPIO_11 11
#define APL_GPIO_12 12
#define APL_GPIO_13 13
#define APL_GPIO_14 14
#define APL_GPIO_15 15
#define APL_GPIO_16 16
#define APL_GPIO_17 17
#define APL_GPIO_18 18
#define APL_GPIO_19 19
#define APL_GPIO_20 20
#define APL_GPIO_21 21
#define APL_GPIO_22 22
#define APL_GPIO_23 23
#define APL_GPIO_24 24
#define APL_GPIO_25 25
#define APL_GPIO_26 26
#define APL_GPIO_27 27
#define APL_GPIO_28 28
#define APL_GPIO_29 29
#define APL_GPIO_30 30
#define APL_GPIO_31 31
#define APL_GPIO_ISLAND_POS 16 #define APL_GPIO_DEV_N_1 DT_APL_GPIO_LABEL_N_1
#define APL_GPIO_PIN_MASK 0xFFFF #define APL_GPIO_32 00
#define APL_GPIO_N_PREFIX (APL_GPIO_N << APL_GPIO_ISLAND_POS) #define APL_GPIO_33 01
#define APL_GPIO_NW_PREFIX (APL_GPIO_NW << APL_GPIO_ISLAND_POS) #define APL_GPIO_34 02
#define APL_GPIO_W_PREFIX (APL_GPIO_W << APL_GPIO_ISLAND_POS) #define APL_GPIO_35 03
#define APL_GPIO_SW_PREFIX (APL_GPIO_SW << APL_GPIO_ISLAND_POS) #define APL_GPIO_36 04
#define APL_GPIO_37 05
#define APL_GPIO_38 06
#define APL_GPIO_39 07
#define APL_GPIO_40 08
#define APL_GPIO_41 09
#define APL_GPIO_42 10
#define APL_GPIO_43 11
#define APL_GPIO_44 12
#define APL_GPIO_45 13
#define APL_GPIO_46 14
#define APL_GPIO_47 15
#define APL_GPIO_48 16
#define APL_GPIO_49 17
#define APL_GPIO_62 18
#define APL_GPIO_63 19
#define APL_GPIO_64 20
#define APL_GPIO_65 21
#define APL_GPIO_66 22
#define APL_GPIO_67 23
#define APL_GPIO_68 24
#define APL_GPIO_69 25
#define APL_GPIO_70 26
#define APL_GPIO_71 27
#define APL_GPIO_72 28
#define APL_GPIO_73 29
#define APL_GPIO_TCK 30
#define APL_GPIO_TRST_B 31
#define APL_GPIO_0 (00 | APL_GPIO_N_PREFIX) #define APL_GPIO_DEV_N_2 DT_APL_GPIO_LABEL_N_2
#define APL_GPIO_1 (01 | APL_GPIO_N_PREFIX) #define APL_GPIO_TMS 00
#define APL_GPIO_2 (02 | APL_GPIO_N_PREFIX) #define APL_GPIO_TDI 01
#define APL_GPIO_3 (03 | APL_GPIO_N_PREFIX) #define APL_GPIO_CX_PMODE 02
#define APL_GPIO_4 (04 | APL_GPIO_N_PREFIX) #define APL_GPIO_CX_PREQ_B 03
#define APL_GPIO_5 (05 | APL_GPIO_N_PREFIX) #define APL_GPIO_JTAGX 04
#define APL_GPIO_6 (06 | APL_GPIO_N_PREFIX) #define APL_GPIO_CX_PRDY_B 05
#define APL_GPIO_7 (07 | APL_GPIO_N_PREFIX) #define APL_GPIO_TDO 06
#define APL_GPIO_8 (08 | APL_GPIO_N_PREFIX) #define APL_GPIO_CNV_BRI_DT 07
#define APL_GPIO_9 (09 | APL_GPIO_N_PREFIX) #define APL_GPIO_CNV_BRI_RSP 08
#define APL_GPIO_10 (10 | APL_GPIO_N_PREFIX) #define APL_GPIO_CNV_RGI_DT 09
#define APL_GPIO_11 (11 | APL_GPIO_N_PREFIX) #define APL_GPIO_CNV_RGI_RSP 10
#define APL_GPIO_12 (12 | APL_GPIO_N_PREFIX) #define APL_GPIO_SVID0_ALERT_B 11
#define APL_GPIO_13 (13 | APL_GPIO_N_PREFIX) #define APL_GPIO_SVOD0_DATA 12
#define APL_GPIO_14 (14 | APL_GPIO_N_PREFIX) #define APL_GPIO_SVOD0_CLK 13
#define APL_GPIO_15 (15 | APL_GPIO_N_PREFIX)
#define APL_GPIO_16 (16 | APL_GPIO_N_PREFIX)
#define APL_GPIO_17 (17 | APL_GPIO_N_PREFIX)
#define APL_GPIO_18 (18 | APL_GPIO_N_PREFIX)
#define APL_GPIO_19 (19 | APL_GPIO_N_PREFIX)
#define APL_GPIO_20 (20 | APL_GPIO_N_PREFIX)
#define APL_GPIO_21 (21 | APL_GPIO_N_PREFIX)
#define APL_GPIO_22 (22 | APL_GPIO_N_PREFIX)
#define APL_GPIO_23 (23 | APL_GPIO_N_PREFIX)
#define APL_GPIO_24 (24 | APL_GPIO_N_PREFIX)
#define APL_GPIO_25 (25 | APL_GPIO_N_PREFIX)
#define APL_GPIO_26 (26 | APL_GPIO_N_PREFIX)
#define APL_GPIO_27 (27 | APL_GPIO_N_PREFIX)
#define APL_GPIO_28 (28 | APL_GPIO_N_PREFIX)
#define APL_GPIO_29 (29 | APL_GPIO_N_PREFIX)
#define APL_GPIO_30 (30 | APL_GPIO_N_PREFIX)
#define APL_GPIO_31 (31 | APL_GPIO_N_PREFIX)
#define APL_GPIO_32 (32 | APL_GPIO_N_PREFIX)
#define APL_GPIO_33 (33 | APL_GPIO_N_PREFIX)
#define APL_GPIO_34 (34 | APL_GPIO_N_PREFIX)
#define APL_GPIO_35 (35 | APL_GPIO_N_PREFIX)
#define APL_GPIO_36 (36 | APL_GPIO_N_PREFIX)
#define APL_GPIO_37 (37 | APL_GPIO_N_PREFIX)
#define APL_GPIO_38 (38 | APL_GPIO_N_PREFIX)
#define APL_GPIO_39 (39 | APL_GPIO_N_PREFIX)
#define APL_GPIO_40 (40 | APL_GPIO_N_PREFIX)
#define APL_GPIO_41 (41 | APL_GPIO_N_PREFIX)
#define APL_GPIO_42 (42 | APL_GPIO_N_PREFIX)
#define APL_GPIO_43 (43 | APL_GPIO_N_PREFIX)
#define APL_GPIO_44 (44 | APL_GPIO_N_PREFIX)
#define APL_GPIO_45 (45 | APL_GPIO_N_PREFIX)
#define APL_GPIO_46 (46 | APL_GPIO_N_PREFIX)
#define APL_GPIO_47 (47 | APL_GPIO_N_PREFIX)
#define APL_GPIO_48 (48 | APL_GPIO_N_PREFIX)
#define APL_GPIO_49 (49 | APL_GPIO_N_PREFIX)
#define APL_GPIO_62 (50 | APL_GPIO_N_PREFIX)
#define APL_GPIO_63 (51 | APL_GPIO_N_PREFIX)
#define APL_GPIO_64 (52 | APL_GPIO_N_PREFIX)
#define APL_GPIO_65 (53 | APL_GPIO_N_PREFIX)
#define APL_GPIO_66 (54 | APL_GPIO_N_PREFIX)
#define APL_GPIO_67 (55 | APL_GPIO_N_PREFIX)
#define APL_GPIO_68 (56 | APL_GPIO_N_PREFIX)
#define APL_GPIO_69 (57 | APL_GPIO_N_PREFIX)
#define APL_GPIO_70 (58 | APL_GPIO_N_PREFIX)
#define APL_GPIO_71 (59 | APL_GPIO_N_PREFIX)
#define APL_GPIO_72 (60 | APL_GPIO_N_PREFIX)
#define APL_GPIO_73 (61 | APL_GPIO_N_PREFIX)
#define APL_GPIO_TCK (62 | APL_GPIO_N_PREFIX)
#define APL_GPIO_TRST_B (63 | APL_GPIO_N_PREFIX)
#define APL_GPIO_TMS (64 | APL_GPIO_N_PREFIX)
#define APL_GPIO_TDI (65 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CX_PMODE (66 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CX_PREQ_B (67 | APL_GPIO_N_PREFIX)
#define APL_GPIO_JTAGX (68 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CX_PRDY_B (69 | APL_GPIO_N_PREFIX)
#define APL_GPIO_TDO (70 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CNV_BRI_DT (71 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CNV_BRI_RSP (72 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CNV_RGI_DT (73 | APL_GPIO_N_PREFIX)
#define APL_GPIO_CNV_RGI_RSP (74 | APL_GPIO_N_PREFIX)
#define APL_GPIO_SVID0_ALERT_B (75 | APL_GPIO_N_PREFIX)
#define APL_GPIO_SVOD0_DATA (76 | APL_GPIO_N_PREFIX)
#define APL_GPIO_SVOD0_CLK (77 | APL_GPIO_N_PREFIX)
#define APL_GPIO_187 (00 | APL_GPIO_NW_PREFIX) #define APL_GPIO_DEV_NW_0 DT_APL_GPIO_LABEL_NW_0
#define APL_GPIO_188 (01 | APL_GPIO_NW_PREFIX) #define APL_GPIO_187 00
#define APL_GPIO_189 (02 | APL_GPIO_NW_PREFIX) #define APL_GPIO_188 01
#define APL_GPIO_190 (03 | APL_GPIO_NW_PREFIX) #define APL_GPIO_189 02
#define APL_GPIO_191 (04 | APL_GPIO_NW_PREFIX) #define APL_GPIO_190 03
#define APL_GPIO_192 (05 | APL_GPIO_NW_PREFIX) #define APL_GPIO_191 04
#define APL_GPIO_193 (06 | APL_GPIO_NW_PREFIX) #define APL_GPIO_192 05
#define APL_GPIO_194 (07 | APL_GPIO_NW_PREFIX) #define APL_GPIO_193 06
#define APL_GPIO_195 (08 | APL_GPIO_NW_PREFIX) #define APL_GPIO_194 07
#define APL_GPIO_196 (09 | APL_GPIO_NW_PREFIX) #define APL_GPIO_195 08
#define APL_GPIO_197 (10 | APL_GPIO_NW_PREFIX) #define APL_GPIO_196 09
#define APL_GPIO_198 (11 | APL_GPIO_NW_PREFIX) #define APL_GPIO_197 10
#define APL_GPIO_199 (12 | APL_GPIO_NW_PREFIX) #define APL_GPIO_198 11
#define APL_GPIO_200 (13 | APL_GPIO_NW_PREFIX) #define APL_GPIO_199 12
#define APL_GPIO_201 (14 | APL_GPIO_NW_PREFIX) #define APL_GPIO_200 13
#define APL_GPIO_202 (15 | APL_GPIO_NW_PREFIX) #define APL_GPIO_201 14
#define APL_GPIO_203 (16 | APL_GPIO_NW_PREFIX) #define APL_GPIO_202 15
#define APL_GPIO_204 (17 | APL_GPIO_NW_PREFIX) #define APL_GPIO_203 16
#define APL_GPIO_PMC_SPI_FS0 (18 | APL_GPIO_NW_PREFIX) #define APL_GPIO_204 17
#define APL_GPIO_PMC_SPI_FS1 (19 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_FS0 18
#define APL_GPIO_PMC_SPI_FS2 (20 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_FS1 19
#define APL_GPIO_PMC_SPI_RXD (21 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_FS2 20
#define APL_GPIO_PMC_SPI_TXC (22 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_RXD 21
#define APL_GPIO_PMC_SPI_CLK (23 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_TXC 22
#define APL_GPIO_PMIC_PWRGOOD (24 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMC_SPI_CLK 23
#define APL_GPIO_PMIC_RESET_B (25 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMIC_PWRGOOD 24
#define APL_GPIO_213 (26 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMIC_RESET_B 25
#define APL_GPIO_214 (27 | APL_GPIO_NW_PREFIX) #define APL_GPIO_213 26
#define APL_GPIO_215 (28 | APL_GPIO_NW_PREFIX) #define APL_GPIO_214 27
#define APL_GPIO_PMIC_THERMTRIP_B (29 | APL_GPIO_NW_PREFIX) #define APL_GPIO_215 28
#define APL_GPIO_PMIC_STDBY (30 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMIC_THERMTRIP_B 29
#define APL_GPIO_PROCHOT_B (31 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PMIC_STDBY 30
#define APL_GPIO_PMIC_I2C_SCL (32 | APL_GPIO_NW_PREFIX) #define APL_GPIO_PROCHOT_B 31
#define APL_GPIO_PMIC_I2C_SDA (33 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_74 (34 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_75 (35 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_76 (36 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_77 (37 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_78 (38 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_79 (39 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_80 (40 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_81 (41 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_82 (42 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_83 (43 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_84 (44 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_85 (45 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_86 (46 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_87 (47 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_88 (48 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_89 (49 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_90 (50 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_91 (51 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_92 (52 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_97 (53 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_98 (54 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_99 (55 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_100 (56 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_101 (57 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_102 (58 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_103 (59 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_FST_SPI_CLK_FB (60 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_104 (61 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_105 (62 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_106 (63 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_109 (64 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_110 (65 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_111 (66 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_112 (67 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_113 (68 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_116 (69 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_117 (70 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_118 (71 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_119 (72 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_120 (73 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_121 (74 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_122 (75 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_123 (76 | APL_GPIO_NW_PREFIX)
#define APL_GPIO_124 (00 | APL_GPIO_W_PREFIX) #define APL_GPIO_DEV_NW_1 DT_APL_GPIO_LABEL_NW_1
#define APL_GPIO_125 (01 | APL_GPIO_W_PREFIX) #define APL_GPIO_PMIC_I2C_SCL 00
#define APL_GPIO_126 (02 | APL_GPIO_W_PREFIX) #define APL_GPIO_PMIC_I2C_SDA 01
#define APL_GPIO_127 (03 | APL_GPIO_W_PREFIX) #define APL_GPIO_74 02
#define APL_GPIO_128 (04 | APL_GPIO_W_PREFIX) #define APL_GPIO_75 03
#define APL_GPIO_129 (05 | APL_GPIO_W_PREFIX) #define APL_GPIO_76 04
#define APL_GPIO_130 (06 | APL_GPIO_W_PREFIX) #define APL_GPIO_77 05
#define APL_GPIO_131 (07 | APL_GPIO_W_PREFIX) #define APL_GPIO_78 06
#define APL_GPIO_132 (08 | APL_GPIO_W_PREFIX) #define APL_GPIO_79 07
#define APL_GPIO_133 (09 | APL_GPIO_W_PREFIX) #define APL_GPIO_80 08
#define APL_GPIO_134 (10 | APL_GPIO_W_PREFIX) #define APL_GPIO_81 09
#define APL_GPIO_135 (11 | APL_GPIO_W_PREFIX) #define APL_GPIO_82 10
#define APL_GPIO_136 (12 | APL_GPIO_W_PREFIX) #define APL_GPIO_83 11
#define APL_GPIO_137 (13 | APL_GPIO_W_PREFIX) #define APL_GPIO_84 12
#define APL_GPIO_138 (14 | APL_GPIO_W_PREFIX) #define APL_GPIO_85 13
#define APL_GPIO_139 (15 | APL_GPIO_W_PREFIX) #define APL_GPIO_86 14
#define APL_GPIO_146 (16 | APL_GPIO_W_PREFIX) #define APL_GPIO_87 15
#define APL_GPIO_147 (17 | APL_GPIO_W_PREFIX) #define APL_GPIO_88 16
#define APL_GPIO_148 (18 | APL_GPIO_W_PREFIX) #define APL_GPIO_89 17
#define APL_GPIO_149 (19 | APL_GPIO_W_PREFIX) #define APL_GPIO_90 18
#define APL_GPIO_150 (20 | APL_GPIO_W_PREFIX) #define APL_GPIO_91 19
#define APL_GPIO_151 (21 | APL_GPIO_W_PREFIX) #define APL_GPIO_92 20
#define APL_GPIO_152 (22 | APL_GPIO_W_PREFIX) #define APL_GPIO_97 21
#define APL_GPIO_153 (23 | APL_GPIO_W_PREFIX) #define APL_GPIO_98 22
#define APL_GPIO_154 (24 | APL_GPIO_W_PREFIX) #define APL_GPIO_99 23
#define APL_GPIO_155 (25 | APL_GPIO_W_PREFIX) #define APL_GPIO_100 24
#define APL_GPIO_209 (26 | APL_GPIO_W_PREFIX) #define APL_GPIO_101 25
#define APL_GPIO_210 (27 | APL_GPIO_W_PREFIX) #define APL_GPIO_102 26
#define APL_GPIO_211 (28 | APL_GPIO_W_PREFIX) #define APL_GPIO_103 27
#define APL_GPIO_212 (29 | APL_GPIO_W_PREFIX) #define APL_GPIO_FST_SPI_CLK_FB 28
#define APL_GPIO_OSC_CLK_OUT_0 (30 | APL_GPIO_W_PREFIX) #define APL_GPIO_104 29
#define APL_GPIO_OSC_CLK_OUT_1 (31 | APL_GPIO_W_PREFIX) #define APL_GPIO_105 30
#define APL_GPIO_OSC_CLK_OUT_2 (32 | APL_GPIO_W_PREFIX) #define APL_GPIO_106 31
#define APL_GPIO_OSC_CLK_OUT_3 (33 | APL_GPIO_W_PREFIX)
#define APL_GPIO_OSC_CLK_OUT_4 (34 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_AC_PRESENT (35 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_BATLOW_B (36 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_PLTRST_B (37 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_PWRBTN_B (38 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_RESETBUTTON_B (39 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_SLP_S0_B (40 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_SLP_S3_B (41 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_SLP_S4_B (42 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_SUSCLK (43 | APL_GPIO_W_PREFIX)
#define APL_GPIO_PMU_WAKE_B (44 | APL_GPIO_W_PREFIX)
#define APL_GPIO_SUS_STAT_B (45 | APL_GPIO_W_PREFIX)
#define APL_GPIO_SUSPWRDNACK (46 | APL_GPIO_W_PREFIX)
#define APL_GPIO_205 (00 | APL_GPIO_SW_PREFIX) #define APL_GPIO_DEV_NW_2 DT_APL_GPIO_LABEL_NW_2
#define APL_GPIO_206 (01 | APL_GPIO_SW_PREFIX) #define APL_GPIO_109 00
#define APL_GPIO_207 (02 | APL_GPIO_SW_PREFIX) #define APL_GPIO_110 01
#define APL_GPIO_208 (03 | APL_GPIO_SW_PREFIX) #define APL_GPIO_111 02
#define APL_GPIO_156 (04 | APL_GPIO_SW_PREFIX) #define APL_GPIO_112 03
#define APL_GPIO_157 (05 | APL_GPIO_SW_PREFIX) #define APL_GPIO_113 04
#define APL_GPIO_158 (06 | APL_GPIO_SW_PREFIX) #define APL_GPIO_116 05
#define APL_GPIO_159 (07 | APL_GPIO_SW_PREFIX) #define APL_GPIO_117 06
#define APL_GPIO_160 (08 | APL_GPIO_SW_PREFIX) #define APL_GPIO_118 07
#define APL_GPIO_161 (09 | APL_GPIO_SW_PREFIX) #define APL_GPIO_119 08
#define APL_GPIO_162 (10 | APL_GPIO_SW_PREFIX) #define APL_GPIO_120 09
#define APL_GPIO_163 (11 | APL_GPIO_SW_PREFIX) #define APL_GPIO_121 10
#define APL_GPIO_164 (12 | APL_GPIO_SW_PREFIX) #define APL_GPIO_122 11
#define APL_GPIO_165 (13 | APL_GPIO_SW_PREFIX) #define APL_GPIO_123 12
#define APL_GPIO_166 (14 | APL_GPIO_SW_PREFIX)
#define APL_GPIO_167 (15 | APL_GPIO_SW_PREFIX) #define APL_GPIO_DEV_W_0 DT_APL_GPIO_LABEL_W_0
#define APL_GPIO_168 (16 | APL_GPIO_SW_PREFIX) #define APL_GPIO_124 00
#define APL_GPIO_169 (17 | APL_GPIO_SW_PREFIX) #define APL_GPIO_125 01
#define APL_GPIO_170 (18 | APL_GPIO_SW_PREFIX) #define APL_GPIO_126 02
#define APL_GPIO_171 (19 | APL_GPIO_SW_PREFIX) #define APL_GPIO_127 03
#define APL_GPIO_172 (20 | APL_GPIO_SW_PREFIX) #define APL_GPIO_128 04
#define APL_GPIO_179 (21 | APL_GPIO_SW_PREFIX) #define APL_GPIO_129 05
#define APL_GPIO_173 (22 | APL_GPIO_SW_PREFIX) #define APL_GPIO_130 06
#define APL_GPIO_174 (23 | APL_GPIO_SW_PREFIX) #define APL_GPIO_131 07
#define APL_GPIO_175 (24 | APL_GPIO_SW_PREFIX) #define APL_GPIO_132 08
#define APL_GPIO_176 (25 | APL_GPIO_SW_PREFIX) #define APL_GPIO_133 09
#define APL_GPIO_177 (26 | APL_GPIO_SW_PREFIX) #define APL_GPIO_134 10
#define APL_GPIO_178 (27 | APL_GPIO_SW_PREFIX) #define APL_GPIO_135 11
#define APL_GPIO_186 (28 | APL_GPIO_SW_PREFIX) #define APL_GPIO_136 12
#define APL_GPIO_182 (29 | APL_GPIO_SW_PREFIX) #define APL_GPIO_137 13
#define APL_GPIO_183 (30 | APL_GPIO_SW_PREFIX) #define APL_GPIO_138 14
#define APL_GPIO_SMB_ALERTB (31 | APL_GPIO_SW_PREFIX) #define APL_GPIO_139 15
#define APL_GPIO_SMB_CLK (32 | APL_GPIO_SW_PREFIX) #define APL_GPIO_146 16
#define APL_GPIO_SMB_DATA (33 | APL_GPIO_SW_PREFIX) #define APL_GPIO_147 17
#define APL_GPIO_LPC_ILB_SERIRQ (34 | APL_GPIO_SW_PREFIX) #define APL_GPIO_148 18
#define APL_GPIO_LPC_CLKOUT0 (35 | APL_GPIO_SW_PREFIX) #define APL_GPIO_149 19
#define APL_GPIO_LPC_CLKOUT1 (36 | APL_GPIO_SW_PREFIX) #define APL_GPIO_150 20
#define APL_GPIO_LPC_AD0 (37 | APL_GPIO_SW_PREFIX) #define APL_GPIO_151 21
#define APL_GPIO_LPC_AD1 (38 | APL_GPIO_SW_PREFIX) #define APL_GPIO_152 22
#define APL_GPIO_LPC_AD2 (39 | APL_GPIO_SW_PREFIX) #define APL_GPIO_153 23
#define APL_GPIO_LPC_AD3 (40 | APL_GPIO_SW_PREFIX) #define APL_GPIO_154 24
#define APL_GPIO_LPC_CLKRUNB (41 | APL_GPIO_SW_PREFIX) #define APL_GPIO_155 25
#define APL_GPIO_LPC_FRAMEB (42 | APL_GPIO_SW_PREFIX) #define APL_GPIO_209 26
#define APL_GPIO_210 27
#define APL_GPIO_211 28
#define APL_GPIO_212 29
#define APL_GPIO_OSC_CLK_OUT_0 30
#define APL_GPIO_OSC_CLK_OUT_1 31
#define APL_GPIO_DEV_W_1 DT_APL_GPIO_LABEL_W_1
#define APL_GPIO_OSC_CLK_OUT_2 00
#define APL_GPIO_OSC_CLK_OUT_3 01
#define APL_GPIO_OSC_CLK_OUT_4 02
#define APL_GPIO_PMU_AC_PRESENT 03
#define APL_GPIO_PMU_BATLOW_B 04
#define APL_GPIO_PMU_PLTRST_B 05
#define APL_GPIO_PMU_PWRBTN_B 06
#define APL_GPIO_PMU_RESETBUTTON_B 07
#define APL_GPIO_PMU_SLP_S0_B 08
#define APL_GPIO_PMU_SLP_S3_B 09
#define APL_GPIO_PMU_SLP_S4_B 10
#define APL_GPIO_PMU_SUSCLK 11
#define APL_GPIO_PMU_WAKE_B 12
#define APL_GPIO_SUS_STAT_B 13
#define APL_GPIO_SUSPWRDNACK 14
#define APL_GPIO_DEV_SW_0 DT_APL_GPIO_LABEL_SW_0
#define APL_GPIO_205 00
#define APL_GPIO_206 01
#define APL_GPIO_207 02
#define APL_GPIO_208 03
#define APL_GPIO_156 04
#define APL_GPIO_157 05
#define APL_GPIO_158 06
#define APL_GPIO_159 07
#define APL_GPIO_160 08
#define APL_GPIO_161 09
#define APL_GPIO_162 10
#define APL_GPIO_163 11
#define APL_GPIO_164 12
#define APL_GPIO_165 13
#define APL_GPIO_166 14
#define APL_GPIO_167 15
#define APL_GPIO_168 16
#define APL_GPIO_169 17
#define APL_GPIO_170 18
#define APL_GPIO_171 19
#define APL_GPIO_172 20
#define APL_GPIO_179 21
#define APL_GPIO_173 22
#define APL_GPIO_174 23
#define APL_GPIO_175 24
#define APL_GPIO_176 25
#define APL_GPIO_177 26
#define APL_GPIO_178 27
#define APL_GPIO_186 28
#define APL_GPIO_182 29
#define APL_GPIO_183 30
#define APL_GPIO_SMB_ALERTB 31
#define APL_GPIO_DEV_SW_1 DT_APL_GPIO_LABEL_SW_1
#define APL_GPIO_SMB_CLK 00
#define APL_GPIO_SMB_DATA 01
#define APL_GPIO_LPC_ILB_SERIRQ 02
#define APL_GPIO_LPC_CLKOUT0 03
#define APL_GPIO_LPC_CLKOUT1 04
#define APL_GPIO_LPC_AD0 05
#define APL_GPIO_LPC_AD1 06
#define APL_GPIO_LPC_AD2 07
#define APL_GPIO_LPC_AD3 08
#define APL_GPIO_LPC_CLKRUNB 09
#define APL_GPIO_LPC_FRAMEB 10
#endif /* __SOC_GPIO_H_ */ #endif /* __SOC_GPIO_H_ */