michaelh/zephyr
1
0
Fork 0
Code Releases Activity

gpio: intel_apl: rework driver for pin_mask callback

Browse source 
To avoid confusion, callbacks using ordinal pin numbers
is going to be reverted. So the driver has to be re-worked
to expose multiple devices so each device has 32 pins.

Also fixes #12765

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2019-01-29 19:34:41 -08:00 • committed by Anas Nashif
commit f7a42a70f8
10 changed files with 619 additions and 440 deletions
Download patch file Download diff file Expand all files Collapse all files

16
soc/x86/apollo_lake/soc.c
View file

@ -102,17 +102,17 @@ MMU_BOOT_REGION(DT_I2C_7_BASE_ADDR, 0x1000,
/* for GPIO controller */
#ifdef CONFIG_GPIO_INTEL_APL
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_0,
DT_APL_GPIO_MEM_SIZE_0,
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_N,
DT_APL_GPIO_MEM_SIZE_N,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_1,
DT_APL_GPIO_MEM_SIZE_1,
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_NW,
DT_APL_GPIO_MEM_SIZE_NW,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_2,
DT_APL_GPIO_MEM_SIZE_2,
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_W,
DT_APL_GPIO_MEM_SIZE_W,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_3,
DT_APL_GPIO_MEM_SIZE_3,
MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_SW,
DT_APL_GPIO_MEM_SIZE_SW,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif